src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "vl/vl_decoder.h"
  28 #include "vl/vl_video_buffer.h"
  29
  30 #include "nouveau_vp3_video.h"
  31
  32 #include "nvc0/nvc0_context.h"
  33 #include "nvc0/nvc0_screen.h"
  34
  35 #include "nvc0/nvc0_graph_macros.h"
  36
  37 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  38 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  39 #endif
  40
  41 static boolean
  42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  43                                 enum pipe_format format,
  44                                 enum pipe_texture_target target,
  45                                 unsigned sample_count,
  46                                 unsigned bindings)
  47 {
  48    if (sample_count > 8)
  49       return FALSE;
  50    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  51       return FALSE;
  52
  53    if (!util_format_is_supported(format, bindings))
  54       return FALSE;
  55
  56    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  57       if (util_format_get_blocksizebits(format) == 3 * 32)
  58          return FALSE;
  59
  60    /* transfers & shared are always supported */
  61    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  62                  PIPE_BIND_TRANSFER_WRITE |
  63                  PIPE_BIND_SHARED);
  64
  65    return (nvc0_format_table[format].usage & bindings) == bindings;
  66 }
  67
  68 static int
  69 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  70 {
  71    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  72
  73    switch (param) {
  74    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  75    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  76       return 15;
  77    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  78       return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
  79    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  80       return 2048;
  81    case PIPE_CAP_MIN_TEXEL_OFFSET:
  82       return -8;
  83    case PIPE_CAP_MAX_TEXEL_OFFSET:
  84       return 7;
  85    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  86    case PIPE_CAP_TEXTURE_SWIZZLE:
  87    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  88    case PIPE_CAP_NPOT_TEXTURES:
  89    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  90    case PIPE_CAP_ANISOTROPIC_FILTER:
  91    case PIPE_CAP_SEAMLESS_CUBE_MAP:
  92    case PIPE_CAP_CUBE_MAP_ARRAY:
  93    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  94    case PIPE_CAP_TEXTURE_MULTISAMPLE:
  95       return 1;
  96    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
  97       return 65536;
  98    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  99       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 100    case PIPE_CAP_TWO_SIDED_STENCIL:
 101    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 102    case PIPE_CAP_POINT_SPRITE:
 103    case PIPE_CAP_TGSI_TEXCOORD:
 104       return 1;
 105    case PIPE_CAP_SM3:
 106       return 1;
 107    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 108       return 330;
 109    case PIPE_CAP_MAX_RENDER_TARGETS:
 110       return 8;
 111    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 112       return 1;
 113    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 114    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 115    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 116       return 1;
 117    case PIPE_CAP_QUERY_TIMESTAMP:
 118    case PIPE_CAP_QUERY_TIME_ELAPSED:
 119    case PIPE_CAP_OCCLUSION_QUERY:
 120    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 121    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 122       return 1;
 123    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 124       return 4;
 125    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 126    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 127       return 128;
 128    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 129    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 130       return 1024;
 131    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 132    case PIPE_CAP_INDEP_BLEND_ENABLE:
 133    case PIPE_CAP_INDEP_BLEND_FUNC:
 134       return 1;
 135    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 136    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 137       return 1;
 138    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 139    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 140       return 0;
 141    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 142       return 0;
 143    case PIPE_CAP_PRIMITIVE_RESTART:
 144    case PIPE_CAP_TGSI_INSTANCEID:
 145    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 146    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 147    case PIPE_CAP_CONDITIONAL_RENDER:
 148    case PIPE_CAP_TEXTURE_BARRIER:
 149    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 150    case PIPE_CAP_START_INSTANCE:
 151       return 1;
 152    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 153       return 0; /* state trackers will know better */
 154    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 155    case PIPE_CAP_USER_INDEX_BUFFERS:
 156    case PIPE_CAP_USER_VERTEX_BUFFERS:
 157       return 1;
 158    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 159       return 256;
 160    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 161       return 1; /* 256 for binding as RT, but that's not possible in GL */
 162    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 163       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 164    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 165    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 166    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 167       return 0;
 168    case PIPE_CAP_COMPUTE:
 169       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 170    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 171       return 1;
 172    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 173       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 174    case PIPE_CAP_ENDIANNESS:
 175       return PIPE_ENDIAN_LITTLE;
 176    case PIPE_CAP_TGSI_VS_LAYER:
 177    case PIPE_CAP_TEXTURE_GATHER_SM5:
 178    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 179    case PIPE_CAP_FAKE_SW_MSAA:
 180       return 0;
 181    case PIPE_CAP_MAX_VIEWPORTS:
 182       return 1;
 183    case PIPE_CAP_TEXTURE_QUERY_LOD:
 184       return 1;
 185    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 186       return 4;
 187    default:
 188       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 189       return 0;
 190    }
 191 }
 192
 193 static int
 194 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 195                              enum pipe_shader_cap param)
 196 {
 197    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 198
 199    switch (shader) {
 200    case PIPE_SHADER_VERTEX:
 201       /*
 202    case PIPE_SHADER_TESSELLATION_CONTROL:
 203    case PIPE_SHADER_TESSELLATION_EVALUATION:
 204       */
 205    case PIPE_SHADER_GEOMETRY:
 206    case PIPE_SHADER_FRAGMENT:
 207       break;
 208    case PIPE_SHADER_COMPUTE:
 209       if (class_3d < NVE4_3D_CLASS)
 210          return 0;
 211       break;
 212    default:
 213       return 0;
 214    }
 215
 216    switch (param) {
 217    case PIPE_SHADER_CAP_PREFERRED_IR:
 218       return PIPE_SHADER_IR_TGSI;
 219    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 220    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 221    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 222    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 223       return 16384;
 224    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 225       return 16;
 226    case PIPE_SHADER_CAP_MAX_INPUTS:
 227       if (shader == PIPE_SHADER_VERTEX)
 228          return 32;
 229       /* NOTE: These only count our slots for GENERIC varyings.
 230        * The address space may be larger, but the actual hard limit seems to be
 231        * less than what the address space layout permits, so don't add TEXCOORD,
 232        * COLOR, etc. here.
 233        */
 234       if (shader == PIPE_SHADER_FRAGMENT)
 235          return 0x1f0 / 16;
 236       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 237        * and excludes 0x60 per-patch inputs.
 238        */
 239       return 0x200 / 16;
 240    case PIPE_SHADER_CAP_MAX_CONSTS:
 241       return 65536 / 16;
 242    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 243       if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
 244          return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
 245       return NVC0_MAX_PIPE_CONSTBUFS;
 246    case PIPE_SHADER_CAP_MAX_ADDRS:
 247       return 1;
 248    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 249    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 250       return shader != PIPE_SHADER_FRAGMENT;
 251    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 252    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 253       return 1;
 254    case PIPE_SHADER_CAP_MAX_PREDS:
 255       return 0;
 256    case PIPE_SHADER_CAP_MAX_TEMPS:
 257       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 258    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 259       return 1;
 260    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 261       return 0;
 262    case PIPE_SHADER_CAP_SUBROUTINES:
 263       return 1;
 264    case PIPE_SHADER_CAP_INTEGERS:
 265       return 1;
 266    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 267       return 16; /* would be 32 in linked (OpenGL-style) mode */
 268    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 269       return 16; /* XXX not sure if more are really safe */
 270    default:
 271       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 272       return 0;
 273    }
 274 }
 275
 276 static float
 277 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 278 {
 279    switch (param) {
 280    case PIPE_CAPF_MAX_LINE_WIDTH:
 281    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 282       return 10.0f;
 283    case PIPE_CAPF_MAX_POINT_WIDTH:
 284       return 63.0f;
 285    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 286       return 63.375f;
 287    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 288       return 16.0f;
 289    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 290       return 15.0f;
 291    default:
 292       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 293       return 0.0f;
 294    }
 295 }
 296
 297 static int
 298 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 299                               enum pipe_compute_cap param, void *data)
 300 {
 301    uint64_t *data64 = (uint64_t *)data;
 302    const uint16_t obj_class = nvc0_screen(pscreen)->compute->oclass;
 303
 304    switch (param) {
 305    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 306       data64[0] = 3;
 307       return 8;
 308    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 309       data64[0] = (obj_class >= NVE4_COMPUTE_CLASS) ? 0x7fffffff : 65535;
 310       data64[1] = 65535;
 311       data64[2] = 65535;
 312       return 24;
 313    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 314       data64[0] = 1024;
 315       data64[1] = 1024;
 316       data64[2] = 64;
 317       return 24;
 318    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 319       data64[0] = 1024;
 320       return 8;
 321    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 322       data64[0] = (uint64_t)1 << 40;
 323       return 8;
 324    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 325       data64[0] = 48 << 10;
 326       return 8;
 327    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 328       data64[0] = 512 << 10;
 329       return 8;
 330    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 331       data64[0] = 4096;
 332       return 8;
 333    default:
 334       return 0;
 335    }
 336 }
 337
 338 static void
 339 nvc0_screen_destroy(struct pipe_screen *pscreen)
 340 {
 341    struct nvc0_screen *screen = nvc0_screen(pscreen);
 342
 343    if (!nouveau_drm_screen_unref(&screen->base))
 344       return;
 345
 346    if (screen->base.fence.current) {
 347       struct nouveau_fence *current = NULL;
 348
 349       /* nouveau_fence_wait will create a new current fence, so wait on the
 350        * _current_ one, and remove both.
 351        */
 352       nouveau_fence_ref(screen->base.fence.current, &current);
 353       nouveau_fence_wait(current);
 354       nouveau_fence_ref(NULL, &current);
 355       nouveau_fence_ref(NULL, &screen->base.fence.current);
 356    }
 357    if (screen->base.pushbuf)
 358       screen->base.pushbuf->user_priv = NULL;
 359
 360    if (screen->blitter)
 361       nvc0_blitter_destroy(screen);
 362    if (screen->pm.prog) {
 363       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 364       nvc0_program_destroy(NULL, screen->pm.prog);
 365    }
 366
 367    nouveau_bo_ref(NULL, &screen->text);
 368    nouveau_bo_ref(NULL, &screen->uniform_bo);
 369    nouveau_bo_ref(NULL, &screen->tls);
 370    nouveau_bo_ref(NULL, &screen->txc);
 371    nouveau_bo_ref(NULL, &screen->fence.bo);
 372    nouveau_bo_ref(NULL, &screen->poly_cache);
 373    nouveau_bo_ref(NULL, &screen->parm);
 374
 375    nouveau_heap_destroy(&screen->lib_code);
 376    nouveau_heap_destroy(&screen->text_heap);
 377
 378    FREE(screen->tic.entries);
 379
 380    nouveau_mm_destroy(screen->mm_VRAM_fe0);
 381
 382    nouveau_object_del(&screen->eng3d);
 383    nouveau_object_del(&screen->eng2d);
 384    nouveau_object_del(&screen->m2mf);
 385    nouveau_object_del(&screen->compute);
 386    nouveau_object_del(&screen->nvsw);
 387
 388    nouveau_screen_fini(&screen->base);
 389
 390    FREE(screen);
 391 }
 392
 393 static int
 394 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 395                      unsigned size, const uint32_t *data)
 396 {
 397    struct nouveau_pushbuf *push = screen->base.pushbuf;
 398
 399    size /= 4;
 400
 401    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 402    PUSH_DATA (push, (m - 0x3800) / 8);
 403    PUSH_DATA (push, pos);
 404    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 405    PUSH_DATA (push, pos);
 406    PUSH_DATAp(push, data, size);
 407
 408    return pos + size;
 409 }
 410
 411 static void
 412 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 413 {
 414    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 415    PUSH_DATA (push, 0xff);
 416    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 417    PUSH_DATA (push, 0xff);
 418    PUSH_DATA (push, 0xff);
 419    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 420    PUSH_DATA (push, 0xff);
 421    PUSH_DATA (push, 0xff);
 422    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 423    PUSH_DATA (push, 0x3f);
 424
 425    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 426    PUSH_DATA (push, (3 << 16) | 3);
 427    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 428    PUSH_DATA (push, (2 << 16) | 2);
 429    BEGIN_NVC0(push, SUBC_3D(0x0de8), 1);
 430    PUSH_DATA (push, 1);
 431
 432    BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 433    PUSH_DATA (push, 0);
 434    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 435    PUSH_DATA (push, 0x10);
 436    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 437    PUSH_DATA (push, 0x10);
 438    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 439    PUSH_DATA (push, 0x10);
 440    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 441    PUSH_DATA (push, 0x10);
 442    PUSH_DATA (push, 0x10);
 443    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 444    PUSH_DATA (push, 0x10);
 445    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 446    PUSH_DATA (push, 0xe);
 447
 448    BEGIN_NVC0(push, SUBC_3D(0x164c), 1);
 449    PUSH_DATA (push, 1 << 12);
 450    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 451    PUSH_DATA (push, 0);
 452    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 453    PUSH_DATA (push, 3);
 454
 455    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 456    PUSH_DATA (push, 0x3fffff);
 457    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 458    PUSH_DATA (push, 1);
 459    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 460    PUSH_DATA (push, 1);
 461    BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 462    PUSH_DATA (push, 3);
 463
 464    if (obj_class >= NVE4_3D_CLASS) {
 465       BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 466       PUSH_DATA (push, 1);
 467    }
 468
 469    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 470     * are supposed to do */
 471 }
 472
 473 static void
 474 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 475 {
 476    struct nvc0_screen *screen = nvc0_screen(pscreen);
 477    struct nouveau_pushbuf *push = screen->base.pushbuf;
 478
 479    /* we need to do it after possible flush in MARK_RING */
 480    *sequence = ++screen->base.fence.sequence;
 481
 482    BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4);
 483    PUSH_DATAh(push, screen->fence.bo->offset);
 484    PUSH_DATA (push, screen->fence.bo->offset);
 485    PUSH_DATA (push, *sequence);
 486    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 487               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 488 }
 489
 490 static u32
 491 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 492 {
 493    struct nvc0_screen *screen = nvc0_screen(pscreen);
 494    return screen->fence.map[0];
 495 }
 496
 497 static int
 498 nvc0_screen_init_compute(struct nvc0_screen *screen)
 499 {
 500    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 501
 502    switch (screen->base.device->chipset & ~0xf) {
 503    case 0xc0:
 504    case 0xd0:
 505       /* Using COMPUTE has weird effects on 3D state, we need to
 506        * investigate this further before enabling it by default.
 507        */
 508       if (debug_get_bool_option("NVC0_COMPUTE", FALSE))
 509          return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 510       return 0;
 511    case 0xe0:
 512    case 0xf0:
 513    case 0x100:
 514       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 515    default:
 516       return -1;
 517    }
 518 }
 519
 520 boolean
 521 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 522                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 523 {
 524    struct nouveau_bo *bo = NULL;
 525    int ret;
 526    uint64_t size = (lpos + lneg) * 32 + cstack;
 527
 528    if (size >= (1 << 20)) {
 529       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 530       return FALSE;
 531    }
 532
 533    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 534    size  = align(size, 0x8000);
 535    size *= screen->mp_count;
 536
 537    size = align(size, 1 << 17);
 538
 539    ret = nouveau_bo_new(screen->base.device, NOUVEAU_BO_VRAM, 1 << 17, size,
 540                         NULL, &bo);
 541    if (ret) {
 542       NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
 543       return FALSE;
 544    }
 545    nouveau_bo_ref(NULL, &screen->tls);
 546    screen->tls = bo;
 547    return TRUE;
 548 }
 549
 550 #define FAIL_SCREEN_INIT(str, err)                    \
 551    do {                                               \
 552       NOUVEAU_ERR(str, err);                          \
 553       nvc0_screen_destroy(pscreen);                   \
 554       return NULL;                                    \
 555    } while(0)
 556
 557 struct pipe_screen *
 558 nvc0_screen_create(struct nouveau_device *dev)
 559 {
 560    struct nvc0_screen *screen;
 561    struct pipe_screen *pscreen;
 562    struct nouveau_object *chan;
 563    struct nouveau_pushbuf *push;
 564    uint64_t value;
 565    uint32_t obj_class;
 566    int ret;
 567    unsigned i;
 568    union nouveau_bo_config mm_config;
 569
 570    switch (dev->chipset & ~0xf) {
 571    case 0xc0:
 572    case 0xd0:
 573    case 0xe0:
 574    case 0xf0:
 575    case 0x100:
 576       break;
 577    default:
 578       return NULL;
 579    }
 580
 581    screen = CALLOC_STRUCT(nvc0_screen);
 582    if (!screen)
 583       return NULL;
 584    pscreen = &screen->base.base;
 585
 586    ret = nouveau_screen_init(&screen->base, dev);
 587    if (ret) {
 588       nvc0_screen_destroy(pscreen);
 589       return NULL;
 590    }
 591    chan = screen->base.channel;
 592    push = screen->base.pushbuf;
 593    push->user_priv = screen;
 594    push->rsvd_kick = 5;
 595
 596    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 597       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 598    screen->base.sysmem_bindings |=
 599       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 600
 601    pscreen->destroy = nvc0_screen_destroy;
 602    pscreen->context_create = nvc0_create;
 603    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 604    pscreen->get_param = nvc0_screen_get_param;
 605    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 606    pscreen->get_paramf = nvc0_screen_get_paramf;
 607    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 608
 609    nvc0_screen_init_resource_functions(pscreen);
 610
 611    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 612    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 613
 614    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL,
 615                         &screen->fence.bo);
 616    if (ret)
 617       goto fail;
 618    nouveau_bo_map(screen->fence.bo, 0, NULL);
 619    screen->fence.map = screen->fence.bo->map;
 620    screen->base.fence.emit = nvc0_screen_fence_emit;
 621    screen->base.fence.update = nvc0_screen_fence_update;
 622
 623
 624    ret = nouveau_object_new(chan,
 625                             (dev->chipset < 0xe0) ? 0x1f906e : 0x906e, 0x906e,
 626                             NULL, 0, &screen->nvsw);
 627    if (ret)
 628       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 629
 630
 631    switch (dev->chipset & ~0xf) {
 632    case 0x100:
 633    case 0xf0:
 634       obj_class = NVF0_P2MF_CLASS;
 635       break;
 636    case 0xe0:
 637       obj_class = NVE4_P2MF_CLASS;
 638       break;
 639    default:
 640       obj_class = NVC0_M2MF_CLASS;
 641       break;
 642    }
 643    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 644                             &screen->m2mf);
 645    if (ret)
 646       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 647
 648    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 649    PUSH_DATA (push, screen->m2mf->oclass);
 650    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 651       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 652       PUSH_DATA (push, 0xa0b5);
 653    }
 654
 655    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 656                             &screen->eng2d);
 657    if (ret)
 658       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 659
 660    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 661    PUSH_DATA (push, screen->eng2d->oclass);
 662    BEGIN_NVC0(push, NVC0_2D(SINGLE_GPC), 1);
 663    PUSH_DATA (push, 0);
 664    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 665    PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY);
 666    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 667    PUSH_DATA (push, 0);
 668    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 669    PUSH_DATA (push, 0);
 670    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 671    PUSH_DATA (push, 0x3f);
 672    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 673    PUSH_DATA (push, 1);
 674
 675    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 676    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 677    PUSH_DATA (push, screen->fence.bo->offset + 16);
 678
 679    switch (dev->chipset & ~0xf) {
 680    case 0x100:
 681    case 0xf0:
 682       obj_class = NVF0_3D_CLASS;
 683       break;
 684    case 0xe0:
 685       obj_class = NVE4_3D_CLASS;
 686       break;
 687    case 0xd0:
 688       obj_class = NVC8_3D_CLASS;
 689       break;
 690    case 0xc0:
 691    default:
 692       switch (dev->chipset) {
 693       case 0xc8:
 694          obj_class = NVC8_3D_CLASS;
 695          break;
 696       case 0xc1:
 697          obj_class = NVC1_3D_CLASS;
 698          break;
 699       default:
 700          obj_class = NVC0_3D_CLASS;
 701          break;
 702       }
 703       break;
 704    }
 705    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 706                             &screen->eng3d);
 707    if (ret)
 708       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 709    screen->base.class_3d = obj_class;
 710
 711    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 712    PUSH_DATA (push, screen->eng3d->oclass);
 713
 714    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 715    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 716
 717    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 718       /* kill shaders after about 1 second (at 100 MHz) */
 719       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 720       PUSH_DATA (push, 0x17);
 721    }
 722
 723    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE), dev->drm_version >= 0x01000101);
 724    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 725    for (i = 0; i < 8; ++i)
 726            PUSH_DATA(push, dev->drm_version >= 0x01000101);
 727
 728    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 729    PUSH_DATA (push, 1);
 730
 731    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 732    PUSH_DATA (push, 0);
 733    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 734    PUSH_DATA (push, 0);
 735    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 736    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 737    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 738    PUSH_DATA (push, 0);
 739    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 740    PUSH_DATA (push, 1);
 741    BEGIN_NVC0(push, NVC0_3D(LINE_LAST_PIXEL), 1);
 742    PUSH_DATA (push, 0);
 743    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 744    PUSH_DATA (push, 1);
 745    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 746    PUSH_DATA (push, 0);
 747    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 748       BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
 749       PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 750    } else {
 751       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
 752       PUSH_DATA (push, 15);
 753    }
 754    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
 755    PUSH_DATA (push, 8); /* 128 */
 756    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
 757    PUSH_DATA (push, 1);
 758    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
 759       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
 760       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
 761    }
 762
 763    nvc0_magic_3d_init(push, screen->eng3d->oclass);
 764
 765    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
 766                         &screen->text);
 767    if (ret)
 768       goto fail;
 769
 770    /* XXX: getting a page fault at the end of the code buffer every few
 771     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 772     */
 773    nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
 774
 775    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
 776                         &screen->uniform_bo);
 777    if (ret)
 778       goto fail;
 779
 780    PUSH_REFN (push, screen->uniform_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 781
 782    for (i = 0; i < 5; ++i) {
 783       /* TIC and TSC entries for each unit (nve4+ only) */
 784       /* auxiliary constants (6 user clip planes, base instance id) */
 785       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 786       PUSH_DATA (push, 512);
 787       PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
 788       PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
 789       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
 790       PUSH_DATA (push, (15 << 4) | 1);
 791       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
 792          unsigned j;
 793          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
 794          PUSH_DATA (push, 0);
 795          for (j = 0; j < 8; ++j)
 796             PUSH_DATA(push, j);
 797       } else {
 798          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
 799          PUSH_DATA (push, 0x54);
 800       }
 801    }
 802    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
 803    PUSH_DATA (push, 0);
 804
 805    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
 806    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 807    PUSH_DATA (push, 256);
 808    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 809    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 810    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
 811    PUSH_DATA (push, 0);
 812    PUSH_DATAf(push, 0.0f);
 813    PUSH_DATAf(push, 0.0f);
 814    PUSH_DATAf(push, 0.0f);
 815    PUSH_DATAf(push, 0.0f);
 816    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 817    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 818    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 819
 820    if (dev->drm_version >= 0x01000101) {
 821       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 822       if (ret) {
 823          NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
 824          goto fail;
 825       }
 826    } else {
 827       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
 828          value = (8 << 8) | 4;
 829       else
 830          value = (16 << 8) | 4;
 831    }
 832    screen->mp_count = value >> 8;
 833    screen->mp_count_compute = screen->mp_count;
 834
 835    nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
 836
 837    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 838    PUSH_DATAh(push, screen->text->offset);
 839    PUSH_DATA (push, screen->text->offset);
 840    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
 841    PUSH_DATAh(push, screen->tls->offset);
 842    PUSH_DATA (push, screen->tls->offset);
 843    PUSH_DATA (push, screen->tls->size >> 32);
 844    PUSH_DATA (push, screen->tls->size);
 845    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
 846    PUSH_DATA (push, 0);
 847    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
 848    PUSH_DATA (push, 0);
 849
 850    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
 851                         &screen->poly_cache);
 852    if (ret)
 853       goto fail;
 854
 855    BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
 856    PUSH_DATAh(push, screen->poly_cache->offset);
 857    PUSH_DATA (push, screen->poly_cache->offset);
 858    PUSH_DATA (push, 3);
 859
 860    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL,
 861                         &screen->txc);
 862    if (ret)
 863       goto fail;
 864
 865    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
 866    PUSH_DATAh(push, screen->txc->offset);
 867    PUSH_DATA (push, screen->txc->offset);
 868    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
 869
 870    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
 871    PUSH_DATAh(push, screen->txc->offset + 65536);
 872    PUSH_DATA (push, screen->txc->offset + 65536);
 873    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
 874
 875    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
 876    PUSH_DATA (push, 0);
 877    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
 878    PUSH_DATA (push, 0);
 879    PUSH_DATA (push, 0);
 880    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
 881    PUSH_DATA (push, 0x3f);
 882
 883    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
 884    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 885    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 886    for (i = 0; i < 8 * 2; ++i)
 887       PUSH_DATA(push, 0);
 888    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
 889    PUSH_DATA (push, 0);
 890    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
 891    PUSH_DATA (push, 0);
 892
 893    /* neither scissors, viewport nor stencil mask should affect clears */
 894    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
 895    PUSH_DATA (push, 0);
 896
 897    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
 898    PUSH_DATA (push, 1);
 899    BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2);
 900    PUSH_DATAf(push, 0.0f);
 901    PUSH_DATAf(push, 1.0f);
 902    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 903    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
 904
 905    /* We use scissors instead of exact view volume clipping,
 906     * so they're always enabled.
 907     */
 908    BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(0)), 3);
 909    PUSH_DATA (push, 1);
 910    PUSH_DATA (push, 8192 << 16);
 911    PUSH_DATA (push, 8192 << 16);
 912
 913 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
 914
 915    i = 0;
 916    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, nvc0_9097_per_instance_bf);
 917    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, nvc0_9097_blend_enables);
 918    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select);
 919    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, nvc0_9097_tep_select);
 920    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, nvc0_9097_gp_select);
 921    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front);
 922    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back);
 923
 924    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
 925    PUSH_DATA (push, 1);
 926    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
 927    PUSH_DATA (push, 1);
 928    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
 929    PUSH_DATA (push, 0x40);
 930    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
 931    PUSH_DATA (push, 0);
 932    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
 933    PUSH_DATA (push, 0x30);
 934    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
 935    PUSH_DATA (push, 3);
 936    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
 937    PUSH_DATA (push, 0x20);
 938    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
 939    PUSH_DATA (push, 0x00);
 940
 941    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
 942    PUSH_DATA (push, 0);
 943    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
 944    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
 945
 946    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
 947
 948    if (nvc0_screen_init_compute(screen))
 949       goto fail;
 950
 951    PUSH_KICK (push);
 952
 953    screen->tic.entries = CALLOC(4096, sizeof(void *));
 954    screen->tsc.entries = screen->tic.entries + 2048;
 955
 956    mm_config.nvc0.tile_mode = 0;
 957    mm_config.nvc0.memtype = 0xfe0;
 958    screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config);
 959
 960    if (!nvc0_blitter_create(screen))
 961       goto fail;
 962
 963    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 964
 965    return pscreen;
 966
 967 fail:
 968    nvc0_screen_destroy(pscreen);
 969    return NULL;
 970 }
 971
 972 int
 973 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
 974 {
 975    int i = screen->tic.next;
 976
 977    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 978       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 979
 980    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 981
 982    if (screen->tic.entries[i])
 983       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 984
 985    screen->tic.entries[i] = entry;
 986    return i;
 987 }
 988
 989 int
 990 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
 991 {
 992    int i = screen->tsc.next;
 993
 994    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 995       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 996
 997    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 998
 999    if (screen->tsc.entries[i])
1000       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1001
1002    screen->tsc.entries[i] = entry;
1003    return i;
1004 }