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gallium: add PIPE_CAP_QUERY_BUFFER_OBJECT
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32
33 #include "nouveau_vp3_video.h"
34
35 #include "nvc0/nvc0_context.h"
36 #include "nvc0/nvc0_screen.h"
37
38 #include "nvc0/mme/com9097.mme.h"
39
40 static boolean
41 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
42 enum pipe_format format,
43 enum pipe_texture_target target,
44 unsigned sample_count,
45 unsigned bindings)
46 {
47 if (sample_count > 8)
48 return false;
49 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
50 return false;
51
52 if (!util_format_is_supported(format, bindings))
53 return false;
54
55 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
56 if (util_format_get_blocksizebits(format) == 3 * 32)
57 return false;
58
59 /* transfers & shared are always supported */
60 bindings &= ~(PIPE_BIND_TRANSFER_READ |
61 PIPE_BIND_TRANSFER_WRITE |
62 PIPE_BIND_SHARED);
63
64 return (nvc0_format_table[format].usage & bindings) == bindings;
65 }
66
67 static int
68 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
69 {
70 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
71 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
72
73 switch (param) {
74 /* non-boolean caps */
75 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
76 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
77 return 15;
78 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
79 return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
80 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
81 return 2048;
82 case PIPE_CAP_MIN_TEXEL_OFFSET:
83 return -8;
84 case PIPE_CAP_MAX_TEXEL_OFFSET:
85 return 7;
86 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
87 return -32;
88 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
89 return 31;
90 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
91 return 128 * 1024 * 1024;
92 case PIPE_CAP_GLSL_FEATURE_LEVEL:
93 return 410;
94 case PIPE_CAP_MAX_RENDER_TARGETS:
95 return 8;
96 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
97 return 1;
98 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
99 return 4;
100 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
101 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
102 return 128;
103 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
104 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
105 return 1024;
106 case PIPE_CAP_MAX_VERTEX_STREAMS:
107 return 4;
108 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
109 return 2048;
110 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
111 return 256;
112 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
113 return 1; /* 256 for binding as RT, but that's not possible in GL */
114 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
115 return 16;
116 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
117 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
118 case PIPE_CAP_MAX_VIEWPORTS:
119 return NVC0_MAX_VIEWPORTS;
120 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
121 return 4;
122 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
123 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
124 case PIPE_CAP_ENDIANNESS:
125 return PIPE_ENDIAN_LITTLE;
126 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
127 return 30;
128
129 /* supported caps */
130 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
131 case PIPE_CAP_TEXTURE_SWIZZLE:
132 case PIPE_CAP_TEXTURE_SHADOW_MAP:
133 case PIPE_CAP_NPOT_TEXTURES:
134 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
135 case PIPE_CAP_ANISOTROPIC_FILTER:
136 case PIPE_CAP_SEAMLESS_CUBE_MAP:
137 case PIPE_CAP_CUBE_MAP_ARRAY:
138 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
139 case PIPE_CAP_TEXTURE_MULTISAMPLE:
140 case PIPE_CAP_TWO_SIDED_STENCIL:
141 case PIPE_CAP_DEPTH_CLIP_DISABLE:
142 case PIPE_CAP_POINT_SPRITE:
143 case PIPE_CAP_TGSI_TEXCOORD:
144 case PIPE_CAP_SM3:
145 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
146 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
147 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
148 case PIPE_CAP_QUERY_TIMESTAMP:
149 case PIPE_CAP_QUERY_TIME_ELAPSED:
150 case PIPE_CAP_OCCLUSION_QUERY:
151 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
152 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
153 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
154 case PIPE_CAP_INDEP_BLEND_ENABLE:
155 case PIPE_CAP_INDEP_BLEND_FUNC:
156 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
157 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
158 case PIPE_CAP_PRIMITIVE_RESTART:
159 case PIPE_CAP_TGSI_INSTANCEID:
160 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
161 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
162 case PIPE_CAP_CONDITIONAL_RENDER:
163 case PIPE_CAP_TEXTURE_BARRIER:
164 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
165 case PIPE_CAP_START_INSTANCE:
166 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
167 case PIPE_CAP_DRAW_INDIRECT:
168 case PIPE_CAP_USER_CONSTANT_BUFFERS:
169 case PIPE_CAP_USER_INDEX_BUFFERS:
170 case PIPE_CAP_USER_VERTEX_BUFFERS:
171 case PIPE_CAP_TEXTURE_QUERY_LOD:
172 case PIPE_CAP_SAMPLE_SHADING:
173 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
174 case PIPE_CAP_TEXTURE_GATHER_SM5:
175 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
176 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
177 case PIPE_CAP_SAMPLER_VIEW_TARGET:
178 case PIPE_CAP_CLIP_HALFZ:
179 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
180 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
181 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
182 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
183 case PIPE_CAP_DEPTH_BOUNDS_TEST:
184 case PIPE_CAP_TGSI_TXQS:
185 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
186 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
187 case PIPE_CAP_SHAREABLE_SHADERS:
188 case PIPE_CAP_CLEAR_TEXTURE:
189 case PIPE_CAP_DRAW_PARAMETERS:
190 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
191 case PIPE_CAP_MULTI_DRAW_INDIRECT:
192 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
193 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
194 return 1;
195 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
196 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
197 case PIPE_CAP_COMPUTE:
198 return (class_3d <= NVE4_3D_CLASS) ? 1 : 0;
199 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
200 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
201
202 /* unsupported caps */
203 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
204 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
205 case PIPE_CAP_SHADER_STENCIL_EXPORT:
206 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
207 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
208 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
209 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
210 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
211 case PIPE_CAP_FAKE_SW_MSAA:
212 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
213 case PIPE_CAP_VERTEXID_NOBASE:
214 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
215 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
216 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
217 case PIPE_CAP_INVALIDATE_BUFFER:
218 case PIPE_CAP_GENERATE_MIPMAP:
219 case PIPE_CAP_STRING_MARKER:
220 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
221 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
222 case PIPE_CAP_QUERY_BUFFER_OBJECT:
223 return 0;
224
225 case PIPE_CAP_VENDOR_ID:
226 return 0x10de;
227 case PIPE_CAP_DEVICE_ID: {
228 uint64_t device_id;
229 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
230 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
231 return -1;
232 }
233 return device_id;
234 }
235 case PIPE_CAP_ACCELERATED:
236 return 1;
237 case PIPE_CAP_VIDEO_MEMORY:
238 return dev->vram_size >> 20;
239 case PIPE_CAP_UMA:
240 return 0;
241 }
242
243 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
244 return 0;
245 }
246
247 static int
248 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
249 enum pipe_shader_cap param)
250 {
251 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
252
253 switch (shader) {
254 case PIPE_SHADER_VERTEX:
255 case PIPE_SHADER_GEOMETRY:
256 case PIPE_SHADER_FRAGMENT:
257 break;
258 case PIPE_SHADER_TESS_CTRL:
259 case PIPE_SHADER_TESS_EVAL:
260 if (class_3d >= GM107_3D_CLASS)
261 return 0;
262 break;
263 case PIPE_SHADER_COMPUTE:
264 if (class_3d > NVE4_3D_CLASS)
265 return 0;
266 break;
267 default:
268 return 0;
269 }
270
271 switch (param) {
272 case PIPE_SHADER_CAP_PREFERRED_IR:
273 return PIPE_SHADER_IR_TGSI;
274 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
275 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
276 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
277 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
278 return 16384;
279 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
280 return 16;
281 case PIPE_SHADER_CAP_MAX_INPUTS:
282 if (shader == PIPE_SHADER_VERTEX)
283 return 32;
284 /* NOTE: These only count our slots for GENERIC varyings.
285 * The address space may be larger, but the actual hard limit seems to be
286 * less than what the address space layout permits, so don't add TEXCOORD,
287 * COLOR, etc. here.
288 */
289 if (shader == PIPE_SHADER_FRAGMENT)
290 return 0x1f0 / 16;
291 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
292 * and excludes 0x60 per-patch inputs.
293 */
294 return 0x200 / 16;
295 case PIPE_SHADER_CAP_MAX_OUTPUTS:
296 return 32;
297 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
298 return 65536;
299 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
300 if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
301 return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
302 return NVC0_MAX_PIPE_CONSTBUFS;
303 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
304 return shader != PIPE_SHADER_FRAGMENT;
305 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
306 return shader != PIPE_SHADER_FRAGMENT || class_3d < GM107_3D_CLASS;
307 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
308 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
309 return 1;
310 case PIPE_SHADER_CAP_MAX_PREDS:
311 return 0;
312 case PIPE_SHADER_CAP_MAX_TEMPS:
313 return NVC0_CAP_MAX_PROGRAM_TEMPS;
314 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
315 return 1;
316 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
317 return 0;
318 case PIPE_SHADER_CAP_SUBROUTINES:
319 return 1;
320 case PIPE_SHADER_CAP_INTEGERS:
321 return 1;
322 case PIPE_SHADER_CAP_DOUBLES:
323 return 1;
324 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
325 return 1;
326 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
327 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
328 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
329 return 0;
330 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
331 return NVC0_MAX_BUFFERS;
332 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
333 return 16; /* would be 32 in linked (OpenGL-style) mode */
334 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
335 return 16; /* XXX not sure if more are really safe */
336 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
337 return 32;
338 default:
339 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
340 return 0;
341 }
342 }
343
344 static float
345 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
346 {
347 switch (param) {
348 case PIPE_CAPF_MAX_LINE_WIDTH:
349 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
350 return 10.0f;
351 case PIPE_CAPF_MAX_POINT_WIDTH:
352 return 63.0f;
353 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
354 return 63.375f;
355 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
356 return 16.0f;
357 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
358 return 15.0f;
359 case PIPE_CAPF_GUARD_BAND_LEFT:
360 case PIPE_CAPF_GUARD_BAND_TOP:
361 return 0.0f;
362 case PIPE_CAPF_GUARD_BAND_RIGHT:
363 case PIPE_CAPF_GUARD_BAND_BOTTOM:
364 return 0.0f; /* that or infinity */
365 }
366
367 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
368 return 0.0f;
369 }
370
371 static int
372 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
373 enum pipe_compute_cap param, void *data)
374 {
375 struct nvc0_screen *screen = nvc0_screen(pscreen);
376 const uint16_t obj_class = screen->compute->oclass;
377
378 #define RET(x) do { \
379 if (data) \
380 memcpy(data, x, sizeof(x)); \
381 return sizeof(x); \
382 } while (0)
383
384 switch (param) {
385 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
386 RET((uint64_t []) { 3 });
387 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
388 if (obj_class >= NVE4_COMPUTE_CLASS) {
389 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
390 } else {
391 RET(((uint64_t []) { 65535, 65535, 65535 }));
392 }
393 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
394 RET(((uint64_t []) { 1024, 1024, 64 }));
395 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
396 RET((uint64_t []) { 1024 });
397 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
398 RET((uint64_t []) { 1ULL << 40 });
399 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
400 RET((uint64_t []) { 48 << 10 });
401 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
402 RET((uint64_t []) { 512 << 10 });
403 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
404 RET((uint64_t []) { 4096 });
405 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
406 RET((uint32_t []) { 32 });
407 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
408 RET((uint64_t []) { 1ULL << 40 });
409 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
410 RET((uint32_t []) { 0 });
411 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
412 RET((uint32_t []) { screen->mp_count_compute });
413 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
414 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
415 default:
416 return 0;
417 }
418
419 #undef RET
420 }
421
422 static void
423 nvc0_screen_destroy(struct pipe_screen *pscreen)
424 {
425 struct nvc0_screen *screen = nvc0_screen(pscreen);
426
427 if (!nouveau_drm_screen_unref(&screen->base))
428 return;
429
430 if (screen->base.fence.current) {
431 struct nouveau_fence *current = NULL;
432
433 /* nouveau_fence_wait will create a new current fence, so wait on the
434 * _current_ one, and remove both.
435 */
436 nouveau_fence_ref(screen->base.fence.current, &current);
437 nouveau_fence_wait(current, NULL);
438 nouveau_fence_ref(NULL, &current);
439 nouveau_fence_ref(NULL, &screen->base.fence.current);
440 }
441 if (screen->base.pushbuf)
442 screen->base.pushbuf->user_priv = NULL;
443
444 if (screen->blitter)
445 nvc0_blitter_destroy(screen);
446 if (screen->pm.prog) {
447 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
448 nvc0_program_destroy(NULL, screen->pm.prog);
449 FREE(screen->pm.prog);
450 }
451
452 nouveau_bo_ref(NULL, &screen->text);
453 nouveau_bo_ref(NULL, &screen->uniform_bo);
454 nouveau_bo_ref(NULL, &screen->tls);
455 nouveau_bo_ref(NULL, &screen->txc);
456 nouveau_bo_ref(NULL, &screen->fence.bo);
457 nouveau_bo_ref(NULL, &screen->poly_cache);
458 nouveau_bo_ref(NULL, &screen->parm);
459
460 nouveau_heap_destroy(&screen->lib_code);
461 nouveau_heap_destroy(&screen->text_heap);
462
463 FREE(screen->tic.entries);
464
465 nouveau_object_del(&screen->eng3d);
466 nouveau_object_del(&screen->eng2d);
467 nouveau_object_del(&screen->m2mf);
468 nouveau_object_del(&screen->compute);
469 nouveau_object_del(&screen->nvsw);
470
471 nouveau_screen_fini(&screen->base);
472
473 FREE(screen);
474 }
475
476 static int
477 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
478 unsigned size, const uint32_t *data)
479 {
480 struct nouveau_pushbuf *push = screen->base.pushbuf;
481
482 size /= 4;
483
484 assert((pos + size) <= 0x800);
485
486 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
487 PUSH_DATA (push, (m - 0x3800) / 8);
488 PUSH_DATA (push, pos);
489 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
490 PUSH_DATA (push, pos);
491 PUSH_DATAp(push, data, size);
492
493 return pos + size;
494 }
495
496 static void
497 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
498 {
499 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
500 PUSH_DATA (push, 0xff);
501 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
502 PUSH_DATA (push, 0xff);
503 PUSH_DATA (push, 0xff);
504 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
505 PUSH_DATA (push, 0xff);
506 PUSH_DATA (push, 0xff);
507 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
508 PUSH_DATA (push, 0x3f);
509
510 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
511 PUSH_DATA (push, (3 << 16) | 3);
512 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
513 PUSH_DATA (push, (2 << 16) | 2);
514
515 if (obj_class < GM107_3D_CLASS) {
516 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
517 PUSH_DATA (push, 0);
518 }
519 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
520 PUSH_DATA (push, 0x10);
521 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
522 PUSH_DATA (push, 0x10);
523 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
524 PUSH_DATA (push, 0x10);
525 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
526 PUSH_DATA (push, 0x10);
527 PUSH_DATA (push, 0x10);
528 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
529 PUSH_DATA (push, 0x10);
530 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
531 PUSH_DATA (push, 0xe);
532
533 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
534 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
535 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
536 PUSH_DATA (push, 0);
537 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
538 PUSH_DATA (push, 3);
539
540 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
541 PUSH_DATA (push, 0x3fffff);
542 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
543 PUSH_DATA (push, 1);
544 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
545 PUSH_DATA (push, 1);
546
547 if (obj_class < GM107_3D_CLASS) {
548 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
549 PUSH_DATA (push, 3);
550
551 if (obj_class >= NVE4_3D_CLASS) {
552 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
553 PUSH_DATA (push, 1);
554 }
555 }
556
557 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
558 * are supposed to do */
559 }
560
561 static void
562 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
563 {
564 struct nvc0_screen *screen = nvc0_screen(pscreen);
565 struct nouveau_pushbuf *push = screen->base.pushbuf;
566
567 /* we need to do it after possible flush in MARK_RING */
568 *sequence = ++screen->base.fence.sequence;
569
570 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
571 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
572 PUSH_DATAh(push, screen->fence.bo->offset);
573 PUSH_DATA (push, screen->fence.bo->offset);
574 PUSH_DATA (push, *sequence);
575 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
576 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
577 }
578
579 static u32
580 nvc0_screen_fence_update(struct pipe_screen *pscreen)
581 {
582 struct nvc0_screen *screen = nvc0_screen(pscreen);
583 return screen->fence.map[0];
584 }
585
586 static int
587 nvc0_screen_init_compute(struct nvc0_screen *screen)
588 {
589 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
590
591 switch (screen->base.device->chipset & ~0xf) {
592 case 0xc0:
593 case 0xd0:
594 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
595 case 0xe0:
596 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
597 case 0xf0:
598 case 0x100:
599 case 0x110:
600 return 0;
601 default:
602 return -1;
603 }
604 }
605
606 bool
607 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
608 uint32_t lpos, uint32_t lneg, uint32_t cstack)
609 {
610 struct nouveau_bo *bo = NULL;
611 int ret;
612 uint64_t size = (lpos + lneg) * 32 + cstack;
613
614 if (size >= (1 << 20)) {
615 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
616 return false;
617 }
618
619 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
620 size = align(size, 0x8000);
621 size *= screen->mp_count;
622
623 size = align(size, 1 << 17);
624
625 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
626 NULL, &bo);
627 if (ret) {
628 NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
629 return false;
630 }
631 nouveau_bo_ref(NULL, &screen->tls);
632 screen->tls = bo;
633 return true;
634 }
635
636 #define FAIL_SCREEN_INIT(str, err) \
637 do { \
638 NOUVEAU_ERR(str, err); \
639 goto fail; \
640 } while(0)
641
642 struct nouveau_screen *
643 nvc0_screen_create(struct nouveau_device *dev)
644 {
645 struct nvc0_screen *screen;
646 struct pipe_screen *pscreen;
647 struct nouveau_object *chan;
648 struct nouveau_pushbuf *push;
649 uint64_t value;
650 uint32_t obj_class;
651 uint32_t flags;
652 int ret;
653 unsigned i;
654
655 switch (dev->chipset & ~0xf) {
656 case 0xc0:
657 case 0xd0:
658 case 0xe0:
659 case 0xf0:
660 case 0x100:
661 case 0x110:
662 break;
663 default:
664 return NULL;
665 }
666
667 screen = CALLOC_STRUCT(nvc0_screen);
668 if (!screen)
669 return NULL;
670 pscreen = &screen->base.base;
671 pscreen->destroy = nvc0_screen_destroy;
672
673 ret = nouveau_screen_init(&screen->base, dev);
674 if (ret) {
675 nvc0_screen_destroy(pscreen);
676 return NULL;
677 }
678 chan = screen->base.channel;
679 push = screen->base.pushbuf;
680 push->user_priv = screen;
681 push->rsvd_kick = 5;
682
683 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
684 PIPE_BIND_SHADER_BUFFER |
685 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
686 PIPE_BIND_COMMAND_ARGS_BUFFER;
687 screen->base.sysmem_bindings |=
688 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
689
690 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
691 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
692 screen->base.vidmem_bindings = 0;
693 }
694
695 pscreen->context_create = nvc0_create;
696 pscreen->is_format_supported = nvc0_screen_is_format_supported;
697 pscreen->get_param = nvc0_screen_get_param;
698 pscreen->get_shader_param = nvc0_screen_get_shader_param;
699 pscreen->get_paramf = nvc0_screen_get_paramf;
700 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
701 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
702
703 nvc0_screen_init_resource_functions(pscreen);
704
705 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
706 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
707
708 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
709 if (screen->base.drm->version >= 0x01000202)
710 flags |= NOUVEAU_BO_COHERENT;
711
712 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
713 if (ret)
714 goto fail;
715 nouveau_bo_map(screen->fence.bo, 0, NULL);
716 screen->fence.map = screen->fence.bo->map;
717 screen->base.fence.emit = nvc0_screen_fence_emit;
718 screen->base.fence.update = nvc0_screen_fence_update;
719
720
721 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
722 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
723 if (ret)
724 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
725
726 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
727 PUSH_DATA (push, screen->nvsw->handle);
728
729 switch (dev->chipset & ~0xf) {
730 case 0x110:
731 case 0x100:
732 case 0xf0:
733 obj_class = NVF0_P2MF_CLASS;
734 break;
735 case 0xe0:
736 obj_class = NVE4_P2MF_CLASS;
737 break;
738 default:
739 obj_class = NVC0_M2MF_CLASS;
740 break;
741 }
742 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
743 &screen->m2mf);
744 if (ret)
745 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
746
747 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
748 PUSH_DATA (push, screen->m2mf->oclass);
749 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
750 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
751 PUSH_DATA (push, 0xa0b5);
752 }
753
754 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
755 &screen->eng2d);
756 if (ret)
757 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
758
759 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
760 PUSH_DATA (push, screen->eng2d->oclass);
761 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
762 PUSH_DATA (push, 0);
763 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
764 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
765 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
766 PUSH_DATA (push, 0);
767 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
768 PUSH_DATA (push, 0);
769 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
770 PUSH_DATA (push, 0x3f);
771 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
772 PUSH_DATA (push, 1);
773 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
774 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
775
776 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
777 PUSH_DATAh(push, screen->fence.bo->offset + 16);
778 PUSH_DATA (push, screen->fence.bo->offset + 16);
779
780 switch (dev->chipset & ~0xf) {
781 case 0x110:
782 obj_class = GM107_3D_CLASS;
783 break;
784 case 0x100:
785 case 0xf0:
786 obj_class = NVF0_3D_CLASS;
787 break;
788 case 0xe0:
789 switch (dev->chipset) {
790 case 0xea:
791 obj_class = NVEA_3D_CLASS;
792 break;
793 default:
794 obj_class = NVE4_3D_CLASS;
795 break;
796 }
797 break;
798 case 0xd0:
799 obj_class = NVC8_3D_CLASS;
800 break;
801 case 0xc0:
802 default:
803 switch (dev->chipset) {
804 case 0xc8:
805 obj_class = NVC8_3D_CLASS;
806 break;
807 case 0xc1:
808 obj_class = NVC1_3D_CLASS;
809 break;
810 default:
811 obj_class = NVC0_3D_CLASS;
812 break;
813 }
814 break;
815 }
816 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
817 &screen->eng3d);
818 if (ret)
819 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
820 screen->base.class_3d = obj_class;
821
822 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
823 PUSH_DATA (push, screen->eng3d->oclass);
824
825 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
826 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
827
828 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
829 /* kill shaders after about 1 second (at 100 MHz) */
830 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
831 PUSH_DATA (push, 0x17);
832 }
833
834 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
835 screen->base.drm->version >= 0x01000101);
836 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
837 for (i = 0; i < 8; ++i)
838 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
839
840 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
841 PUSH_DATA (push, 1);
842
843 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
844 PUSH_DATA (push, 0);
845 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
846 PUSH_DATA (push, 0);
847 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
848 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
849 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
850 PUSH_DATA (push, 0);
851 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
852 PUSH_DATA (push, 1);
853 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
854 PUSH_DATA (push, 1);
855 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
856 PUSH_DATA (push, 1);
857 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
858 PUSH_DATA (push, 0);
859 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
860 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
861 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
862 BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
863 PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
864 } else {
865 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
866 PUSH_DATA (push, 15);
867 }
868 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
869 PUSH_DATA (push, 8); /* 128 */
870 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
871 PUSH_DATA (push, 1);
872 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
873 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
874 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
875 }
876
877 nvc0_magic_3d_init(push, screen->eng3d->oclass);
878
879 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
880 &screen->text);
881 if (ret)
882 goto fail;
883
884 /* XXX: getting a page fault at the end of the code buffer every few
885 * launches, don't use the last 256 bytes to work around them - prefetch ?
886 */
887 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
888
889 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 6 << 16, NULL,
890 &screen->uniform_bo);
891 if (ret)
892 goto fail;
893
894 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
895
896 for (i = 0; i < 5; ++i) {
897 /* TIC and TSC entries for each unit (nve4+ only) */
898 /* auxiliary constants (6 user clip planes, base instance id) */
899 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
900 PUSH_DATA (push, 1024);
901 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 10));
902 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 10));
903 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
904 PUSH_DATA (push, (15 << 4) | 1);
905 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
906 unsigned j;
907 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
908 PUSH_DATA (push, 0);
909 for (j = 0; j < 8; ++j)
910 PUSH_DATA(push, j);
911 } else {
912 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
913 PUSH_DATA (push, 0x54);
914 }
915 }
916 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
917 PUSH_DATA (push, 0);
918
919 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
920 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
921 PUSH_DATA (push, 256);
922 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 10));
923 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 10));
924 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
925 PUSH_DATA (push, 0);
926 PUSH_DATAf(push, 0.0f);
927 PUSH_DATAf(push, 0.0f);
928 PUSH_DATAf(push, 0.0f);
929 PUSH_DATAf(push, 0.0f);
930 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
931 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 10));
932 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 10));
933
934 if (screen->base.drm->version >= 0x01000101) {
935 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
936 if (ret) {
937 NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
938 goto fail;
939 }
940 } else {
941 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
942 value = (8 << 8) | 4;
943 else
944 value = (16 << 8) | 4;
945 }
946 screen->gpc_count = value & 0x000000ff;
947 screen->mp_count = value >> 8;
948 screen->mp_count_compute = screen->mp_count;
949
950 nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
951
952 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
953 PUSH_DATAh(push, screen->text->offset);
954 PUSH_DATA (push, screen->text->offset);
955 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
956 PUSH_DATAh(push, screen->tls->offset);
957 PUSH_DATA (push, screen->tls->offset);
958 PUSH_DATA (push, screen->tls->size >> 32);
959 PUSH_DATA (push, screen->tls->size);
960 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
961 PUSH_DATA (push, 0);
962 /* Reduce likelihood of collision with real buffers by placing the hole at
963 * the top of the 4G area. This will have to be dealt with for real
964 * eventually by blocking off that area from the VM.
965 */
966 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
967 PUSH_DATA (push, 0xff << 24);
968
969 if (screen->eng3d->oclass < GM107_3D_CLASS) {
970 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
971 &screen->poly_cache);
972 if (ret)
973 goto fail;
974
975 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
976 PUSH_DATAh(push, screen->poly_cache->offset);
977 PUSH_DATA (push, screen->poly_cache->offset);
978 PUSH_DATA (push, 3);
979 }
980
981 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
982 &screen->txc);
983 if (ret)
984 goto fail;
985
986 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
987 PUSH_DATAh(push, screen->txc->offset);
988 PUSH_DATA (push, screen->txc->offset);
989 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
990
991 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
992 PUSH_DATAh(push, screen->txc->offset + 65536);
993 PUSH_DATA (push, screen->txc->offset + 65536);
994 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
995
996 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
997 PUSH_DATA (push, 0);
998 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
999 PUSH_DATA (push, 0);
1000 PUSH_DATA (push, 0);
1001 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1002 PUSH_DATA (push, 0x3f);
1003
1004 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1005 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1006 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1007 for (i = 0; i < 8 * 2; ++i)
1008 PUSH_DATA(push, 0);
1009 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1010 PUSH_DATA (push, 0);
1011 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1012 PUSH_DATA (push, 0);
1013
1014 /* neither scissors, viewport nor stencil mask should affect clears */
1015 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1016 PUSH_DATA (push, 0);
1017
1018 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1019 PUSH_DATA (push, 1);
1020 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1021 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1022 PUSH_DATAf(push, 0.0f);
1023 PUSH_DATAf(push, 1.0f);
1024 }
1025 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1026 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1027
1028 /* We use scissors instead of exact view volume clipping,
1029 * so they're always enabled.
1030 */
1031 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1032 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1033 PUSH_DATA (push, 1);
1034 PUSH_DATA (push, 8192 << 16);
1035 PUSH_DATA (push, 8192 << 16);
1036 }
1037
1038 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1039
1040 i = 0;
1041 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1042 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1043 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1044 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1045 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1046 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1047 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1048 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1049 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1050 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1051 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1052
1053 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1054 PUSH_DATA (push, 1);
1055 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1056 PUSH_DATA (push, 1);
1057 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1058 PUSH_DATA (push, 0x40);
1059 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1060 PUSH_DATA (push, 0);
1061 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1062 PUSH_DATA (push, 0x30);
1063 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1064 PUSH_DATA (push, 3);
1065 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1066 PUSH_DATA (push, 0x20);
1067 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1068 PUSH_DATA (push, 0x00);
1069 screen->save_state.patch_vertices = 3;
1070
1071 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1072 PUSH_DATA (push, 0);
1073 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1074 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1075
1076 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1077
1078 if (nvc0_screen_init_compute(screen))
1079 goto fail;
1080
1081 PUSH_KICK (push);
1082
1083 screen->tic.entries = CALLOC(4096, sizeof(void *));
1084 screen->tsc.entries = screen->tic.entries + 2048;
1085
1086 if (!nvc0_blitter_create(screen))
1087 goto fail;
1088
1089 nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1090
1091 return &screen->base;
1092
1093 fail:
1094 screen->base.base.context_create = NULL;
1095 return &screen->base;
1096 }
1097
1098 int
1099 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1100 {
1101 int i = screen->tic.next;
1102
1103 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1104 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1105
1106 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1107
1108 if (screen->tic.entries[i])
1109 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1110
1111 screen->tic.entries[i] = entry;
1112 return i;
1113 }
1114
1115 int
1116 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1117 {
1118 int i = screen->tsc.next;
1119
1120 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1121 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1122
1123 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1124
1125 if (screen->tsc.entries[i])
1126 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1127
1128 screen->tsc.entries[i] = entry;
1129 return i;
1130 }