src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nvc0/nvc0_context.h"
  36 #include "nvc0/nvc0_screen.h"
  37
  38 #include "nvc0/mme/com9097.mme.h"
  39 #include "nvc0/mme/com90c0.mme.h"
  40
  41 static boolean
  42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  43                                 enum pipe_format format,
  44                                 enum pipe_texture_target target,
  45                                 unsigned sample_count,
  46                                 unsigned bindings)
  47 {
  48    const struct util_format_description *desc = util_format_description(format);
  49
  50    if (sample_count > 8)
  51       return false;
  52    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  53       return false;
  54
  55    /* Short-circuit the rest of the logic -- this is used by the state tracker
  56     * to determine valid MS levels in a no-attachments scenario.
  57     */
  58    if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
  59       return true;
  60
  61    if (!util_format_is_supported(format, bindings))
  62       return false;
  63
  64    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  65       if (util_format_get_blocksizebits(format) == 3 * 32)
  66          return false;
  67
  68    if (bindings & PIPE_BIND_LINEAR)
  69       if (util_format_is_depth_or_stencil(format) ||
  70           (target != PIPE_TEXTURE_1D &&
  71            target != PIPE_TEXTURE_2D &&
  72            target != PIPE_TEXTURE_RECT) ||
  73           sample_count > 1)
  74          return false;
  75
  76    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
  77     */
  78    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
  79         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
  80        /* The claim is that this should work on GM107 but it doesn't. Need to
  81         * test further and figure out if it's a nouveau issue or a HW one.
  82        nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
  83         */
  84        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
  85       return false;
  86
  87    /* transfers & shared are always supported */
  88    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  89                  PIPE_BIND_TRANSFER_WRITE |
  90                  PIPE_BIND_LINEAR |
  91                  PIPE_BIND_SHARED);
  92
  93    return (( nvc0_format_table[format].usage |
  94             nvc0_vertex_format[format].usage) & bindings) == bindings;
  95 }
  96
  97 static int
  98 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  99 {
 100    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 101    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
 102
 103    switch (param) {
 104    /* non-boolean caps */
 105    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 106    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 107       return 15;
 108    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 109       return 12;
 110    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 111       return 2048;
 112    case PIPE_CAP_MIN_TEXEL_OFFSET:
 113       return -8;
 114    case PIPE_CAP_MAX_TEXEL_OFFSET:
 115       return 7;
 116    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 117       return -32;
 118    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 119       return 31;
 120    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 121       return 128 * 1024 * 1024;
 122    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 123       return 410;
 124    case PIPE_CAP_MAX_RENDER_TARGETS:
 125       return 8;
 126    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 127       return 1;
 128    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 129       return 4;
 130    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 131    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 132       return 128;
 133    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 134    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 135       return 1024;
 136    case PIPE_CAP_MAX_VERTEX_STREAMS:
 137       return 4;
 138    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 139       return 2048;
 140    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 141       return 256;
 142    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 143       return 16; /* 256 for binding as RT, but that's not possible in GL */
 144    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 145       return 16;
 146    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 147       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 148    case PIPE_CAP_MAX_VIEWPORTS:
 149       return NVC0_MAX_VIEWPORTS;
 150    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 151       return 4;
 152    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 153       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 154    case PIPE_CAP_ENDIANNESS:
 155       return PIPE_ENDIAN_LITTLE;
 156    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 157       return 30;
 158
 159    /* supported caps */
 160    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 161    case PIPE_CAP_TEXTURE_SWIZZLE:
 162    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 163    case PIPE_CAP_NPOT_TEXTURES:
 164    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 165    case PIPE_CAP_ANISOTROPIC_FILTER:
 166    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 167    case PIPE_CAP_CUBE_MAP_ARRAY:
 168    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 169    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 170    case PIPE_CAP_TWO_SIDED_STENCIL:
 171    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 172    case PIPE_CAP_POINT_SPRITE:
 173    case PIPE_CAP_TGSI_TEXCOORD:
 174    case PIPE_CAP_SM3:
 175    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 176    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 177    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 178    case PIPE_CAP_QUERY_TIMESTAMP:
 179    case PIPE_CAP_QUERY_TIME_ELAPSED:
 180    case PIPE_CAP_OCCLUSION_QUERY:
 181    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 182    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 183    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 184    case PIPE_CAP_INDEP_BLEND_ENABLE:
 185    case PIPE_CAP_INDEP_BLEND_FUNC:
 186    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 187    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 188    case PIPE_CAP_PRIMITIVE_RESTART:
 189    case PIPE_CAP_TGSI_INSTANCEID:
 190    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 191    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 192    case PIPE_CAP_CONDITIONAL_RENDER:
 193    case PIPE_CAP_TEXTURE_BARRIER:
 194    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 195    case PIPE_CAP_START_INSTANCE:
 196    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 197    case PIPE_CAP_DRAW_INDIRECT:
 198    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 199    case PIPE_CAP_USER_INDEX_BUFFERS:
 200    case PIPE_CAP_USER_VERTEX_BUFFERS:
 201    case PIPE_CAP_TEXTURE_QUERY_LOD:
 202    case PIPE_CAP_SAMPLE_SHADING:
 203    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 204    case PIPE_CAP_TEXTURE_GATHER_SM5:
 205    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 206    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 207    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 208    case PIPE_CAP_CLIP_HALFZ:
 209    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 210    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 211    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 212    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 213    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 214    case PIPE_CAP_TGSI_TXQS:
 215    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 216    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 217    case PIPE_CAP_SHAREABLE_SHADERS:
 218    case PIPE_CAP_CLEAR_TEXTURE:
 219    case PIPE_CAP_DRAW_PARAMETERS:
 220    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 221    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 222    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 223    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 224    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 225    case PIPE_CAP_INVALIDATE_BUFFER:
 226    case PIPE_CAP_STRING_MARKER:
 227    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 228       return 1;
 229    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 230       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 231    case PIPE_CAP_COMPUTE:
 232       if (debug_get_bool_option("NVF0_COMPUTE", false))
 233          return 1;
 234       return (class_3d <= NVE4_3D_CLASS) ? 1 : 0;
 235    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 236       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 237
 238    /* unsupported caps */
 239    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 240    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 241    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 242    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 243    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 244    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 245    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 246    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 247    case PIPE_CAP_FAKE_SW_MSAA:
 248    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 249    case PIPE_CAP_VERTEXID_NOBASE:
 250    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 251    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 252    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 253    case PIPE_CAP_GENERATE_MIPMAP:
 254    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 255    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 256    case PIPE_CAP_QUERY_MEMORY_INFO:
 257    case PIPE_CAP_PCI_GROUP:
 258    case PIPE_CAP_PCI_BUS:
 259    case PIPE_CAP_PCI_DEVICE:
 260    case PIPE_CAP_PCI_FUNCTION:
 261    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 262       return 0;
 263
 264    case PIPE_CAP_VENDOR_ID:
 265       return 0x10de;
 266    case PIPE_CAP_DEVICE_ID: {
 267       uint64_t device_id;
 268       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 269          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 270          return -1;
 271       }
 272       return device_id;
 273    }
 274    case PIPE_CAP_ACCELERATED:
 275       return 1;
 276    case PIPE_CAP_VIDEO_MEMORY:
 277       return dev->vram_size >> 20;
 278    case PIPE_CAP_UMA:
 279       return 0;
 280    }
 281
 282    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 283    return 0;
 284 }
 285
 286 static int
 287 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 288                              enum pipe_shader_cap param)
 289 {
 290    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 291
 292    switch (shader) {
 293    case PIPE_SHADER_VERTEX:
 294    case PIPE_SHADER_GEOMETRY:
 295    case PIPE_SHADER_FRAGMENT:
 296       break;
 297    case PIPE_SHADER_TESS_CTRL:
 298    case PIPE_SHADER_TESS_EVAL:
 299       if (class_3d >= GM107_3D_CLASS)
 300          return 0;
 301       break;
 302    case PIPE_SHADER_COMPUTE:
 303       if (!debug_get_bool_option("NVF0_COMPUTE", false))
 304          if (class_3d > NVE4_3D_CLASS)
 305             return 0;
 306       break;
 307    default:
 308       return 0;
 309    }
 310
 311    switch (param) {
 312    case PIPE_SHADER_CAP_PREFERRED_IR:
 313       return PIPE_SHADER_IR_TGSI;
 314    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 315       if (class_3d == NVF0_3D_CLASS &&
 316           !debug_get_bool_option("NVF0_COMPUTE", false))
 317          return 0;
 318       return 1 << PIPE_SHADER_IR_TGSI;
 319    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 320    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 321    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 322    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 323       return 16384;
 324    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 325       return 16;
 326    case PIPE_SHADER_CAP_MAX_INPUTS:
 327       if (shader == PIPE_SHADER_VERTEX)
 328          return 32;
 329       /* NOTE: These only count our slots for GENERIC varyings.
 330        * The address space may be larger, but the actual hard limit seems to be
 331        * less than what the address space layout permits, so don't add TEXCOORD,
 332        * COLOR, etc. here.
 333        */
 334       if (shader == PIPE_SHADER_FRAGMENT)
 335          return 0x1f0 / 16;
 336       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 337        * and excludes 0x60 per-patch inputs.
 338        */
 339       return 0x200 / 16;
 340    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 341       return 32;
 342    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 343       return 65536;
 344    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 345       return NVC0_MAX_PIPE_CONSTBUFS;
 346    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 347       return shader != PIPE_SHADER_FRAGMENT;
 348    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 349       return shader != PIPE_SHADER_FRAGMENT || class_3d < GM107_3D_CLASS;
 350    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 351    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 352       return 1;
 353    case PIPE_SHADER_CAP_MAX_PREDS:
 354       return 0;
 355    case PIPE_SHADER_CAP_MAX_TEMPS:
 356       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 357    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 358       return 1;
 359    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 360       return 1;
 361    case PIPE_SHADER_CAP_SUBROUTINES:
 362       return 1;
 363    case PIPE_SHADER_CAP_INTEGERS:
 364       return 1;
 365    case PIPE_SHADER_CAP_DOUBLES:
 366       return 1;
 367    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 368       return 1;
 369    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 370       return 1;
 371    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 372    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 373       return 0;
 374    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 375       return NVC0_MAX_BUFFERS;
 376    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 377       return 16; /* would be 32 in linked (OpenGL-style) mode */
 378    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 379       return 16; /* XXX not sure if more are really safe */
 380    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 381       return 32;
 382    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 383       return 0;
 384    default:
 385       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 386       return 0;
 387    }
 388 }
 389
 390 static float
 391 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 392 {
 393    switch (param) {
 394    case PIPE_CAPF_MAX_LINE_WIDTH:
 395    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 396       return 10.0f;
 397    case PIPE_CAPF_MAX_POINT_WIDTH:
 398       return 63.0f;
 399    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 400       return 63.375f;
 401    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 402       return 16.0f;
 403    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 404       return 15.0f;
 405    case PIPE_CAPF_GUARD_BAND_LEFT:
 406    case PIPE_CAPF_GUARD_BAND_TOP:
 407       return 0.0f;
 408    case PIPE_CAPF_GUARD_BAND_RIGHT:
 409    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 410       return 0.0f; /* that or infinity */
 411    }
 412
 413    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 414    return 0.0f;
 415 }
 416
 417 static int
 418 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 419                               enum pipe_shader_ir ir_type,
 420                               enum pipe_compute_cap param, void *data)
 421 {
 422    struct nvc0_screen *screen = nvc0_screen(pscreen);
 423    const uint16_t obj_class = screen->compute->oclass;
 424
 425 #define RET(x) do {                  \
 426    if (data)                         \
 427       memcpy(data, x, sizeof(x));    \
 428    return sizeof(x);                 \
 429 } while (0)
 430
 431    switch (param) {
 432    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 433       RET((uint64_t []) { 3 });
 434    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 435       if (obj_class >= NVE4_COMPUTE_CLASS) {
 436          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 437       } else {
 438          RET(((uint64_t []) { 65535, 65535, 65535 }));
 439       }
 440    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 441       RET(((uint64_t []) { 1024, 1024, 64 }));
 442    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 443       RET((uint64_t []) { 1024 });
 444    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 445       RET((uint64_t []) { 1ULL << 40 });
 446    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 447       switch (obj_class) {
 448       case GM200_COMPUTE_CLASS:
 449          RET((uint64_t []) { 96 << 10 });
 450          break;
 451       case GM107_COMPUTE_CLASS:
 452          RET((uint64_t []) { 64 << 10 });
 453          break;
 454       default:
 455          RET((uint64_t []) { 48 << 10 });
 456          break;
 457       }
 458    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 459       RET((uint64_t []) { 512 << 10 });
 460    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 461       RET((uint64_t []) { 4096 });
 462    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 463       RET((uint32_t []) { 32 });
 464    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 465       RET((uint64_t []) { 1ULL << 40 });
 466    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 467       RET((uint32_t []) { 0 });
 468    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 469       RET((uint32_t []) { screen->mp_count_compute });
 470    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 471       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 472    default:
 473       return 0;
 474    }
 475
 476 #undef RET
 477 }
 478
 479 static void
 480 nvc0_screen_destroy(struct pipe_screen *pscreen)
 481 {
 482    struct nvc0_screen *screen = nvc0_screen(pscreen);
 483
 484    if (!nouveau_drm_screen_unref(&screen->base))
 485       return;
 486
 487    if (screen->base.fence.current) {
 488       struct nouveau_fence *current = NULL;
 489
 490       /* nouveau_fence_wait will create a new current fence, so wait on the
 491        * _current_ one, and remove both.
 492        */
 493       nouveau_fence_ref(screen->base.fence.current, &current);
 494       nouveau_fence_wait(current, NULL);
 495       nouveau_fence_ref(NULL, &current);
 496       nouveau_fence_ref(NULL, &screen->base.fence.current);
 497    }
 498    if (screen->base.pushbuf)
 499       screen->base.pushbuf->user_priv = NULL;
 500
 501    if (screen->blitter)
 502       nvc0_blitter_destroy(screen);
 503    if (screen->pm.prog) {
 504       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 505       nvc0_program_destroy(NULL, screen->pm.prog);
 506       FREE(screen->pm.prog);
 507    }
 508
 509    nouveau_bo_ref(NULL, &screen->text);
 510    nouveau_bo_ref(NULL, &screen->uniform_bo);
 511    nouveau_bo_ref(NULL, &screen->tls);
 512    nouveau_bo_ref(NULL, &screen->txc);
 513    nouveau_bo_ref(NULL, &screen->fence.bo);
 514    nouveau_bo_ref(NULL, &screen->poly_cache);
 515    nouveau_bo_ref(NULL, &screen->parm);
 516
 517    nouveau_heap_destroy(&screen->lib_code);
 518    nouveau_heap_destroy(&screen->text_heap);
 519
 520    FREE(screen->tic.entries);
 521
 522    nouveau_object_del(&screen->eng3d);
 523    nouveau_object_del(&screen->eng2d);
 524    nouveau_object_del(&screen->m2mf);
 525    nouveau_object_del(&screen->compute);
 526    nouveau_object_del(&screen->nvsw);
 527
 528    nouveau_screen_fini(&screen->base);
 529
 530    FREE(screen);
 531 }
 532
 533 static int
 534 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 535                      unsigned size, const uint32_t *data)
 536 {
 537    struct nouveau_pushbuf *push = screen->base.pushbuf;
 538
 539    size /= 4;
 540
 541    assert((pos + size) <= 0x800);
 542
 543    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 544    PUSH_DATA (push, (m - 0x3800) / 8);
 545    PUSH_DATA (push, pos);
 546    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 547    PUSH_DATA (push, pos);
 548    PUSH_DATAp(push, data, size);
 549
 550    return pos + size;
 551 }
 552
 553 static void
 554 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 555 {
 556    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 557    PUSH_DATA (push, 0xff);
 558    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 559    PUSH_DATA (push, 0xff);
 560    PUSH_DATA (push, 0xff);
 561    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 562    PUSH_DATA (push, 0xff);
 563    PUSH_DATA (push, 0xff);
 564    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 565    PUSH_DATA (push, 0x3f);
 566
 567    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 568    PUSH_DATA (push, (3 << 16) | 3);
 569    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 570    PUSH_DATA (push, (2 << 16) | 2);
 571
 572    if (obj_class < GM107_3D_CLASS) {
 573       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 574       PUSH_DATA (push, 0);
 575    }
 576    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 577    PUSH_DATA (push, 0x10);
 578    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 579    PUSH_DATA (push, 0x10);
 580    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 581    PUSH_DATA (push, 0x10);
 582    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 583    PUSH_DATA (push, 0x10);
 584    PUSH_DATA (push, 0x10);
 585    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 586    PUSH_DATA (push, 0x10);
 587    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 588    PUSH_DATA (push, 0xe);
 589
 590    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 591    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 592    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 593    PUSH_DATA (push, 0);
 594    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 595    PUSH_DATA (push, 3);
 596
 597    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 598    PUSH_DATA (push, 0x3fffff);
 599    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 600    PUSH_DATA (push, 1);
 601    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 602    PUSH_DATA (push, 1);
 603
 604    if (obj_class < GM107_3D_CLASS) {
 605       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 606       PUSH_DATA (push, 3);
 607
 608       if (obj_class >= NVE4_3D_CLASS) {
 609          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 610          PUSH_DATA (push, 1);
 611       }
 612    }
 613
 614    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 615     * are supposed to do */
 616 }
 617
 618 static void
 619 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 620 {
 621    struct nvc0_screen *screen = nvc0_screen(pscreen);
 622    struct nouveau_pushbuf *push = screen->base.pushbuf;
 623
 624    /* we need to do it after possible flush in MARK_RING */
 625    *sequence = ++screen->base.fence.sequence;
 626
 627    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 628    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 629    PUSH_DATAh(push, screen->fence.bo->offset);
 630    PUSH_DATA (push, screen->fence.bo->offset);
 631    PUSH_DATA (push, *sequence);
 632    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 633               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 634 }
 635
 636 static u32
 637 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 638 {
 639    struct nvc0_screen *screen = nvc0_screen(pscreen);
 640    return screen->fence.map[0];
 641 }
 642
 643 static int
 644 nvc0_screen_init_compute(struct nvc0_screen *screen)
 645 {
 646    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 647
 648    switch (screen->base.device->chipset & ~0xf) {
 649    case 0xc0:
 650    case 0xd0:
 651       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 652    case 0xe0:
 653       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 654    case 0xf0:
 655    case 0x100:
 656    case 0x110:
 657    case 0x120:
 658       if (debug_get_bool_option("NVF0_COMPUTE", false))
 659          return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 660       return 0;
 661    default:
 662       return -1;
 663    }
 664 }
 665
 666 bool
 667 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 668                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 669 {
 670    struct nouveau_bo *bo = NULL;
 671    int ret;
 672    uint64_t size = (lpos + lneg) * 32 + cstack;
 673
 674    if (size >= (1 << 20)) {
 675       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 676       return false;
 677    }
 678
 679    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 680    size  = align(size, 0x8000);
 681    size *= screen->mp_count;
 682
 683    size = align(size, 1 << 17);
 684
 685    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 686                         NULL, &bo);
 687    if (ret) {
 688       NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
 689       return false;
 690    }
 691    nouveau_bo_ref(NULL, &screen->tls);
 692    screen->tls = bo;
 693    return true;
 694 }
 695
 696 #define FAIL_SCREEN_INIT(str, err)                    \
 697    do {                                               \
 698       NOUVEAU_ERR(str, err);                          \
 699       goto fail;                                      \
 700    } while(0)
 701
 702 struct nouveau_screen *
 703 nvc0_screen_create(struct nouveau_device *dev)
 704 {
 705    struct nvc0_screen *screen;
 706    struct pipe_screen *pscreen;
 707    struct nouveau_object *chan;
 708    struct nouveau_pushbuf *push;
 709    uint64_t value;
 710    uint32_t obj_class;
 711    uint32_t flags;
 712    int ret;
 713    unsigned i;
 714
 715    switch (dev->chipset & ~0xf) {
 716    case 0xc0:
 717    case 0xd0:
 718    case 0xe0:
 719    case 0xf0:
 720    case 0x100:
 721    case 0x110:
 722    case 0x120:
 723       break;
 724    default:
 725       return NULL;
 726    }
 727
 728    screen = CALLOC_STRUCT(nvc0_screen);
 729    if (!screen)
 730       return NULL;
 731    pscreen = &screen->base.base;
 732    pscreen->destroy = nvc0_screen_destroy;
 733
 734    ret = nouveau_screen_init(&screen->base, dev);
 735    if (ret) {
 736       nvc0_screen_destroy(pscreen);
 737       return NULL;
 738    }
 739    chan = screen->base.channel;
 740    push = screen->base.pushbuf;
 741    push->user_priv = screen;
 742    push->rsvd_kick = 5;
 743
 744    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 745       PIPE_BIND_SHADER_BUFFER |
 746       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 747       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
 748    screen->base.sysmem_bindings |=
 749       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 750
 751    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
 752       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
 753       screen->base.vidmem_bindings = 0;
 754    }
 755
 756    pscreen->context_create = nvc0_create;
 757    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 758    pscreen->get_param = nvc0_screen_get_param;
 759    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 760    pscreen->get_paramf = nvc0_screen_get_paramf;
 761    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 762    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 763
 764    nvc0_screen_init_resource_functions(pscreen);
 765
 766    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 767    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 768
 769    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
 770    if (screen->base.drm->version >= 0x01000202)
 771       flags |= NOUVEAU_BO_COHERENT;
 772
 773    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
 774    if (ret)
 775       goto fail;
 776    nouveau_bo_map(screen->fence.bo, 0, NULL);
 777    screen->fence.map = screen->fence.bo->map;
 778    screen->base.fence.emit = nvc0_screen_fence_emit;
 779    screen->base.fence.update = nvc0_screen_fence_update;
 780
 781
 782    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
 783                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
 784    if (ret)
 785       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 786
 787    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
 788    PUSH_DATA (push, screen->nvsw->handle);
 789
 790    switch (dev->chipset & ~0xf) {
 791    case 0x120:
 792    case 0x110:
 793    case 0x100:
 794    case 0xf0:
 795       obj_class = NVF0_P2MF_CLASS;
 796       break;
 797    case 0xe0:
 798       obj_class = NVE4_P2MF_CLASS;
 799       break;
 800    default:
 801       obj_class = NVC0_M2MF_CLASS;
 802       break;
 803    }
 804    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 805                             &screen->m2mf);
 806    if (ret)
 807       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 808
 809    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 810    PUSH_DATA (push, screen->m2mf->oclass);
 811    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 812       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 813       PUSH_DATA (push, 0xa0b5);
 814    }
 815
 816    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 817                             &screen->eng2d);
 818    if (ret)
 819       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 820
 821    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 822    PUSH_DATA (push, screen->eng2d->oclass);
 823    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
 824    PUSH_DATA (push, 0);
 825    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 826    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 827    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 828    PUSH_DATA (push, 0);
 829    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 830    PUSH_DATA (push, 0);
 831    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 832    PUSH_DATA (push, 0x3f);
 833    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 834    PUSH_DATA (push, 1);
 835    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
 836    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 837
 838    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 839    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 840    PUSH_DATA (push, screen->fence.bo->offset + 16);
 841
 842    switch (dev->chipset & ~0xf) {
 843    case 0x120:
 844       obj_class = GM200_3D_CLASS;
 845       break;
 846    case 0x110:
 847       obj_class = GM107_3D_CLASS;
 848       break;
 849    case 0x100:
 850    case 0xf0:
 851       obj_class = NVF0_3D_CLASS;
 852       break;
 853    case 0xe0:
 854       switch (dev->chipset) {
 855       case 0xea:
 856          obj_class = NVEA_3D_CLASS;
 857          break;
 858       default:
 859          obj_class = NVE4_3D_CLASS;
 860          break;
 861       }
 862       break;
 863    case 0xd0:
 864       obj_class = NVC8_3D_CLASS;
 865       break;
 866    case 0xc0:
 867    default:
 868       switch (dev->chipset) {
 869       case 0xc8:
 870          obj_class = NVC8_3D_CLASS;
 871          break;
 872       case 0xc1:
 873          obj_class = NVC1_3D_CLASS;
 874          break;
 875       default:
 876          obj_class = NVC0_3D_CLASS;
 877          break;
 878       }
 879       break;
 880    }
 881    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 882                             &screen->eng3d);
 883    if (ret)
 884       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 885    screen->base.class_3d = obj_class;
 886
 887    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 888    PUSH_DATA (push, screen->eng3d->oclass);
 889
 890    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 891    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 892
 893    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 894       /* kill shaders after about 1 second (at 100 MHz) */
 895       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 896       PUSH_DATA (push, 0x17);
 897    }
 898
 899    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
 900                     screen->base.drm->version >= 0x01000101);
 901    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 902    for (i = 0; i < 8; ++i)
 903            PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 904
 905    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 906    PUSH_DATA (push, 1);
 907
 908    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 909    PUSH_DATA (push, 0);
 910    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 911    PUSH_DATA (push, 0);
 912    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 913    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 914    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 915    PUSH_DATA (push, 0);
 916    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 917    PUSH_DATA (push, 1);
 918    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 919    PUSH_DATA (push, 1);
 920    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 921    PUSH_DATA (push, 1);
 922    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 923    PUSH_DATA (push, 0);
 924    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
 925    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
 926    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 927       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
 928    } else {
 929       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
 930       PUSH_DATA (push, 15);
 931    }
 932    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
 933    PUSH_DATA (push, 8); /* 128 */
 934    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
 935    PUSH_DATA (push, 1);
 936    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
 937       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
 938       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
 939    }
 940
 941    nvc0_magic_3d_init(push, screen->eng3d->oclass);
 942
 943    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
 944                         &screen->text);
 945    if (ret)
 946       goto fail;
 947
 948    /* XXX: getting a page fault at the end of the code buffer every few
 949     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 950     */
 951    nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
 952
 953    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
 954                         &screen->uniform_bo);
 955    if (ret)
 956       goto fail;
 957
 958    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
 959
 960    for (i = 0; i < 5; ++i) {
 961       /* TIC and TSC entries for each unit (nve4+ only) */
 962       /* auxiliary constants (6 user clip planes, base instance id) */
 963       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 964       PUSH_DATA (push, 2048);
 965       PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
 966       PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
 967       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
 968       PUSH_DATA (push, (15 << 4) | 1);
 969       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
 970          unsigned j;
 971          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
 972          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
 973          for (j = 0; j < 8; ++j)
 974             PUSH_DATA(push, j);
 975       } else {
 976          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
 977          PUSH_DATA (push, 0x54);
 978       }
 979    }
 980    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
 981    PUSH_DATA (push, 0);
 982
 983    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
 984    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 985    PUSH_DATA (push, 256);
 986    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 987    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 988    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
 989    PUSH_DATA (push, 0);
 990    PUSH_DATAf(push, 0.0f);
 991    PUSH_DATAf(push, 0.0f);
 992    PUSH_DATAf(push, 0.0f);
 993    PUSH_DATAf(push, 0.0f);
 994    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 995    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 996    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 997
 998    if (screen->base.drm->version >= 0x01000101) {
 999       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1000       if (ret) {
1001          NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
1002          goto fail;
1003       }
1004    } else {
1005       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1006          value = (8 << 8) | 4;
1007       else
1008          value = (16 << 8) | 4;
1009    }
1010    screen->gpc_count = value & 0x000000ff;
1011    screen->mp_count = value >> 8;
1012    screen->mp_count_compute = screen->mp_count;
1013
1014    nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1015
1016    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
1017    PUSH_DATAh(push, screen->text->offset);
1018    PUSH_DATA (push, screen->text->offset);
1019    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1020    PUSH_DATAh(push, screen->tls->offset);
1021    PUSH_DATA (push, screen->tls->offset);
1022    PUSH_DATA (push, screen->tls->size >> 32);
1023    PUSH_DATA (push, screen->tls->size);
1024    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1025    PUSH_DATA (push, 0);
1026    /* Reduce likelihood of collision with real buffers by placing the hole at
1027     * the top of the 4G area. This will have to be dealt with for real
1028     * eventually by blocking off that area from the VM.
1029     */
1030    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1031    PUSH_DATA (push, 0xff << 24);
1032
1033    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1034       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1035                            &screen->poly_cache);
1036       if (ret)
1037          goto fail;
1038
1039       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1040       PUSH_DATAh(push, screen->poly_cache->offset);
1041       PUSH_DATA (push, screen->poly_cache->offset);
1042       PUSH_DATA (push, 3);
1043    }
1044
1045    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1046                         &screen->txc);
1047    if (ret)
1048       goto fail;
1049
1050    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1051    PUSH_DATAh(push, screen->txc->offset);
1052    PUSH_DATA (push, screen->txc->offset);
1053    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1054    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1055       screen->tic.maxwell = true;
1056       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1057          screen->tic.maxwell =
1058             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1059          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1060       }
1061    }
1062
1063    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1064    PUSH_DATAh(push, screen->txc->offset + 65536);
1065    PUSH_DATA (push, screen->txc->offset + 65536);
1066    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1067
1068    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1069    PUSH_DATA (push, 0);
1070    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1071    PUSH_DATA (push, 0);
1072    PUSH_DATA (push, 0);
1073    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1074    PUSH_DATA (push, 0x3f);
1075
1076    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1077    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1078    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1079    for (i = 0; i < 8 * 2; ++i)
1080       PUSH_DATA(push, 0);
1081    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1082    PUSH_DATA (push, 0);
1083    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1084    PUSH_DATA (push, 0);
1085
1086    /* neither scissors, viewport nor stencil mask should affect clears */
1087    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1088    PUSH_DATA (push, 0);
1089
1090    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1091    PUSH_DATA (push, 1);
1092    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1093       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1094       PUSH_DATAf(push, 0.0f);
1095       PUSH_DATAf(push, 1.0f);
1096    }
1097    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1098    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1099
1100    /* We use scissors instead of exact view volume clipping,
1101     * so they're always enabled.
1102     */
1103    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1104       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1105       PUSH_DATA (push, 1);
1106       PUSH_DATA (push, 8192 << 16);
1107       PUSH_DATA (push, 8192 << 16);
1108    }
1109
1110 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1111
1112    i = 0;
1113    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1114    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1115    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1116    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1117    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1118    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1119    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1120    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1121    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1122    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1123    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1124    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1125    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1126
1127    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1128    PUSH_DATA (push, 1);
1129    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1130    PUSH_DATA (push, 1);
1131    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1132    PUSH_DATA (push, 0x40);
1133    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1134    PUSH_DATA (push, 0);
1135    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1136    PUSH_DATA (push, 0x30);
1137    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1138    PUSH_DATA (push, 3);
1139    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1140    PUSH_DATA (push, 0x20);
1141    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1142    PUSH_DATA (push, 0x00);
1143    screen->save_state.patch_vertices = 3;
1144
1145    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1146    PUSH_DATA (push, 0);
1147    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1148    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1149
1150    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1151
1152    if (nvc0_screen_init_compute(screen))
1153       goto fail;
1154
1155    PUSH_KICK (push);
1156
1157    screen->tic.entries = CALLOC(4096, sizeof(void *));
1158    screen->tsc.entries = screen->tic.entries + 2048;
1159
1160    if (!nvc0_blitter_create(screen))
1161       goto fail;
1162
1163    nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1164
1165    return &screen->base;
1166
1167 fail:
1168    screen->base.base.context_create = NULL;
1169    return &screen->base;
1170 }
1171
1172 int
1173 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1174 {
1175    int i = screen->tic.next;
1176
1177    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1178       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1179
1180    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1181
1182    if (screen->tic.entries[i])
1183       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1184
1185    screen->tic.entries[i] = entry;
1186    return i;
1187 }
1188
1189 int
1190 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1191 {
1192    int i = screen->tsc.next;
1193
1194    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1195       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1196
1197    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1198
1199    if (screen->tsc.entries[i])
1200       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1201
1202    screen->tsc.entries[i] = entry;
1203    return i;
1204 }