src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "vl/vl_decoder.h"
  28 #include "vl/vl_video_buffer.h"
  29
  30 #include "nouveau_vp3_video.h"
  31
  32 #include "nvc0/nvc0_context.h"
  33 #include "nvc0/nvc0_screen.h"
  34
  35 #include "nvc0/nvc0_graph_macros.h"
  36
  37 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  38 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  39 #endif
  40
  41 static boolean
  42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  43                                 enum pipe_format format,
  44                                 enum pipe_texture_target target,
  45                                 unsigned sample_count,
  46                                 unsigned bindings)
  47 {
  48    if (sample_count > 8)
  49       return FALSE;
  50    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  51       return FALSE;
  52
  53    if (!util_format_is_supported(format, bindings))
  54       return FALSE;
  55
  56    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  57       if (util_format_get_blocksizebits(format) == 3 * 32)
  58          return FALSE;
  59
  60    /* transfers & shared are always supported */
  61    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  62                  PIPE_BIND_TRANSFER_WRITE |
  63                  PIPE_BIND_SHARED);
  64
  65    return (nvc0_format_table[format].usage & bindings) == bindings;
  66 }
  67
  68 static int
  69 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  70 {
  71    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  72
  73    switch (param) {
  74    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  75    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  76       return 15;
  77    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  78       return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
  79    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  80       return 2048;
  81    case PIPE_CAP_MIN_TEXEL_OFFSET:
  82       return -8;
  83    case PIPE_CAP_MAX_TEXEL_OFFSET:
  84       return 7;
  85    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  86    case PIPE_CAP_TEXTURE_SWIZZLE:
  87    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  88    case PIPE_CAP_NPOT_TEXTURES:
  89    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  90    case PIPE_CAP_ANISOTROPIC_FILTER:
  91    case PIPE_CAP_SEAMLESS_CUBE_MAP:
  92    case PIPE_CAP_CUBE_MAP_ARRAY:
  93    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  94    case PIPE_CAP_TEXTURE_MULTISAMPLE:
  95       return 1;
  96    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
  97       return 65536;
  98    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  99       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 100    case PIPE_CAP_TWO_SIDED_STENCIL:
 101    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 102    case PIPE_CAP_POINT_SPRITE:
 103    case PIPE_CAP_TGSI_TEXCOORD:
 104       return 1;
 105    case PIPE_CAP_SM3:
 106       return 1;
 107    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 108       return 330;
 109    case PIPE_CAP_MAX_RENDER_TARGETS:
 110       return 8;
 111    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 112       return 1;
 113    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 114    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 115    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 116       return 1;
 117    case PIPE_CAP_QUERY_TIMESTAMP:
 118    case PIPE_CAP_QUERY_TIME_ELAPSED:
 119    case PIPE_CAP_OCCLUSION_QUERY:
 120    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 121    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 122       return 1;
 123    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 124       return 4;
 125    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 126    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 127       return 128;
 128    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 129    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 130       return 1024;
 131    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 132    case PIPE_CAP_INDEP_BLEND_ENABLE:
 133    case PIPE_CAP_INDEP_BLEND_FUNC:
 134       return 1;
 135    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 136    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 137       return 1;
 138    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 139    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 140       return 0;
 141    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 142       return 0;
 143    case PIPE_CAP_PRIMITIVE_RESTART:
 144    case PIPE_CAP_TGSI_INSTANCEID:
 145    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 146    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 147    case PIPE_CAP_CONDITIONAL_RENDER:
 148    case PIPE_CAP_TEXTURE_BARRIER:
 149    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 150    case PIPE_CAP_START_INSTANCE:
 151       return 1;
 152    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 153       return 0; /* state trackers will know better */
 154    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 155    case PIPE_CAP_USER_INDEX_BUFFERS:
 156    case PIPE_CAP_USER_VERTEX_BUFFERS:
 157       return 1;
 158    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 159       return 256;
 160    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 161       return 1; /* 256 for binding as RT, but that's not possible in GL */
 162    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 163       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 164    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 165    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 166    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 167       return 0;
 168    case PIPE_CAP_COMPUTE:
 169       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 170    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 171       return 1;
 172    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 173       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 174    case PIPE_CAP_ENDIANNESS:
 175       return PIPE_ENDIAN_LITTLE;
 176    case PIPE_CAP_TGSI_VS_LAYER:
 177       return 0;
 178    case PIPE_CAP_MAX_VIEWPORTS:
 179       return 1;
 180    default:
 181       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 182       return 0;
 183    }
 184 }
 185
 186 static int
 187 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 188                              enum pipe_shader_cap param)
 189 {
 190    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 191
 192    switch (shader) {
 193    case PIPE_SHADER_VERTEX:
 194       /*
 195    case PIPE_SHADER_TESSELLATION_CONTROL:
 196    case PIPE_SHADER_TESSELLATION_EVALUATION:
 197       */
 198    case PIPE_SHADER_GEOMETRY:
 199    case PIPE_SHADER_FRAGMENT:
 200       break;
 201    case PIPE_SHADER_COMPUTE:
 202       if (class_3d < NVE4_3D_CLASS)
 203          return 0;
 204       break;
 205    default:
 206       return 0;
 207    }
 208
 209    switch (param) {
 210    case PIPE_SHADER_CAP_PREFERRED_IR:
 211       return PIPE_SHADER_IR_TGSI;
 212    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 213    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 214    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 215    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 216       return 16384;
 217    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 218       return 16;
 219    case PIPE_SHADER_CAP_MAX_INPUTS:
 220       if (shader == PIPE_SHADER_VERTEX)
 221          return 32;
 222       /* NOTE: These only count our slots for GENERIC varyings.
 223        * The address space may be larger, but the actual hard limit seems to be
 224        * less than what the address space layout permits, so don't add TEXCOORD,
 225        * COLOR, etc. here.
 226        */
 227       if (shader == PIPE_SHADER_FRAGMENT)
 228          return 0x1f0 / 16;
 229       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 230        * and excludes 0x60 per-patch inputs.
 231        */
 232       return 0x200 / 16;
 233    case PIPE_SHADER_CAP_MAX_CONSTS:
 234       return 65536 / 16;
 235    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 236       if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
 237          return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
 238       return NVC0_MAX_PIPE_CONSTBUFS;
 239    case PIPE_SHADER_CAP_MAX_ADDRS:
 240       return 1;
 241    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 242    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 243       return shader != PIPE_SHADER_FRAGMENT;
 244    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 245    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 246       return 1;
 247    case PIPE_SHADER_CAP_MAX_PREDS:
 248       return 0;
 249    case PIPE_SHADER_CAP_MAX_TEMPS:
 250       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 251    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 252       return 1;
 253    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 254       return 0;
 255    case PIPE_SHADER_CAP_SUBROUTINES:
 256       return 1;
 257    case PIPE_SHADER_CAP_INTEGERS:
 258       return 1;
 259    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 260       return 16; /* would be 32 in linked (OpenGL-style) mode */
 261    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 262       return 16; /* XXX not sure if more are really safe */
 263    default:
 264       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 265       return 0;
 266    }
 267 }
 268
 269 static float
 270 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 271 {
 272    switch (param) {
 273    case PIPE_CAPF_MAX_LINE_WIDTH:
 274    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 275       return 10.0f;
 276    case PIPE_CAPF_MAX_POINT_WIDTH:
 277       return 63.0f;
 278    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 279       return 63.375f;
 280    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 281       return 16.0f;
 282    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 283       return 15.0f;
 284    default:
 285       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 286       return 0.0f;
 287    }
 288 }
 289
 290 static int
 291 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 292                               enum pipe_compute_cap param, void *data)
 293 {
 294    uint64_t *data64 = (uint64_t *)data;
 295    const uint16_t obj_class = nvc0_screen(pscreen)->compute->oclass;
 296
 297    switch (param) {
 298    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 299       data64[0] = 3;
 300       return 8;
 301    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 302       data64[0] = (obj_class >= NVE4_COMPUTE_CLASS) ? 0x7fffffff : 65535;
 303       data64[1] = 65535;
 304       data64[2] = 65535;
 305       return 24;
 306    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 307       data64[0] = 1024;
 308       data64[1] = 1024;
 309       data64[2] = 64;
 310       return 24;
 311    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 312       data64[0] = 1024;
 313       return 8;
 314    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 315       data64[0] = (uint64_t)1 << 40;
 316       return 8;
 317    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 318       data64[0] = 48 << 10;
 319       return 8;
 320    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 321       data64[0] = 512 << 10;
 322       return 8;
 323    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 324       data64[0] = 4096;
 325       return 8;
 326    default:
 327       return 0;
 328    }
 329 }
 330
 331 static void
 332 nvc0_screen_destroy(struct pipe_screen *pscreen)
 333 {
 334    struct nvc0_screen *screen = nvc0_screen(pscreen);
 335
 336    if (!nouveau_drm_screen_unref(&screen->base))
 337       return;
 338
 339    if (screen->base.fence.current) {
 340       nouveau_fence_wait(screen->base.fence.current);
 341       nouveau_fence_ref(NULL, &screen->base.fence.current);
 342    }
 343    if (screen->base.pushbuf)
 344       screen->base.pushbuf->user_priv = NULL;
 345
 346    if (screen->blitter)
 347       nvc0_blitter_destroy(screen);
 348    if (screen->pm.prog) {
 349       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 350       nvc0_program_destroy(NULL, screen->pm.prog);
 351    }
 352
 353    nouveau_bo_ref(NULL, &screen->text);
 354    nouveau_bo_ref(NULL, &screen->uniform_bo);
 355    nouveau_bo_ref(NULL, &screen->tls);
 356    nouveau_bo_ref(NULL, &screen->txc);
 357    nouveau_bo_ref(NULL, &screen->fence.bo);
 358    nouveau_bo_ref(NULL, &screen->poly_cache);
 359    nouveau_bo_ref(NULL, &screen->parm);
 360
 361    nouveau_heap_destroy(&screen->lib_code);
 362    nouveau_heap_destroy(&screen->text_heap);
 363
 364    FREE(screen->tic.entries);
 365
 366    nouveau_mm_destroy(screen->mm_VRAM_fe0);
 367
 368    nouveau_object_del(&screen->eng3d);
 369    nouveau_object_del(&screen->eng2d);
 370    nouveau_object_del(&screen->m2mf);
 371    nouveau_object_del(&screen->compute);
 372    nouveau_object_del(&screen->nvsw);
 373
 374    nouveau_screen_fini(&screen->base);
 375
 376    FREE(screen);
 377 }
 378
 379 static int
 380 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 381                      unsigned size, const uint32_t *data)
 382 {
 383    struct nouveau_pushbuf *push = screen->base.pushbuf;
 384
 385    size /= 4;
 386
 387    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 388    PUSH_DATA (push, (m - 0x3800) / 8);
 389    PUSH_DATA (push, pos);
 390    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 391    PUSH_DATA (push, pos);
 392    PUSH_DATAp(push, data, size);
 393
 394    return pos + size;
 395 }
 396
 397 static void
 398 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 399 {
 400    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 401    PUSH_DATA (push, 0xff);
 402    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 403    PUSH_DATA (push, 0xff);
 404    PUSH_DATA (push, 0xff);
 405    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 406    PUSH_DATA (push, 0xff);
 407    PUSH_DATA (push, 0xff);
 408    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 409    PUSH_DATA (push, 0x3f);
 410
 411    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 412    PUSH_DATA (push, (3 << 16) | 3);
 413    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 414    PUSH_DATA (push, (2 << 16) | 2);
 415    BEGIN_NVC0(push, SUBC_3D(0x0de8), 1);
 416    PUSH_DATA (push, 1);
 417
 418    BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 419    PUSH_DATA (push, 0);
 420    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 421    PUSH_DATA (push, 0x10);
 422    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 423    PUSH_DATA (push, 0x10);
 424    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 425    PUSH_DATA (push, 0x10);
 426    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 427    PUSH_DATA (push, 0x10);
 428    PUSH_DATA (push, 0x10);
 429    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 430    PUSH_DATA (push, 0x10);
 431    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 432    PUSH_DATA (push, 0xe);
 433
 434    BEGIN_NVC0(push, SUBC_3D(0x164c), 1);
 435    PUSH_DATA (push, 1 << 12);
 436    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 437    PUSH_DATA (push, 0);
 438    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 439    PUSH_DATA (push, 3);
 440
 441    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 442    PUSH_DATA (push, 0x3fffff);
 443    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 444    PUSH_DATA (push, 1);
 445    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 446    PUSH_DATA (push, 1);
 447    BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 448    PUSH_DATA (push, 3);
 449
 450    if (obj_class >= NVE4_3D_CLASS) {
 451       BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 452       PUSH_DATA (push, 1);
 453    }
 454
 455    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 456     * are supposed to do */
 457 }
 458
 459 static void
 460 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 461 {
 462    struct nvc0_screen *screen = nvc0_screen(pscreen);
 463    struct nouveau_pushbuf *push = screen->base.pushbuf;
 464
 465    /* we need to do it after possible flush in MARK_RING */
 466    *sequence = ++screen->base.fence.sequence;
 467
 468    BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4);
 469    PUSH_DATAh(push, screen->fence.bo->offset);
 470    PUSH_DATA (push, screen->fence.bo->offset);
 471    PUSH_DATA (push, *sequence);
 472    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 473               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 474 }
 475
 476 static u32
 477 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 478 {
 479    struct nvc0_screen *screen = nvc0_screen(pscreen);
 480    return screen->fence.map[0];
 481 }
 482
 483 static int
 484 nvc0_screen_init_compute(struct nvc0_screen *screen)
 485 {
 486    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 487
 488    switch (screen->base.device->chipset & ~0xf) {
 489    case 0xc0:
 490    case 0xd0:
 491       /* Using COMPUTE has weird effects on 3D state, we need to
 492        * investigate this further before enabling it by default.
 493        */
 494       if (debug_get_bool_option("NVC0_COMPUTE", FALSE))
 495          return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 496       return 0;
 497    case 0xe0:
 498    case 0xf0:
 499    case 0x100:
 500       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 501    default:
 502       return -1;
 503    }
 504 }
 505
 506 boolean
 507 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 508                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 509 {
 510    struct nouveau_bo *bo = NULL;
 511    int ret;
 512    uint64_t size = (lpos + lneg) * 32 + cstack;
 513
 514    if (size >= (1 << 20)) {
 515       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 516       return FALSE;
 517    }
 518
 519    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 520    size  = align(size, 0x8000);
 521    size *= screen->mp_count;
 522
 523    size = align(size, 1 << 17);
 524
 525    ret = nouveau_bo_new(screen->base.device, NOUVEAU_BO_VRAM, 1 << 17, size,
 526                         NULL, &bo);
 527    if (ret) {
 528       NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
 529       return FALSE;
 530    }
 531    nouveau_bo_ref(NULL, &screen->tls);
 532    screen->tls = bo;
 533    return TRUE;
 534 }
 535
 536 #define FAIL_SCREEN_INIT(str, err)                    \
 537    do {                                               \
 538       NOUVEAU_ERR(str, err);                          \
 539       nvc0_screen_destroy(pscreen);                   \
 540       return NULL;                                    \
 541    } while(0)
 542
 543 struct pipe_screen *
 544 nvc0_screen_create(struct nouveau_device *dev)
 545 {
 546    struct nvc0_screen *screen;
 547    struct pipe_screen *pscreen;
 548    struct nouveau_object *chan;
 549    struct nouveau_pushbuf *push;
 550    uint64_t value;
 551    uint32_t obj_class;
 552    int ret;
 553    unsigned i;
 554    union nouveau_bo_config mm_config;
 555
 556    switch (dev->chipset & ~0xf) {
 557    case 0xc0:
 558    case 0xd0:
 559    case 0xe0:
 560    case 0xf0:
 561    case 0x100:
 562       break;
 563    default:
 564       return NULL;
 565    }
 566
 567    screen = CALLOC_STRUCT(nvc0_screen);
 568    if (!screen)
 569       return NULL;
 570    pscreen = &screen->base.base;
 571
 572    ret = nouveau_screen_init(&screen->base, dev);
 573    if (ret) {
 574       nvc0_screen_destroy(pscreen);
 575       return NULL;
 576    }
 577    chan = screen->base.channel;
 578    push = screen->base.pushbuf;
 579    push->user_priv = screen;
 580    push->rsvd_kick = 5;
 581
 582    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 583       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 584    screen->base.sysmem_bindings |=
 585       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 586
 587    pscreen->destroy = nvc0_screen_destroy;
 588    pscreen->context_create = nvc0_create;
 589    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 590    pscreen->get_param = nvc0_screen_get_param;
 591    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 592    pscreen->get_paramf = nvc0_screen_get_paramf;
 593    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 594
 595    nvc0_screen_init_resource_functions(pscreen);
 596
 597    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 598    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 599
 600    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL,
 601                         &screen->fence.bo);
 602    if (ret)
 603       goto fail;
 604    nouveau_bo_map(screen->fence.bo, 0, NULL);
 605    screen->fence.map = screen->fence.bo->map;
 606    screen->base.fence.emit = nvc0_screen_fence_emit;
 607    screen->base.fence.update = nvc0_screen_fence_update;
 608
 609
 610    ret = nouveau_object_new(chan,
 611                             (dev->chipset < 0xe0) ? 0x1f906e : 0x906e, 0x906e,
 612                             NULL, 0, &screen->nvsw);
 613    if (ret)
 614       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 615
 616
 617    switch (dev->chipset & ~0xf) {
 618    case 0x100:
 619    case 0xf0:
 620       obj_class = NVF0_P2MF_CLASS;
 621       break;
 622    case 0xe0:
 623       obj_class = NVE4_P2MF_CLASS;
 624       break;
 625    default:
 626       obj_class = NVC0_M2MF_CLASS;
 627       break;
 628    }
 629    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 630                             &screen->m2mf);
 631    if (ret)
 632       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 633
 634    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 635    PUSH_DATA (push, screen->m2mf->oclass);
 636    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 637       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 638       PUSH_DATA (push, 0xa0b5);
 639    }
 640
 641    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 642                             &screen->eng2d);
 643    if (ret)
 644       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 645
 646    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 647    PUSH_DATA (push, screen->eng2d->oclass);
 648    BEGIN_NVC0(push, NVC0_2D(SINGLE_GPC), 1);
 649    PUSH_DATA (push, 0);
 650    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 651    PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY);
 652    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 653    PUSH_DATA (push, 0);
 654    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 655    PUSH_DATA (push, 0);
 656    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 657    PUSH_DATA (push, 0x3f);
 658    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 659    PUSH_DATA (push, 1);
 660
 661    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 662    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 663    PUSH_DATA (push, screen->fence.bo->offset + 16);
 664
 665    switch (dev->chipset & ~0xf) {
 666    case 0x100:
 667    case 0xf0:
 668       obj_class = NVF0_3D_CLASS;
 669       break;
 670    case 0xe0:
 671       obj_class = NVE4_3D_CLASS;
 672       break;
 673    case 0xd0:
 674       obj_class = NVC8_3D_CLASS;
 675       break;
 676    case 0xc0:
 677    default:
 678       switch (dev->chipset) {
 679       case 0xc8:
 680          obj_class = NVC8_3D_CLASS;
 681          break;
 682       case 0xc1:
 683          obj_class = NVC1_3D_CLASS;
 684          break;
 685       default:
 686          obj_class = NVC0_3D_CLASS;
 687          break;
 688       }
 689       break;
 690    }
 691    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 692                             &screen->eng3d);
 693    if (ret)
 694       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 695    screen->base.class_3d = obj_class;
 696
 697    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 698    PUSH_DATA (push, screen->eng3d->oclass);
 699
 700    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 701    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 702
 703    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 704       /* kill shaders after about 1 second (at 100 MHz) */
 705       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 706       PUSH_DATA (push, 0x17);
 707    }
 708
 709    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE), dev->drm_version >= 0x01000101);
 710    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 711    for (i = 0; i < 8; ++i)
 712            PUSH_DATA(push, dev->drm_version >= 0x01000101);
 713
 714    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 715    PUSH_DATA (push, 1);
 716
 717    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 718    PUSH_DATA (push, 0);
 719    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 720    PUSH_DATA (push, 0);
 721    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 722    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 723    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 724    PUSH_DATA (push, 0);
 725    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 726    PUSH_DATA (push, 1);
 727    BEGIN_NVC0(push, NVC0_3D(LINE_LAST_PIXEL), 1);
 728    PUSH_DATA (push, 0);
 729    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 730    PUSH_DATA (push, 1);
 731    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 732    PUSH_DATA (push, 0);
 733    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 734       BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
 735       PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 736    } else {
 737       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
 738       PUSH_DATA (push, 15);
 739    }
 740    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
 741    PUSH_DATA (push, 8); /* 128 */
 742    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
 743    PUSH_DATA (push, 1);
 744    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
 745       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
 746       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
 747    }
 748
 749    nvc0_magic_3d_init(push, screen->eng3d->oclass);
 750
 751    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
 752                         &screen->text);
 753    if (ret)
 754       goto fail;
 755
 756    /* XXX: getting a page fault at the end of the code buffer every few
 757     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 758     */
 759    nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
 760
 761    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
 762                         &screen->uniform_bo);
 763    if (ret)
 764       goto fail;
 765
 766    PUSH_REFN (push, screen->uniform_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 767
 768    for (i = 0; i < 5; ++i) {
 769       /* TIC and TSC entries for each unit (nve4+ only) */
 770       /* auxiliary constants (6 user clip planes, base instance id) */
 771       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 772       PUSH_DATA (push, 512);
 773       PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
 774       PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
 775       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
 776       PUSH_DATA (push, (15 << 4) | 1);
 777       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
 778          unsigned j;
 779          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
 780          PUSH_DATA (push, 0);
 781          for (j = 0; j < 8; ++j)
 782             PUSH_DATA(push, j);
 783       } else {
 784          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
 785          PUSH_DATA (push, 0x54);
 786       }
 787    }
 788    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
 789    PUSH_DATA (push, 0);
 790
 791    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
 792    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 793    PUSH_DATA (push, 256);
 794    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 795    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 796    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
 797    PUSH_DATA (push, 0);
 798    PUSH_DATAf(push, 0.0f);
 799    PUSH_DATAf(push, 0.0f);
 800    PUSH_DATAf(push, 0.0f);
 801    PUSH_DATAf(push, 0.0f);
 802    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 803    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 804    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 805
 806    if (dev->drm_version >= 0x01000101) {
 807       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 808       if (ret) {
 809          NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
 810          goto fail;
 811       }
 812    } else {
 813       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
 814          value = (8 << 8) | 4;
 815       else
 816          value = (16 << 8) | 4;
 817    }
 818    screen->mp_count = value >> 8;
 819    screen->mp_count_compute = screen->mp_count;
 820
 821    nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
 822
 823    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 824    PUSH_DATAh(push, screen->text->offset);
 825    PUSH_DATA (push, screen->text->offset);
 826    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
 827    PUSH_DATAh(push, screen->tls->offset);
 828    PUSH_DATA (push, screen->tls->offset);
 829    PUSH_DATA (push, screen->tls->size >> 32);
 830    PUSH_DATA (push, screen->tls->size);
 831    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
 832    PUSH_DATA (push, 0);
 833    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
 834    PUSH_DATA (push, 0);
 835
 836    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
 837                         &screen->poly_cache);
 838    if (ret)
 839       goto fail;
 840
 841    BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
 842    PUSH_DATAh(push, screen->poly_cache->offset);
 843    PUSH_DATA (push, screen->poly_cache->offset);
 844    PUSH_DATA (push, 3);
 845
 846    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL,
 847                         &screen->txc);
 848    if (ret)
 849       goto fail;
 850
 851    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
 852    PUSH_DATAh(push, screen->txc->offset);
 853    PUSH_DATA (push, screen->txc->offset);
 854    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
 855
 856    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
 857    PUSH_DATAh(push, screen->txc->offset + 65536);
 858    PUSH_DATA (push, screen->txc->offset + 65536);
 859    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
 860
 861    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
 862    PUSH_DATA (push, 0);
 863    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
 864    PUSH_DATA (push, 0);
 865    PUSH_DATA (push, 0);
 866    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
 867    PUSH_DATA (push, 0x3f);
 868
 869    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
 870    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 871    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 872    for (i = 0; i < 8 * 2; ++i)
 873       PUSH_DATA(push, 0);
 874    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
 875    PUSH_DATA (push, 0);
 876    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
 877    PUSH_DATA (push, 0);
 878
 879    /* neither scissors, viewport nor stencil mask should affect clears */
 880    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
 881    PUSH_DATA (push, 0);
 882
 883    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
 884    PUSH_DATA (push, 1);
 885    BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2);
 886    PUSH_DATAf(push, 0.0f);
 887    PUSH_DATAf(push, 1.0f);
 888    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 889    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
 890
 891    /* We use scissors instead of exact view volume clipping,
 892     * so they're always enabled.
 893     */
 894    BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(0)), 3);
 895    PUSH_DATA (push, 1);
 896    PUSH_DATA (push, 8192 << 16);
 897    PUSH_DATA (push, 8192 << 16);
 898
 899 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
 900
 901    i = 0;
 902    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, nvc0_9097_per_instance_bf);
 903    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, nvc0_9097_blend_enables);
 904    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select);
 905    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, nvc0_9097_tep_select);
 906    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, nvc0_9097_gp_select);
 907    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front);
 908    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back);
 909
 910    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
 911    PUSH_DATA (push, 1);
 912    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
 913    PUSH_DATA (push, 1);
 914    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
 915    PUSH_DATA (push, 0x40);
 916    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
 917    PUSH_DATA (push, 0);
 918    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
 919    PUSH_DATA (push, 0x30);
 920    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
 921    PUSH_DATA (push, 3);
 922    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
 923    PUSH_DATA (push, 0x20);
 924    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
 925    PUSH_DATA (push, 0x00);
 926
 927    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
 928    PUSH_DATA (push, 0);
 929    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
 930    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
 931
 932    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
 933
 934    if (nvc0_screen_init_compute(screen))
 935       goto fail;
 936
 937    PUSH_KICK (push);
 938
 939    screen->tic.entries = CALLOC(4096, sizeof(void *));
 940    screen->tsc.entries = screen->tic.entries + 2048;
 941
 942    mm_config.nvc0.tile_mode = 0;
 943    mm_config.nvc0.memtype = 0xfe0;
 944    screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config);
 945
 946    if (!nvc0_blitter_create(screen))
 947       goto fail;
 948
 949    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 950
 951    return pscreen;
 952
 953 fail:
 954    nvc0_screen_destroy(pscreen);
 955    return NULL;
 956 }
 957
 958 int
 959 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
 960 {
 961    int i = screen->tic.next;
 962
 963    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 964       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 965
 966    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 967
 968    if (screen->tic.entries[i])
 969       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 970
 971    screen->tic.entries[i] = entry;
 972    return i;
 973 }
 974
 975 int
 976 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
 977 {
 978    int i = screen->tsc.next;
 979
 980    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 981       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 982
 983    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 984
 985    if (screen->tsc.entries[i])
 986       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 987
 988    screen->tsc.entries[i] = entry;
 989    return i;
 990 }