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nvc0: enable compute support on Fermi
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include "util/u_format.h"
26 #include "util/u_format_s3tc.h"
27 #include "pipe/p_screen.h"
28
29 #include "vl/vl_decoder.h"
30 #include "vl/vl_video_buffer.h"
31
32 #include "nouveau_vp3_video.h"
33
34 #include "nvc0/nvc0_context.h"
35 #include "nvc0/nvc0_screen.h"
36
37 #include "nvc0/mme/com9097.mme.h"
38
39 static boolean
40 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
41 enum pipe_format format,
42 enum pipe_texture_target target,
43 unsigned sample_count,
44 unsigned bindings)
45 {
46 if (sample_count > 8)
47 return false;
48 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
49 return false;
50
51 if (!util_format_is_supported(format, bindings))
52 return false;
53
54 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
55 if (util_format_get_blocksizebits(format) == 3 * 32)
56 return false;
57
58 /* transfers & shared are always supported */
59 bindings &= ~(PIPE_BIND_TRANSFER_READ |
60 PIPE_BIND_TRANSFER_WRITE |
61 PIPE_BIND_SHARED);
62
63 return (nvc0_format_table[format].usage & bindings) == bindings;
64 }
65
66 static int
67 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
68 {
69 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
70 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
71
72 switch (param) {
73 /* non-boolean caps */
74 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
75 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
76 return 15;
77 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
78 return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
79 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
80 return 2048;
81 case PIPE_CAP_MIN_TEXEL_OFFSET:
82 return -8;
83 case PIPE_CAP_MAX_TEXEL_OFFSET:
84 return 7;
85 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
86 return -32;
87 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
88 return 31;
89 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
90 return 128 * 1024 * 1024;
91 case PIPE_CAP_GLSL_FEATURE_LEVEL:
92 return 410;
93 case PIPE_CAP_MAX_RENDER_TARGETS:
94 return 8;
95 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
96 return 1;
97 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
98 return 4;
99 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
100 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
101 return 128;
102 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
103 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
104 return 1024;
105 case PIPE_CAP_MAX_VERTEX_STREAMS:
106 return 4;
107 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
108 return 2048;
109 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
110 return 256;
111 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
112 return 1; /* 256 for binding as RT, but that's not possible in GL */
113 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
114 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
115 case PIPE_CAP_MAX_VIEWPORTS:
116 return NVC0_MAX_VIEWPORTS;
117 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
118 return 4;
119 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
120 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
121 case PIPE_CAP_ENDIANNESS:
122 return PIPE_ENDIAN_LITTLE;
123 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
124 return 30;
125
126 /* supported caps */
127 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
128 case PIPE_CAP_TEXTURE_SWIZZLE:
129 case PIPE_CAP_TEXTURE_SHADOW_MAP:
130 case PIPE_CAP_NPOT_TEXTURES:
131 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
132 case PIPE_CAP_ANISOTROPIC_FILTER:
133 case PIPE_CAP_SEAMLESS_CUBE_MAP:
134 case PIPE_CAP_CUBE_MAP_ARRAY:
135 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
136 case PIPE_CAP_TEXTURE_MULTISAMPLE:
137 case PIPE_CAP_TWO_SIDED_STENCIL:
138 case PIPE_CAP_DEPTH_CLIP_DISABLE:
139 case PIPE_CAP_POINT_SPRITE:
140 case PIPE_CAP_TGSI_TEXCOORD:
141 case PIPE_CAP_SM3:
142 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
143 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
144 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
145 case PIPE_CAP_QUERY_TIMESTAMP:
146 case PIPE_CAP_QUERY_TIME_ELAPSED:
147 case PIPE_CAP_OCCLUSION_QUERY:
148 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
149 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
150 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
151 case PIPE_CAP_INDEP_BLEND_ENABLE:
152 case PIPE_CAP_INDEP_BLEND_FUNC:
153 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
154 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
155 case PIPE_CAP_PRIMITIVE_RESTART:
156 case PIPE_CAP_TGSI_INSTANCEID:
157 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
158 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
159 case PIPE_CAP_CONDITIONAL_RENDER:
160 case PIPE_CAP_TEXTURE_BARRIER:
161 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
162 case PIPE_CAP_START_INSTANCE:
163 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
164 case PIPE_CAP_DRAW_INDIRECT:
165 case PIPE_CAP_USER_CONSTANT_BUFFERS:
166 case PIPE_CAP_USER_INDEX_BUFFERS:
167 case PIPE_CAP_USER_VERTEX_BUFFERS:
168 case PIPE_CAP_TEXTURE_QUERY_LOD:
169 case PIPE_CAP_SAMPLE_SHADING:
170 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
171 case PIPE_CAP_TEXTURE_GATHER_SM5:
172 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
173 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
174 case PIPE_CAP_SAMPLER_VIEW_TARGET:
175 case PIPE_CAP_CLIP_HALFZ:
176 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
177 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
178 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
179 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
180 case PIPE_CAP_DEPTH_BOUNDS_TEST:
181 case PIPE_CAP_TGSI_TXQS:
182 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
183 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
184 case PIPE_CAP_SHAREABLE_SHADERS:
185 return 1;
186 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
187 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
188 case PIPE_CAP_COMPUTE:
189 return (class_3d <= NVE4_3D_CLASS) ? 1 : 0;
190 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
191 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
192
193 /* unsupported caps */
194 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
195 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
196 case PIPE_CAP_SHADER_STENCIL_EXPORT:
197 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
198 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
199 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
200 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
201 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
202 case PIPE_CAP_FAKE_SW_MSAA:
203 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
204 case PIPE_CAP_VERTEXID_NOBASE:
205 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
206 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
207 return 0;
208
209 case PIPE_CAP_VENDOR_ID:
210 return 0x10de;
211 case PIPE_CAP_DEVICE_ID: {
212 uint64_t device_id;
213 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
214 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
215 return -1;
216 }
217 return device_id;
218 }
219 case PIPE_CAP_ACCELERATED:
220 return 1;
221 case PIPE_CAP_VIDEO_MEMORY:
222 return dev->vram_size >> 20;
223 case PIPE_CAP_UMA:
224 return 0;
225 }
226
227 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
228 return 0;
229 }
230
231 static int
232 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
233 enum pipe_shader_cap param)
234 {
235 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
236
237 switch (shader) {
238 case PIPE_SHADER_VERTEX:
239 case PIPE_SHADER_GEOMETRY:
240 case PIPE_SHADER_FRAGMENT:
241 break;
242 case PIPE_SHADER_TESS_CTRL:
243 case PIPE_SHADER_TESS_EVAL:
244 if (class_3d >= GM107_3D_CLASS)
245 return 0;
246 break;
247 case PIPE_SHADER_COMPUTE:
248 if (class_3d > NVE4_3D_CLASS)
249 return 0;
250 break;
251 default:
252 return 0;
253 }
254
255 switch (param) {
256 case PIPE_SHADER_CAP_PREFERRED_IR:
257 return PIPE_SHADER_IR_TGSI;
258 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
259 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
260 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
261 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
262 return 16384;
263 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
264 return 16;
265 case PIPE_SHADER_CAP_MAX_INPUTS:
266 if (shader == PIPE_SHADER_VERTEX)
267 return 32;
268 /* NOTE: These only count our slots for GENERIC varyings.
269 * The address space may be larger, but the actual hard limit seems to be
270 * less than what the address space layout permits, so don't add TEXCOORD,
271 * COLOR, etc. here.
272 */
273 if (shader == PIPE_SHADER_FRAGMENT)
274 return 0x1f0 / 16;
275 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
276 * and excludes 0x60 per-patch inputs.
277 */
278 return 0x200 / 16;
279 case PIPE_SHADER_CAP_MAX_OUTPUTS:
280 return 32;
281 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
282 return 65536;
283 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
284 if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
285 return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
286 return NVC0_MAX_PIPE_CONSTBUFS;
287 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
288 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
289 return shader != PIPE_SHADER_FRAGMENT;
290 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
291 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
292 return 1;
293 case PIPE_SHADER_CAP_MAX_PREDS:
294 return 0;
295 case PIPE_SHADER_CAP_MAX_TEMPS:
296 return NVC0_CAP_MAX_PROGRAM_TEMPS;
297 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
298 return 1;
299 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
300 return 0;
301 case PIPE_SHADER_CAP_SUBROUTINES:
302 return 1;
303 case PIPE_SHADER_CAP_INTEGERS:
304 return 1;
305 case PIPE_SHADER_CAP_DOUBLES:
306 return 1;
307 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
308 return 1;
309 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
310 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
311 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
312 return 0;
313 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
314 return 16; /* would be 32 in linked (OpenGL-style) mode */
315 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
316 return 16; /* XXX not sure if more are really safe */
317 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
318 return 32;
319 default:
320 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
321 return 0;
322 }
323 }
324
325 static float
326 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
327 {
328 switch (param) {
329 case PIPE_CAPF_MAX_LINE_WIDTH:
330 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
331 return 10.0f;
332 case PIPE_CAPF_MAX_POINT_WIDTH:
333 return 63.0f;
334 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
335 return 63.375f;
336 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
337 return 16.0f;
338 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
339 return 15.0f;
340 case PIPE_CAPF_GUARD_BAND_LEFT:
341 case PIPE_CAPF_GUARD_BAND_TOP:
342 return 0.0f;
343 case PIPE_CAPF_GUARD_BAND_RIGHT:
344 case PIPE_CAPF_GUARD_BAND_BOTTOM:
345 return 0.0f; /* that or infinity */
346 }
347
348 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
349 return 0.0f;
350 }
351
352 static int
353 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
354 enum pipe_compute_cap param, void *data)
355 {
356 struct nvc0_screen *screen = nvc0_screen(pscreen);
357 const uint16_t obj_class = screen->compute->oclass;
358
359 #define RET(x) do { \
360 if (data) \
361 memcpy(data, x, sizeof(x)); \
362 return sizeof(x); \
363 } while (0)
364
365 switch (param) {
366 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
367 RET((uint64_t []) { 3 });
368 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
369 if (obj_class >= NVE4_COMPUTE_CLASS) {
370 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
371 } else {
372 RET(((uint64_t []) { 65535, 65535, 65535 }));
373 }
374 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
375 RET(((uint64_t []) { 1024, 1024, 64 }));
376 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
377 RET((uint64_t []) { 1024 });
378 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
379 RET((uint64_t []) { 1ULL << 40 });
380 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
381 RET((uint64_t []) { 48 << 10 });
382 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
383 RET((uint64_t []) { 512 << 10 });
384 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
385 RET((uint64_t []) { 4096 });
386 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
387 RET((uint32_t []) { 32 });
388 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
389 RET((uint64_t []) { 1ULL << 40 });
390 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
391 RET((uint32_t []) { 0 });
392 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
393 RET((uint32_t []) { screen->mp_count_compute });
394 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
395 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
396 default:
397 return 0;
398 }
399
400 #undef RET
401 }
402
403 static void
404 nvc0_screen_destroy(struct pipe_screen *pscreen)
405 {
406 struct nvc0_screen *screen = nvc0_screen(pscreen);
407
408 if (!nouveau_drm_screen_unref(&screen->base))
409 return;
410
411 if (screen->base.fence.current) {
412 struct nouveau_fence *current = NULL;
413
414 /* nouveau_fence_wait will create a new current fence, so wait on the
415 * _current_ one, and remove both.
416 */
417 nouveau_fence_ref(screen->base.fence.current, &current);
418 nouveau_fence_wait(current, NULL);
419 nouveau_fence_ref(NULL, &current);
420 nouveau_fence_ref(NULL, &screen->base.fence.current);
421 }
422 if (screen->base.pushbuf)
423 screen->base.pushbuf->user_priv = NULL;
424
425 if (screen->blitter)
426 nvc0_blitter_destroy(screen);
427 if (screen->pm.prog) {
428 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
429 nvc0_program_destroy(NULL, screen->pm.prog);
430 }
431
432 nouveau_bo_ref(NULL, &screen->text);
433 nouveau_bo_ref(NULL, &screen->uniform_bo);
434 nouveau_bo_ref(NULL, &screen->tls);
435 nouveau_bo_ref(NULL, &screen->txc);
436 nouveau_bo_ref(NULL, &screen->fence.bo);
437 nouveau_bo_ref(NULL, &screen->poly_cache);
438 nouveau_bo_ref(NULL, &screen->parm);
439
440 nouveau_heap_destroy(&screen->lib_code);
441 nouveau_heap_destroy(&screen->text_heap);
442
443 FREE(screen->tic.entries);
444
445 nouveau_object_del(&screen->eng3d);
446 nouveau_object_del(&screen->eng2d);
447 nouveau_object_del(&screen->m2mf);
448 nouveau_object_del(&screen->compute);
449 nouveau_object_del(&screen->nvsw);
450
451 nouveau_screen_fini(&screen->base);
452
453 FREE(screen);
454 }
455
456 static int
457 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
458 unsigned size, const uint32_t *data)
459 {
460 struct nouveau_pushbuf *push = screen->base.pushbuf;
461
462 size /= 4;
463
464 assert((pos + size) <= 0x800);
465
466 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
467 PUSH_DATA (push, (m - 0x3800) / 8);
468 PUSH_DATA (push, pos);
469 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
470 PUSH_DATA (push, pos);
471 PUSH_DATAp(push, data, size);
472
473 return pos + size;
474 }
475
476 static void
477 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
478 {
479 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
480 PUSH_DATA (push, 0xff);
481 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
482 PUSH_DATA (push, 0xff);
483 PUSH_DATA (push, 0xff);
484 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
485 PUSH_DATA (push, 0xff);
486 PUSH_DATA (push, 0xff);
487 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
488 PUSH_DATA (push, 0x3f);
489
490 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
491 PUSH_DATA (push, (3 << 16) | 3);
492 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
493 PUSH_DATA (push, (2 << 16) | 2);
494
495 if (obj_class < GM107_3D_CLASS) {
496 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
497 PUSH_DATA (push, 0);
498 }
499 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
500 PUSH_DATA (push, 0x10);
501 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
502 PUSH_DATA (push, 0x10);
503 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
504 PUSH_DATA (push, 0x10);
505 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
506 PUSH_DATA (push, 0x10);
507 PUSH_DATA (push, 0x10);
508 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
509 PUSH_DATA (push, 0x10);
510 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
511 PUSH_DATA (push, 0xe);
512
513 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
514 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
515 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
516 PUSH_DATA (push, 0);
517 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
518 PUSH_DATA (push, 3);
519
520 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
521 PUSH_DATA (push, 0x3fffff);
522 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
523 PUSH_DATA (push, 1);
524 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
525 PUSH_DATA (push, 1);
526
527 if (obj_class < GM107_3D_CLASS) {
528 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
529 PUSH_DATA (push, 3);
530
531 if (obj_class >= NVE4_3D_CLASS) {
532 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
533 PUSH_DATA (push, 1);
534 }
535 }
536
537 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
538 * are supposed to do */
539 }
540
541 static void
542 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
543 {
544 struct nvc0_screen *screen = nvc0_screen(pscreen);
545 struct nouveau_pushbuf *push = screen->base.pushbuf;
546
547 /* we need to do it after possible flush in MARK_RING */
548 *sequence = ++screen->base.fence.sequence;
549
550 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
551 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
552 PUSH_DATAh(push, screen->fence.bo->offset);
553 PUSH_DATA (push, screen->fence.bo->offset);
554 PUSH_DATA (push, *sequence);
555 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
556 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
557 }
558
559 static u32
560 nvc0_screen_fence_update(struct pipe_screen *pscreen)
561 {
562 struct nvc0_screen *screen = nvc0_screen(pscreen);
563 return screen->fence.map[0];
564 }
565
566 static int
567 nvc0_screen_init_compute(struct nvc0_screen *screen)
568 {
569 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
570
571 switch (screen->base.device->chipset & ~0xf) {
572 case 0xc0:
573 case 0xd0:
574 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
575 case 0xe0:
576 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
577 case 0xf0:
578 case 0x100:
579 case 0x110:
580 return 0;
581 default:
582 return -1;
583 }
584 }
585
586 bool
587 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
588 uint32_t lpos, uint32_t lneg, uint32_t cstack)
589 {
590 struct nouveau_bo *bo = NULL;
591 int ret;
592 uint64_t size = (lpos + lneg) * 32 + cstack;
593
594 if (size >= (1 << 20)) {
595 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
596 return false;
597 }
598
599 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
600 size = align(size, 0x8000);
601 size *= screen->mp_count;
602
603 size = align(size, 1 << 17);
604
605 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
606 NULL, &bo);
607 if (ret) {
608 NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
609 return false;
610 }
611 nouveau_bo_ref(NULL, &screen->tls);
612 screen->tls = bo;
613 return true;
614 }
615
616 #define FAIL_SCREEN_INIT(str, err) \
617 do { \
618 NOUVEAU_ERR(str, err); \
619 nvc0_screen_destroy(pscreen); \
620 return NULL; \
621 } while(0)
622
623 struct pipe_screen *
624 nvc0_screen_create(struct nouveau_device *dev)
625 {
626 struct nvc0_screen *screen;
627 struct pipe_screen *pscreen;
628 struct nouveau_object *chan;
629 struct nouveau_pushbuf *push;
630 uint64_t value;
631 uint32_t obj_class;
632 uint32_t flags;
633 int ret;
634 unsigned i;
635
636 switch (dev->chipset & ~0xf) {
637 case 0xc0:
638 case 0xd0:
639 case 0xe0:
640 case 0xf0:
641 case 0x100:
642 case 0x110:
643 break;
644 default:
645 return NULL;
646 }
647
648 screen = CALLOC_STRUCT(nvc0_screen);
649 if (!screen)
650 return NULL;
651 pscreen = &screen->base.base;
652
653 ret = nouveau_screen_init(&screen->base, dev);
654 if (ret) {
655 nvc0_screen_destroy(pscreen);
656 return NULL;
657 }
658 chan = screen->base.channel;
659 push = screen->base.pushbuf;
660 push->user_priv = screen;
661 push->rsvd_kick = 5;
662
663 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
664 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
665 PIPE_BIND_COMMAND_ARGS_BUFFER;
666 screen->base.sysmem_bindings |=
667 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
668
669 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
670 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
671 screen->base.vidmem_bindings = 0;
672 }
673
674 pscreen->destroy = nvc0_screen_destroy;
675 pscreen->context_create = nvc0_create;
676 pscreen->is_format_supported = nvc0_screen_is_format_supported;
677 pscreen->get_param = nvc0_screen_get_param;
678 pscreen->get_shader_param = nvc0_screen_get_shader_param;
679 pscreen->get_paramf = nvc0_screen_get_paramf;
680 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
681 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
682
683 nvc0_screen_init_resource_functions(pscreen);
684
685 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
686 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
687
688 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
689 if (dev->drm_version >= 0x01000202)
690 flags |= NOUVEAU_BO_COHERENT;
691
692 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
693 if (ret)
694 goto fail;
695 nouveau_bo_map(screen->fence.bo, 0, NULL);
696 screen->fence.map = screen->fence.bo->map;
697 screen->base.fence.emit = nvc0_screen_fence_emit;
698 screen->base.fence.update = nvc0_screen_fence_update;
699
700
701 ret = nouveau_object_new(chan,
702 (dev->chipset < 0xe0) ? 0x1f906e : 0x906e, 0x906e,
703 NULL, 0, &screen->nvsw);
704 if (ret)
705 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
706
707
708 switch (dev->chipset & ~0xf) {
709 case 0x110:
710 case 0x100:
711 case 0xf0:
712 obj_class = NVF0_P2MF_CLASS;
713 break;
714 case 0xe0:
715 obj_class = NVE4_P2MF_CLASS;
716 break;
717 default:
718 obj_class = NVC0_M2MF_CLASS;
719 break;
720 }
721 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
722 &screen->m2mf);
723 if (ret)
724 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
725
726 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
727 PUSH_DATA (push, screen->m2mf->oclass);
728 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
729 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
730 PUSH_DATA (push, 0xa0b5);
731 }
732
733 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
734 &screen->eng2d);
735 if (ret)
736 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
737
738 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
739 PUSH_DATA (push, screen->eng2d->oclass);
740 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
741 PUSH_DATA (push, 0);
742 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
743 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
744 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
745 PUSH_DATA (push, 0);
746 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
747 PUSH_DATA (push, 0);
748 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
749 PUSH_DATA (push, 0x3f);
750 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
751 PUSH_DATA (push, 1);
752 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
753 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
754
755 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
756 PUSH_DATAh(push, screen->fence.bo->offset + 16);
757 PUSH_DATA (push, screen->fence.bo->offset + 16);
758
759 switch (dev->chipset & ~0xf) {
760 case 0x110:
761 obj_class = GM107_3D_CLASS;
762 break;
763 case 0x100:
764 case 0xf0:
765 obj_class = NVF0_3D_CLASS;
766 break;
767 case 0xe0:
768 switch (dev->chipset) {
769 case 0xea:
770 obj_class = NVEA_3D_CLASS;
771 break;
772 default:
773 obj_class = NVE4_3D_CLASS;
774 break;
775 }
776 break;
777 case 0xd0:
778 obj_class = NVC8_3D_CLASS;
779 break;
780 case 0xc0:
781 default:
782 switch (dev->chipset) {
783 case 0xc8:
784 obj_class = NVC8_3D_CLASS;
785 break;
786 case 0xc1:
787 obj_class = NVC1_3D_CLASS;
788 break;
789 default:
790 obj_class = NVC0_3D_CLASS;
791 break;
792 }
793 break;
794 }
795 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
796 &screen->eng3d);
797 if (ret)
798 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
799 screen->base.class_3d = obj_class;
800
801 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
802 PUSH_DATA (push, screen->eng3d->oclass);
803
804 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
805 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
806
807 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
808 /* kill shaders after about 1 second (at 100 MHz) */
809 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
810 PUSH_DATA (push, 0x17);
811 }
812
813 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE), dev->drm_version >= 0x01000101);
814 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
815 for (i = 0; i < 8; ++i)
816 PUSH_DATA(push, dev->drm_version >= 0x01000101);
817
818 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
819 PUSH_DATA (push, 1);
820
821 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
822 PUSH_DATA (push, 0);
823 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
824 PUSH_DATA (push, 0);
825 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
826 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
827 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
828 PUSH_DATA (push, 0);
829 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
830 PUSH_DATA (push, 1);
831 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
832 PUSH_DATA (push, 1);
833 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
834 PUSH_DATA (push, 1);
835 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
836 PUSH_DATA (push, 0);
837 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
838 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
839 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
840 BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
841 PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
842 } else {
843 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
844 PUSH_DATA (push, 15);
845 }
846 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
847 PUSH_DATA (push, 8); /* 128 */
848 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
849 PUSH_DATA (push, 1);
850 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
851 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
852 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
853 }
854
855 nvc0_magic_3d_init(push, screen->eng3d->oclass);
856
857 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
858 &screen->text);
859 if (ret)
860 goto fail;
861
862 /* XXX: getting a page fault at the end of the code buffer every few
863 * launches, don't use the last 256 bytes to work around them - prefetch ?
864 */
865 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
866
867 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 6 << 16, NULL,
868 &screen->uniform_bo);
869 if (ret)
870 goto fail;
871
872 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
873
874 for (i = 0; i < 5; ++i) {
875 /* TIC and TSC entries for each unit (nve4+ only) */
876 /* auxiliary constants (6 user clip planes, base instance id) */
877 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
878 PUSH_DATA (push, 512);
879 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
880 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
881 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
882 PUSH_DATA (push, (15 << 4) | 1);
883 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
884 unsigned j;
885 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
886 PUSH_DATA (push, 0);
887 for (j = 0; j < 8; ++j)
888 PUSH_DATA(push, j);
889 } else {
890 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
891 PUSH_DATA (push, 0x54);
892 }
893 }
894 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
895 PUSH_DATA (push, 0);
896
897 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
898 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
899 PUSH_DATA (push, 256);
900 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
901 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
902 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
903 PUSH_DATA (push, 0);
904 PUSH_DATAf(push, 0.0f);
905 PUSH_DATAf(push, 0.0f);
906 PUSH_DATAf(push, 0.0f);
907 PUSH_DATAf(push, 0.0f);
908 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
909 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
910 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
911
912 if (dev->drm_version >= 0x01000101) {
913 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
914 if (ret) {
915 NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
916 goto fail;
917 }
918 } else {
919 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
920 value = (8 << 8) | 4;
921 else
922 value = (16 << 8) | 4;
923 }
924 screen->gpc_count = value & 0x000000ff;
925 screen->mp_count = value >> 8;
926 screen->mp_count_compute = screen->mp_count;
927
928 nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
929
930 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
931 PUSH_DATAh(push, screen->text->offset);
932 PUSH_DATA (push, screen->text->offset);
933 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
934 PUSH_DATAh(push, screen->tls->offset);
935 PUSH_DATA (push, screen->tls->offset);
936 PUSH_DATA (push, screen->tls->size >> 32);
937 PUSH_DATA (push, screen->tls->size);
938 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
939 PUSH_DATA (push, 0);
940 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
941 PUSH_DATA (push, 0);
942
943 if (screen->eng3d->oclass < GM107_3D_CLASS) {
944 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
945 &screen->poly_cache);
946 if (ret)
947 goto fail;
948
949 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
950 PUSH_DATAh(push, screen->poly_cache->offset);
951 PUSH_DATA (push, screen->poly_cache->offset);
952 PUSH_DATA (push, 3);
953 }
954
955 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
956 &screen->txc);
957 if (ret)
958 goto fail;
959
960 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
961 PUSH_DATAh(push, screen->txc->offset);
962 PUSH_DATA (push, screen->txc->offset);
963 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
964
965 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
966 PUSH_DATAh(push, screen->txc->offset + 65536);
967 PUSH_DATA (push, screen->txc->offset + 65536);
968 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
969
970 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
971 PUSH_DATA (push, 0);
972 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
973 PUSH_DATA (push, 0);
974 PUSH_DATA (push, 0);
975 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
976 PUSH_DATA (push, 0x3f);
977
978 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
979 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
980 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
981 for (i = 0; i < 8 * 2; ++i)
982 PUSH_DATA(push, 0);
983 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
984 PUSH_DATA (push, 0);
985 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
986 PUSH_DATA (push, 0);
987
988 /* neither scissors, viewport nor stencil mask should affect clears */
989 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
990 PUSH_DATA (push, 0);
991
992 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
993 PUSH_DATA (push, 1);
994 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
995 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
996 PUSH_DATAf(push, 0.0f);
997 PUSH_DATAf(push, 1.0f);
998 }
999 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1000 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1001
1002 /* We use scissors instead of exact view volume clipping,
1003 * so they're always enabled.
1004 */
1005 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1006 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1007 PUSH_DATA (push, 1);
1008 PUSH_DATA (push, 8192 << 16);
1009 PUSH_DATA (push, 8192 << 16);
1010 }
1011
1012 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1013
1014 i = 0;
1015 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1016 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1017 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1018 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1019 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1020 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1021 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1022 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1023 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1024
1025 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1026 PUSH_DATA (push, 1);
1027 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1028 PUSH_DATA (push, 1);
1029 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1030 PUSH_DATA (push, 0x40);
1031 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1032 PUSH_DATA (push, 0);
1033 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1034 PUSH_DATA (push, 0x30);
1035 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1036 PUSH_DATA (push, 3);
1037 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1038 PUSH_DATA (push, 0x20);
1039 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1040 PUSH_DATA (push, 0x00);
1041 screen->save_state.patch_vertices = 3;
1042
1043 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1044 PUSH_DATA (push, 0);
1045 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1046 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1047
1048 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1049
1050 if (nvc0_screen_init_compute(screen))
1051 goto fail;
1052
1053 PUSH_KICK (push);
1054
1055 screen->tic.entries = CALLOC(4096, sizeof(void *));
1056 screen->tsc.entries = screen->tic.entries + 2048;
1057
1058 if (!nvc0_blitter_create(screen))
1059 goto fail;
1060
1061 nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1062
1063 return pscreen;
1064
1065 fail:
1066 nvc0_screen_destroy(pscreen);
1067 return NULL;
1068 }
1069
1070 int
1071 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1072 {
1073 int i = screen->tic.next;
1074
1075 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1076 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1077
1078 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1079
1080 if (screen->tic.entries[i])
1081 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1082
1083 screen->tic.entries[i] = entry;
1084 return i;
1085 }
1086
1087 int
1088 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1089 {
1090 int i = screen->tsc.next;
1091
1092 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1093 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1094
1095 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1096
1097 if (screen->tsc.entries[i])
1098 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1099
1100 screen->tsc.entries[i] = entry;
1101 return i;
1102 }