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gallium: add initial support for conservative rasterization
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "nouveau_vp3_video.h"
31
32 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nvc0_screen.h"
34
35 #include "nvc0/mme/com9097.mme.h"
36 #include "nvc0/mme/com90c0.mme.h"
37
38 #include "nv50/g80_texture.xml.h"
39
40 static boolean
41 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
42 enum pipe_format format,
43 enum pipe_texture_target target,
44 unsigned sample_count,
45 unsigned bindings)
46 {
47 const struct util_format_description *desc = util_format_description(format);
48
49 if (sample_count > 8)
50 return false;
51 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
52 return false;
53
54 /* Short-circuit the rest of the logic -- this is used by the state tracker
55 * to determine valid MS levels in a no-attachments scenario.
56 */
57 if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
58 return true;
59
60 if (!util_format_is_supported(format, bindings))
61 return false;
62
63 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
64 if (util_format_get_blocksizebits(format) == 3 * 32)
65 return false;
66
67 if (bindings & PIPE_BIND_LINEAR)
68 if (util_format_is_depth_or_stencil(format) ||
69 (target != PIPE_TEXTURE_1D &&
70 target != PIPE_TEXTURE_2D &&
71 target != PIPE_TEXTURE_RECT) ||
72 sample_count > 1)
73 return false;
74
75 /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
76 */
77 if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
78 desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
79 /* The claim is that this should work on GM107 but it doesn't. Need to
80 * test further and figure out if it's a nouveau issue or a HW one.
81 nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
82 */
83 nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
84 return false;
85
86 /* shared is always supported */
87 bindings &= ~(PIPE_BIND_LINEAR |
88 PIPE_BIND_SHARED);
89
90 if (bindings & PIPE_BIND_SHADER_IMAGE) {
91 if (sample_count > 0 &&
92 nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
93 /* MS images are currently unsupported on Maxwell because they have to
94 * be handled explicitly. */
95 return false;
96 }
97
98 if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
99 nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
100 /* This should work on Fermi, but for currently unknown reasons it
101 * does not and results in breaking reads from pbos. */
102 return false;
103 }
104 }
105
106 return (( nvc0_format_table[format].usage |
107 nvc0_vertex_format[format].usage) & bindings) == bindings;
108 }
109
110 static int
111 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
112 {
113 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
114 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
115
116 switch (param) {
117 /* non-boolean caps */
118 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
119 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
120 return 15;
121 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
122 return 12;
123 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
124 return 2048;
125 case PIPE_CAP_MIN_TEXEL_OFFSET:
126 return -8;
127 case PIPE_CAP_MAX_TEXEL_OFFSET:
128 return 7;
129 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
130 return -32;
131 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
132 return 31;
133 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
134 return 128 * 1024 * 1024;
135 case PIPE_CAP_GLSL_FEATURE_LEVEL:
136 return 430;
137 case PIPE_CAP_MAX_RENDER_TARGETS:
138 return 8;
139 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
140 return 1;
141 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
142 return 4;
143 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
144 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
145 return 128;
146 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
147 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
148 return 1024;
149 case PIPE_CAP_MAX_VERTEX_STREAMS:
150 return 4;
151 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
152 return 2048;
153 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
154 return 256;
155 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
156 if (class_3d < GM107_3D_CLASS)
157 return 256; /* IMAGE bindings require alignment to 256 */
158 return 16;
159 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
160 return 16;
161 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
162 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
163 case PIPE_CAP_MAX_VIEWPORTS:
164 return NVC0_MAX_VIEWPORTS;
165 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
166 return 4;
167 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
168 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
169 case PIPE_CAP_ENDIANNESS:
170 return PIPE_ENDIAN_LITTLE;
171 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
172 return 30;
173 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
174 return NVC0_MAX_WINDOW_RECTANGLES;
175
176 /* supported caps */
177 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
178 case PIPE_CAP_TEXTURE_SWIZZLE:
179 case PIPE_CAP_NPOT_TEXTURES:
180 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
181 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
182 case PIPE_CAP_ANISOTROPIC_FILTER:
183 case PIPE_CAP_SEAMLESS_CUBE_MAP:
184 case PIPE_CAP_CUBE_MAP_ARRAY:
185 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
186 case PIPE_CAP_TEXTURE_MULTISAMPLE:
187 case PIPE_CAP_DEPTH_CLIP_DISABLE:
188 case PIPE_CAP_POINT_SPRITE:
189 case PIPE_CAP_TGSI_TEXCOORD:
190 case PIPE_CAP_SM3:
191 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
192 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
193 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
194 case PIPE_CAP_QUERY_TIMESTAMP:
195 case PIPE_CAP_QUERY_TIME_ELAPSED:
196 case PIPE_CAP_OCCLUSION_QUERY:
197 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
198 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
199 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
200 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
201 case PIPE_CAP_INDEP_BLEND_ENABLE:
202 case PIPE_CAP_INDEP_BLEND_FUNC:
203 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
204 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
205 case PIPE_CAP_PRIMITIVE_RESTART:
206 case PIPE_CAP_TGSI_INSTANCEID:
207 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
208 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
209 case PIPE_CAP_CONDITIONAL_RENDER:
210 case PIPE_CAP_TEXTURE_BARRIER:
211 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
212 case PIPE_CAP_START_INSTANCE:
213 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
214 case PIPE_CAP_DRAW_INDIRECT:
215 case PIPE_CAP_USER_VERTEX_BUFFERS:
216 case PIPE_CAP_TEXTURE_QUERY_LOD:
217 case PIPE_CAP_SAMPLE_SHADING:
218 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
219 case PIPE_CAP_TEXTURE_GATHER_SM5:
220 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
221 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
222 case PIPE_CAP_SAMPLER_VIEW_TARGET:
223 case PIPE_CAP_CLIP_HALFZ:
224 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
225 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
226 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
227 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
228 case PIPE_CAP_DEPTH_BOUNDS_TEST:
229 case PIPE_CAP_TGSI_TXQS:
230 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
231 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
232 case PIPE_CAP_SHAREABLE_SHADERS:
233 case PIPE_CAP_CLEAR_TEXTURE:
234 case PIPE_CAP_DRAW_PARAMETERS:
235 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
236 case PIPE_CAP_MULTI_DRAW_INDIRECT:
237 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
238 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
239 case PIPE_CAP_QUERY_BUFFER_OBJECT:
240 case PIPE_CAP_INVALIDATE_BUFFER:
241 case PIPE_CAP_STRING_MARKER:
242 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
243 case PIPE_CAP_CULL_DISTANCE:
244 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
245 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
246 case PIPE_CAP_TGSI_VOTE:
247 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
248 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
249 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
250 case PIPE_CAP_DOUBLES:
251 case PIPE_CAP_INT64:
252 case PIPE_CAP_TGSI_TEX_TXF_LZ:
253 case PIPE_CAP_TGSI_CLOCK:
254 case PIPE_CAP_COMPUTE:
255 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
256 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
257 case PIPE_CAP_QUERY_SO_OVERFLOW:
258 return 1;
259 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
260 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
261 case PIPE_CAP_TGSI_FS_FBFETCH:
262 return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
263 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
264 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
265 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
266 case PIPE_CAP_POST_DEPTH_COVERAGE:
267 return class_3d >= GM200_3D_CLASS;
268 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
269 case PIPE_CAP_TGSI_BALLOT:
270 case PIPE_CAP_BINDLESS_TEXTURE:
271 return class_3d >= NVE4_3D_CLASS;
272
273 /* unsupported caps */
274 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
275 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
276 case PIPE_CAP_SHADER_STENCIL_EXPORT:
277 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
278 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
279 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
280 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
281 case PIPE_CAP_FAKE_SW_MSAA:
282 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
283 case PIPE_CAP_VERTEXID_NOBASE:
284 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
285 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
286 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
287 case PIPE_CAP_GENERATE_MIPMAP:
288 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
289 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
290 case PIPE_CAP_QUERY_MEMORY_INFO:
291 case PIPE_CAP_PCI_GROUP:
292 case PIPE_CAP_PCI_BUS:
293 case PIPE_CAP_PCI_DEVICE:
294 case PIPE_CAP_PCI_FUNCTION:
295 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
296 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
297 case PIPE_CAP_NATIVE_FENCE_FD:
298 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
299 case PIPE_CAP_INT64_DIVMOD:
300 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
301 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
302 case PIPE_CAP_MEMOBJ:
303 case PIPE_CAP_LOAD_CONSTBUF:
304 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
305 case PIPE_CAP_TILE_RASTER_ORDER:
306 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
307 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
308 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
309 case PIPE_CAP_FENCE_SIGNAL:
310 case PIPE_CAP_CONSTBUF0_FLAGS:
311 case PIPE_CAP_PACKED_UNIFORMS:
312 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
313 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
314 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
315 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
316 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
317 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
318 return 0;
319
320 case PIPE_CAP_VENDOR_ID:
321 return 0x10de;
322 case PIPE_CAP_DEVICE_ID: {
323 uint64_t device_id;
324 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
325 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
326 return -1;
327 }
328 return device_id;
329 }
330 case PIPE_CAP_ACCELERATED:
331 return 1;
332 case PIPE_CAP_VIDEO_MEMORY:
333 return dev->vram_size >> 20;
334 case PIPE_CAP_UMA:
335 return 0;
336 }
337
338 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
339 return 0;
340 }
341
342 static int
343 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
344 enum pipe_shader_type shader,
345 enum pipe_shader_cap param)
346 {
347 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
348
349 switch (shader) {
350 case PIPE_SHADER_VERTEX:
351 case PIPE_SHADER_GEOMETRY:
352 case PIPE_SHADER_FRAGMENT:
353 case PIPE_SHADER_COMPUTE:
354 case PIPE_SHADER_TESS_CTRL:
355 case PIPE_SHADER_TESS_EVAL:
356 break;
357 default:
358 return 0;
359 }
360
361 switch (param) {
362 case PIPE_SHADER_CAP_PREFERRED_IR:
363 return PIPE_SHADER_IR_TGSI;
364 case PIPE_SHADER_CAP_SUPPORTED_IRS:
365 return 1 << PIPE_SHADER_IR_TGSI;
366 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
367 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
368 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
369 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
370 return 16384;
371 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
372 return 16;
373 case PIPE_SHADER_CAP_MAX_INPUTS:
374 if (shader == PIPE_SHADER_VERTEX)
375 return 32;
376 /* NOTE: These only count our slots for GENERIC varyings.
377 * The address space may be larger, but the actual hard limit seems to be
378 * less than what the address space layout permits, so don't add TEXCOORD,
379 * COLOR, etc. here.
380 */
381 if (shader == PIPE_SHADER_FRAGMENT)
382 return 0x1f0 / 16;
383 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
384 * and excludes 0x60 per-patch inputs.
385 */
386 return 0x200 / 16;
387 case PIPE_SHADER_CAP_MAX_OUTPUTS:
388 return 32;
389 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
390 return 65536;
391 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
392 return NVC0_MAX_PIPE_CONSTBUFS;
393 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
394 return shader != PIPE_SHADER_FRAGMENT;
395 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
396 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
397 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
398 return 1;
399 case PIPE_SHADER_CAP_MAX_TEMPS:
400 return NVC0_CAP_MAX_PROGRAM_TEMPS;
401 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
402 return 1;
403 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
404 return 1;
405 case PIPE_SHADER_CAP_SUBROUTINES:
406 return 1;
407 case PIPE_SHADER_CAP_INTEGERS:
408 return 1;
409 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
410 return 1;
411 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
412 return 1;
413 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
414 return 1;
415 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
416 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
417 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
418 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
419 case PIPE_SHADER_CAP_INT64_ATOMICS:
420 case PIPE_SHADER_CAP_FP16:
421 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
422 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
423 return 0;
424 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
425 return NVC0_MAX_BUFFERS;
426 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
427 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
428 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
429 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
430 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
431 return 32;
432 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
433 if (class_3d >= NVE4_3D_CLASS)
434 return NVC0_MAX_IMAGES;
435 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
436 return NVC0_MAX_IMAGES;
437 return 0;
438 default:
439 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
440 return 0;
441 }
442 }
443
444 static float
445 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
446 {
447 switch (param) {
448 case PIPE_CAPF_MAX_LINE_WIDTH:
449 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
450 return 10.0f;
451 case PIPE_CAPF_MAX_POINT_WIDTH:
452 return 63.0f;
453 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
454 return 63.375f;
455 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
456 return 16.0f;
457 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
458 return 15.0f;
459 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
460 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
461 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
462 return 0.0f;
463 }
464
465 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
466 return 0.0f;
467 }
468
469 static int
470 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
471 enum pipe_shader_ir ir_type,
472 enum pipe_compute_cap param, void *data)
473 {
474 struct nvc0_screen *screen = nvc0_screen(pscreen);
475 const uint16_t obj_class = screen->compute->oclass;
476
477 #define RET(x) do { \
478 if (data) \
479 memcpy(data, x, sizeof(x)); \
480 return sizeof(x); \
481 } while (0)
482
483 switch (param) {
484 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
485 RET((uint64_t []) { 3 });
486 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
487 if (obj_class >= NVE4_COMPUTE_CLASS) {
488 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
489 } else {
490 RET(((uint64_t []) { 65535, 65535, 65535 }));
491 }
492 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
493 RET(((uint64_t []) { 1024, 1024, 64 }));
494 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
495 RET((uint64_t []) { 1024 });
496 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
497 if (obj_class >= NVE4_COMPUTE_CLASS) {
498 RET((uint64_t []) { 1024 });
499 } else {
500 RET((uint64_t []) { 512 });
501 }
502 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
503 RET((uint64_t []) { 1ULL << 40 });
504 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
505 switch (obj_class) {
506 case GM200_COMPUTE_CLASS:
507 RET((uint64_t []) { 96 << 10 });
508 break;
509 case GM107_COMPUTE_CLASS:
510 RET((uint64_t []) { 64 << 10 });
511 break;
512 default:
513 RET((uint64_t []) { 48 << 10 });
514 break;
515 }
516 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
517 RET((uint64_t []) { 512 << 10 });
518 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
519 RET((uint64_t []) { 4096 });
520 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
521 RET((uint32_t []) { 32 });
522 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
523 RET((uint64_t []) { 1ULL << 40 });
524 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
525 RET((uint32_t []) { 0 });
526 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
527 RET((uint32_t []) { screen->mp_count_compute });
528 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
529 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
530 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
531 RET((uint32_t []) { 64 });
532 default:
533 return 0;
534 }
535
536 #undef RET
537 }
538
539 static void
540 nvc0_screen_destroy(struct pipe_screen *pscreen)
541 {
542 struct nvc0_screen *screen = nvc0_screen(pscreen);
543
544 if (!nouveau_drm_screen_unref(&screen->base))
545 return;
546
547 if (screen->base.fence.current) {
548 struct nouveau_fence *current = NULL;
549
550 /* nouveau_fence_wait will create a new current fence, so wait on the
551 * _current_ one, and remove both.
552 */
553 nouveau_fence_ref(screen->base.fence.current, &current);
554 nouveau_fence_wait(current, NULL);
555 nouveau_fence_ref(NULL, &current);
556 nouveau_fence_ref(NULL, &screen->base.fence.current);
557 }
558 if (screen->base.pushbuf)
559 screen->base.pushbuf->user_priv = NULL;
560
561 if (screen->blitter)
562 nvc0_blitter_destroy(screen);
563 if (screen->pm.prog) {
564 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
565 nvc0_program_destroy(NULL, screen->pm.prog);
566 FREE(screen->pm.prog);
567 }
568
569 nouveau_bo_ref(NULL, &screen->text);
570 nouveau_bo_ref(NULL, &screen->uniform_bo);
571 nouveau_bo_ref(NULL, &screen->tls);
572 nouveau_bo_ref(NULL, &screen->txc);
573 nouveau_bo_ref(NULL, &screen->fence.bo);
574 nouveau_bo_ref(NULL, &screen->poly_cache);
575
576 nouveau_heap_destroy(&screen->lib_code);
577 nouveau_heap_destroy(&screen->text_heap);
578
579 FREE(screen->default_tsc);
580 FREE(screen->tic.entries);
581
582 nouveau_object_del(&screen->eng3d);
583 nouveau_object_del(&screen->eng2d);
584 nouveau_object_del(&screen->m2mf);
585 nouveau_object_del(&screen->compute);
586 nouveau_object_del(&screen->nvsw);
587
588 nouveau_screen_fini(&screen->base);
589
590 FREE(screen);
591 }
592
593 static int
594 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
595 unsigned size, const uint32_t *data)
596 {
597 struct nouveau_pushbuf *push = screen->base.pushbuf;
598
599 size /= 4;
600
601 assert((pos + size) <= 0x800);
602
603 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
604 PUSH_DATA (push, (m - 0x3800) / 8);
605 PUSH_DATA (push, pos);
606 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
607 PUSH_DATA (push, pos);
608 PUSH_DATAp(push, data, size);
609
610 return pos + size;
611 }
612
613 static void
614 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
615 {
616 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
617 PUSH_DATA (push, 0xff);
618 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
619 PUSH_DATA (push, 0xff);
620 PUSH_DATA (push, 0xff);
621 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
622 PUSH_DATA (push, 0xff);
623 PUSH_DATA (push, 0xff);
624 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
625 PUSH_DATA (push, 0x3f);
626
627 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
628 PUSH_DATA (push, (3 << 16) | 3);
629 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
630 PUSH_DATA (push, (2 << 16) | 2);
631
632 if (obj_class < GM107_3D_CLASS) {
633 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
634 PUSH_DATA (push, 0);
635 }
636 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
637 PUSH_DATA (push, 0x10);
638 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
639 PUSH_DATA (push, 0x10);
640 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
641 PUSH_DATA (push, 0x10);
642 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
643 PUSH_DATA (push, 0x10);
644 PUSH_DATA (push, 0x10);
645 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
646 PUSH_DATA (push, 0x10);
647 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
648 PUSH_DATA (push, 0xe);
649
650 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
651 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
652 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
653 PUSH_DATA (push, 0);
654 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
655 PUSH_DATA (push, 3);
656
657 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
658 PUSH_DATA (push, 0x3fffff);
659 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
660 PUSH_DATA (push, 1);
661 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
662 PUSH_DATA (push, 1);
663
664 if (obj_class < GM107_3D_CLASS) {
665 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
666 PUSH_DATA (push, 3);
667
668 if (obj_class >= NVE4_3D_CLASS) {
669 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
670 PUSH_DATA (push, 1);
671 }
672 }
673
674 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
675 * are supposed to do */
676 }
677
678 static void
679 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
680 {
681 struct nvc0_screen *screen = nvc0_screen(pscreen);
682 struct nouveau_pushbuf *push = screen->base.pushbuf;
683
684 /* we need to do it after possible flush in MARK_RING */
685 *sequence = ++screen->base.fence.sequence;
686
687 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
688 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
689 PUSH_DATAh(push, screen->fence.bo->offset);
690 PUSH_DATA (push, screen->fence.bo->offset);
691 PUSH_DATA (push, *sequence);
692 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
693 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
694 }
695
696 static u32
697 nvc0_screen_fence_update(struct pipe_screen *pscreen)
698 {
699 struct nvc0_screen *screen = nvc0_screen(pscreen);
700 return screen->fence.map[0];
701 }
702
703 static int
704 nvc0_screen_init_compute(struct nvc0_screen *screen)
705 {
706 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
707
708 switch (screen->base.device->chipset & ~0xf) {
709 case 0xc0:
710 case 0xd0:
711 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
712 case 0xe0:
713 case 0xf0:
714 case 0x100:
715 case 0x110:
716 case 0x120:
717 case 0x130:
718 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
719 default:
720 return -1;
721 }
722 }
723
724 static int
725 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
726 uint32_t lpos, uint32_t lneg, uint32_t cstack)
727 {
728 struct nouveau_bo *bo = NULL;
729 int ret;
730 uint64_t size = (lpos + lneg) * 32 + cstack;
731
732 if (size >= (1 << 20)) {
733 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
734 return -1;
735 }
736
737 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
738 size = align(size, 0x8000);
739 size *= screen->mp_count;
740
741 size = align(size, 1 << 17);
742
743 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
744 NULL, &bo);
745 if (ret)
746 return ret;
747
748 /* Make sure that the pushbuf has acquired a reference to the old tls
749 * segment, as it may have commands that will reference it.
750 */
751 if (screen->tls)
752 PUSH_REFN(screen->base.pushbuf, screen->tls,
753 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RDWR);
754 nouveau_bo_ref(NULL, &screen->tls);
755 screen->tls = bo;
756 return 0;
757 }
758
759 int
760 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
761 {
762 struct nouveau_pushbuf *push = screen->base.pushbuf;
763 struct nouveau_bo *bo;
764 int ret;
765
766 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
767 1 << 17, size, NULL, &bo);
768 if (ret)
769 return ret;
770
771 /* Make sure that the pushbuf has acquired a reference to the old text
772 * segment, as it may have commands that will reference it.
773 */
774 if (screen->text)
775 PUSH_REFN(push, screen->text,
776 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
777 nouveau_bo_ref(NULL, &screen->text);
778 screen->text = bo;
779
780 nouveau_heap_destroy(&screen->lib_code);
781 nouveau_heap_destroy(&screen->text_heap);
782
783 /* XXX: getting a page fault at the end of the code buffer every few
784 * launches, don't use the last 256 bytes to work around them - prefetch ?
785 */
786 nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
787
788 /* update the code segment setup */
789 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
790 PUSH_DATAh(push, screen->text->offset);
791 PUSH_DATA (push, screen->text->offset);
792 if (screen->compute) {
793 BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
794 PUSH_DATAh(push, screen->text->offset);
795 PUSH_DATA (push, screen->text->offset);
796 }
797
798 return 0;
799 }
800
801 #define FAIL_SCREEN_INIT(str, err) \
802 do { \
803 NOUVEAU_ERR(str, err); \
804 goto fail; \
805 } while(0)
806
807 struct nouveau_screen *
808 nvc0_screen_create(struct nouveau_device *dev)
809 {
810 struct nvc0_screen *screen;
811 struct pipe_screen *pscreen;
812 struct nouveau_object *chan;
813 struct nouveau_pushbuf *push;
814 uint64_t value;
815 uint32_t obj_class;
816 uint32_t flags;
817 int ret;
818 unsigned i;
819
820 switch (dev->chipset & ~0xf) {
821 case 0xc0:
822 case 0xd0:
823 case 0xe0:
824 case 0xf0:
825 case 0x100:
826 case 0x110:
827 case 0x120:
828 case 0x130:
829 break;
830 default:
831 return NULL;
832 }
833
834 screen = CALLOC_STRUCT(nvc0_screen);
835 if (!screen)
836 return NULL;
837 pscreen = &screen->base.base;
838 pscreen->destroy = nvc0_screen_destroy;
839
840 ret = nouveau_screen_init(&screen->base, dev);
841 if (ret)
842 FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
843 chan = screen->base.channel;
844 push = screen->base.pushbuf;
845 push->user_priv = screen;
846 push->rsvd_kick = 5;
847
848 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
849 PIPE_BIND_SHADER_BUFFER |
850 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
851 PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
852 screen->base.sysmem_bindings |=
853 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
854
855 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
856 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
857 screen->base.vidmem_bindings = 0;
858 }
859
860 pscreen->context_create = nvc0_create;
861 pscreen->is_format_supported = nvc0_screen_is_format_supported;
862 pscreen->get_param = nvc0_screen_get_param;
863 pscreen->get_shader_param = nvc0_screen_get_shader_param;
864 pscreen->get_paramf = nvc0_screen_get_paramf;
865 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
866 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
867
868 nvc0_screen_init_resource_functions(pscreen);
869
870 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
871 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
872
873 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
874 if (screen->base.drm->version >= 0x01000202)
875 flags |= NOUVEAU_BO_COHERENT;
876
877 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
878 if (ret)
879 FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
880 nouveau_bo_map(screen->fence.bo, 0, NULL);
881 screen->fence.map = screen->fence.bo->map;
882 screen->base.fence.emit = nvc0_screen_fence_emit;
883 screen->base.fence.update = nvc0_screen_fence_update;
884
885
886 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
887 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
888 if (ret)
889 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
890
891 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
892 PUSH_DATA (push, screen->nvsw->handle);
893
894 switch (dev->chipset & ~0xf) {
895 case 0x130:
896 case 0x120:
897 case 0x110:
898 case 0x100:
899 case 0xf0:
900 obj_class = NVF0_P2MF_CLASS;
901 break;
902 case 0xe0:
903 obj_class = NVE4_P2MF_CLASS;
904 break;
905 default:
906 obj_class = NVC0_M2MF_CLASS;
907 break;
908 }
909 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
910 &screen->m2mf);
911 if (ret)
912 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
913
914 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
915 PUSH_DATA (push, screen->m2mf->oclass);
916 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
917 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
918 PUSH_DATA (push, 0xa0b5);
919 }
920
921 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
922 &screen->eng2d);
923 if (ret)
924 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
925
926 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
927 PUSH_DATA (push, screen->eng2d->oclass);
928 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
929 PUSH_DATA (push, 0);
930 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
931 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
932 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
933 PUSH_DATA (push, 0);
934 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
935 PUSH_DATA (push, 0);
936 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
937 PUSH_DATA (push, 0x3f);
938 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
939 PUSH_DATA (push, 1);
940 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
941 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
942
943 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
944 PUSH_DATAh(push, screen->fence.bo->offset + 16);
945 PUSH_DATA (push, screen->fence.bo->offset + 16);
946
947 switch (dev->chipset & ~0xf) {
948 case 0x130:
949 switch (dev->chipset) {
950 case 0x130:
951 case 0x13b:
952 obj_class = GP100_3D_CLASS;
953 break;
954 default:
955 obj_class = GP102_3D_CLASS;
956 break;
957 }
958 break;
959 case 0x120:
960 obj_class = GM200_3D_CLASS;
961 break;
962 case 0x110:
963 obj_class = GM107_3D_CLASS;
964 break;
965 case 0x100:
966 case 0xf0:
967 obj_class = NVF0_3D_CLASS;
968 break;
969 case 0xe0:
970 switch (dev->chipset) {
971 case 0xea:
972 obj_class = NVEA_3D_CLASS;
973 break;
974 default:
975 obj_class = NVE4_3D_CLASS;
976 break;
977 }
978 break;
979 case 0xd0:
980 obj_class = NVC8_3D_CLASS;
981 break;
982 case 0xc0:
983 default:
984 switch (dev->chipset) {
985 case 0xc8:
986 obj_class = NVC8_3D_CLASS;
987 break;
988 case 0xc1:
989 obj_class = NVC1_3D_CLASS;
990 break;
991 default:
992 obj_class = NVC0_3D_CLASS;
993 break;
994 }
995 break;
996 }
997 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
998 &screen->eng3d);
999 if (ret)
1000 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
1001 screen->base.class_3d = obj_class;
1002
1003 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
1004 PUSH_DATA (push, screen->eng3d->oclass);
1005
1006 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
1007 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
1008
1009 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
1010 /* kill shaders after about 1 second (at 100 MHz) */
1011 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
1012 PUSH_DATA (push, 0x17);
1013 }
1014
1015 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
1016 screen->base.drm->version >= 0x01000101);
1017 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
1018 for (i = 0; i < 8; ++i)
1019 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
1020
1021 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
1022 PUSH_DATA (push, 1);
1023
1024 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
1025 PUSH_DATA (push, 0);
1026 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
1027 PUSH_DATA (push, 0);
1028 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
1029 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
1030 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
1031 PUSH_DATA (push, 0);
1032 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
1033 PUSH_DATA (push, 1);
1034 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
1035 PUSH_DATA (push, 1);
1036 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
1037 PUSH_DATA (push, 1);
1038 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
1039 PUSH_DATA (push, 0);
1040 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1041 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1042 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1043 IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1044 } else {
1045 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1046 PUSH_DATA (push, 15);
1047 }
1048 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1049 PUSH_DATA (push, 8); /* 128 */
1050 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1051 PUSH_DATA (push, 1);
1052 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1053 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1054 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1055 }
1056
1057 nvc0_magic_3d_init(push, screen->eng3d->oclass);
1058
1059 ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1060 if (ret)
1061 FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1062
1063 /* 6 user uniform areas, 6 driver areas, and 1 for the runout */
1064 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 13 << 16, NULL,
1065 &screen->uniform_bo);
1066 if (ret)
1067 FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1068
1069 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1070
1071 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1072 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1073 PUSH_DATA (push, 256);
1074 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1075 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1076 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1077 PUSH_DATA (push, 0);
1078 PUSH_DATAf(push, 0.0f);
1079 PUSH_DATAf(push, 0.0f);
1080 PUSH_DATAf(push, 0.0f);
1081 PUSH_DATAf(push, 0.0f);
1082 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1083 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1084 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1085
1086 if (screen->base.drm->version >= 0x01000101) {
1087 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1088 if (ret)
1089 FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1090 } else {
1091 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1092 value = (8 << 8) | 4;
1093 else
1094 value = (16 << 8) | 4;
1095 }
1096 screen->gpc_count = value & 0x000000ff;
1097 screen->mp_count = value >> 8;
1098 screen->mp_count_compute = screen->mp_count;
1099
1100 ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1101 if (ret)
1102 FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1103
1104 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1105 PUSH_DATAh(push, screen->tls->offset);
1106 PUSH_DATA (push, screen->tls->offset);
1107 PUSH_DATA (push, screen->tls->size >> 32);
1108 PUSH_DATA (push, screen->tls->size);
1109 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1110 PUSH_DATA (push, 0);
1111 /* Reduce likelihood of collision with real buffers by placing the hole at
1112 * the top of the 4G area. This will have to be dealt with for real
1113 * eventually by blocking off that area from the VM.
1114 */
1115 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1116 PUSH_DATA (push, 0xff << 24);
1117
1118 if (screen->eng3d->oclass < GM107_3D_CLASS) {
1119 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1120 &screen->poly_cache);
1121 if (ret)
1122 FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1123
1124 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1125 PUSH_DATAh(push, screen->poly_cache->offset);
1126 PUSH_DATA (push, screen->poly_cache->offset);
1127 PUSH_DATA (push, 3);
1128 }
1129
1130 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1131 &screen->txc);
1132 if (ret)
1133 FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1134
1135 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1136 PUSH_DATAh(push, screen->txc->offset);
1137 PUSH_DATA (push, screen->txc->offset);
1138 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1139 if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1140 screen->tic.maxwell = true;
1141 if (screen->eng3d->oclass == GM107_3D_CLASS) {
1142 screen->tic.maxwell =
1143 debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1144 IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1145 }
1146 }
1147
1148 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1149 PUSH_DATAh(push, screen->txc->offset + 65536);
1150 PUSH_DATA (push, screen->txc->offset + 65536);
1151 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1152
1153 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1154 PUSH_DATA (push, 0);
1155 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1156 PUSH_DATA (push, 0);
1157 PUSH_DATA (push, 0);
1158 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1159 PUSH_DATA (push, 0x3f);
1160
1161 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1162 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1163 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1164 for (i = 0; i < 8 * 2; ++i)
1165 PUSH_DATA(push, 0);
1166 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1167 PUSH_DATA (push, 0);
1168 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1169 PUSH_DATA (push, 0);
1170
1171 /* neither scissors, viewport nor stencil mask should affect clears */
1172 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1173 PUSH_DATA (push, 0);
1174
1175 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1176 PUSH_DATA (push, 1);
1177 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1178 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1179 PUSH_DATAf(push, 0.0f);
1180 PUSH_DATAf(push, 1.0f);
1181 }
1182 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1183 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1184
1185 /* We use scissors instead of exact view volume clipping,
1186 * so they're always enabled.
1187 */
1188 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1189 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1190 PUSH_DATA (push, 1);
1191 PUSH_DATA (push, 8192 << 16);
1192 PUSH_DATA (push, 8192 << 16);
1193 }
1194
1195 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1196
1197 i = 0;
1198 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1199 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1200 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1201 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1202 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1203 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1204 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1205 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1206 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1207 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1208 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1209 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1210 MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1211
1212 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1213 PUSH_DATA (push, 1);
1214 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1215 PUSH_DATA (push, 1);
1216 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1217 PUSH_DATA (push, 0x40);
1218 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1219 PUSH_DATA (push, 0);
1220 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1221 PUSH_DATA (push, 0x30);
1222 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1223 PUSH_DATA (push, 3);
1224 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1225 PUSH_DATA (push, 0x20);
1226 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1227 PUSH_DATA (push, 0x00);
1228 screen->save_state.patch_vertices = 3;
1229
1230 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1231 PUSH_DATA (push, 0);
1232 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1233 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1234
1235 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1236
1237 if (nvc0_screen_init_compute(screen))
1238 goto fail;
1239
1240 /* XXX: Compute and 3D are somehow aliased on Fermi. */
1241 for (i = 0; i < 5; ++i) {
1242 /* TIC and TSC entries for each unit (nve4+ only) */
1243 /* auxiliary constants (6 user clip planes, base instance id) */
1244 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1245 PUSH_DATA (push, NVC0_CB_AUX_SIZE);
1246 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1247 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1248 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
1249 PUSH_DATA (push, (15 << 4) | 1);
1250 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1251 unsigned j;
1252 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1253 PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1254 for (j = 0; j < 8; ++j)
1255 PUSH_DATA(push, j);
1256 } else {
1257 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1258 PUSH_DATA (push, 0x54);
1259 }
1260
1261 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1262 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1263 PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1264 PUSH_DATA (push, 0); /* 0 */
1265 PUSH_DATA (push, 0);
1266 PUSH_DATA (push, 1); /* 1 */
1267 PUSH_DATA (push, 0);
1268 PUSH_DATA (push, 0); /* 2 */
1269 PUSH_DATA (push, 1);
1270 PUSH_DATA (push, 1); /* 3 */
1271 PUSH_DATA (push, 1);
1272 PUSH_DATA (push, 2); /* 4 */
1273 PUSH_DATA (push, 0);
1274 PUSH_DATA (push, 3); /* 5 */
1275 PUSH_DATA (push, 0);
1276 PUSH_DATA (push, 2); /* 6 */
1277 PUSH_DATA (push, 1);
1278 PUSH_DATA (push, 3); /* 7 */
1279 PUSH_DATA (push, 1);
1280 }
1281 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1282 PUSH_DATA (push, 0);
1283
1284 PUSH_KICK (push);
1285
1286 screen->tic.entries = CALLOC(
1287 NVC0_TIC_MAX_ENTRIES + NVC0_TSC_MAX_ENTRIES + NVE4_IMG_MAX_HANDLES,
1288 sizeof(void *));
1289 screen->tsc.entries = screen->tic.entries + NVC0_TIC_MAX_ENTRIES;
1290 screen->img.entries = (void *)(screen->tsc.entries + NVC0_TSC_MAX_ENTRIES);
1291
1292 if (!nvc0_blitter_create(screen))
1293 goto fail;
1294
1295 screen->default_tsc = CALLOC_STRUCT(nv50_tsc_entry);
1296 screen->default_tsc->tsc[0] = G80_TSC_0_SRGB_CONVERSION;
1297
1298 nouveau_fence_new(&screen->base, &screen->base.fence.current);
1299
1300 return &screen->base;
1301
1302 fail:
1303 screen->base.base.context_create = NULL;
1304 return &screen->base;
1305 }
1306
1307 int
1308 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1309 {
1310 int i = screen->tic.next;
1311
1312 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1313 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1314
1315 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1316
1317 if (screen->tic.entries[i])
1318 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1319
1320 screen->tic.entries[i] = entry;
1321 return i;
1322 }
1323
1324 int
1325 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1326 {
1327 int i = screen->tsc.next;
1328
1329 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1330 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1331
1332 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1333
1334 if (screen->tsc.entries[i])
1335 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1336
1337 screen->tsc.entries[i] = entry;
1338 return i;
1339 }