src/gallium/drivers/nouveau/nvc0/nvc0_screen.h

   1 #ifndef __NVC0_SCREEN_H__
   2 #define __NVC0_SCREEN_H__
   3
   4 #include "nouveau_screen.h"
   5 #include "nouveau_mm.h"
   6 #include "nouveau_fence.h"
   7 #include "nouveau_heap.h"
   8
   9 #include "nv_object.xml.h"
  10
  11 #include "nvc0/nvc0_winsys.h"
  12 #include "nvc0/nvc0_stateobj.h"
  13
  14 #define NVC0_TIC_MAX_ENTRIES 2048
  15 #define NVC0_TSC_MAX_ENTRIES 2048
  16 #define NVE4_IMG_MAX_HANDLES 512
  17
  18 /* doesn't count driver-reserved slot */
  19 #define NVC0_MAX_PIPE_CONSTBUFS 15
  20 #define NVC0_MAX_CONST_BUFFERS  16
  21 #define NVC0_MAX_CONSTBUF_SIZE  65536
  22
  23 #define NVC0_MAX_SURFACE_SLOTS 16
  24
  25 #define NVC0_MAX_VIEWPORTS 16
  26
  27 #define NVC0_MAX_BUFFERS 32
  28
  29 #define NVC0_MAX_IMAGES 8
  30
  31 #define NVC0_MAX_WINDOW_RECTANGLES 8
  32
  33 struct nvc0_context;
  34
  35 struct nvc0_blitter;
  36
  37 struct nvc0_graph_state {
  38    bool flushed;
  39    bool rasterizer_discard;
  40    bool early_z_forced;
  41    bool prim_restart;
  42    uint32_t instance_elts; /* bitmask of per-instance elements */
  43    uint32_t instance_base;
  44    uint32_t constant_vbos;
  45    uint32_t constant_elts;
  46    int32_t index_bias;
  47    uint16_t scissor;
  48    bool flatshade;
  49    uint8_t patch_vertices;
  50    uint8_t vbo_mode; /* 0 = normal, 1 = translate, 3 = translate, forced */
  51    uint8_t num_vtxbufs;
  52    uint8_t num_vtxelts;
  53    uint8_t num_textures[6];
  54    uint8_t num_samplers[6];
  55    uint8_t tls_required; /* bitmask of shader types using l[] */
  56    uint8_t clip_enable;
  57    uint32_t clip_mode;
  58    bool uniform_buffer_bound[6];
  59    struct nvc0_transform_feedback_state *tfb;
  60    bool seamless_cube_map;
  61    bool post_depth_coverage;
  62 };
  63
  64 struct nvc0_cb_binding {
  65    uint64_t addr;
  66    int size;
  67 };
  68
  69 struct nvc0_screen {
  70    struct nouveau_screen base;
  71
  72    struct nvc0_context *cur_ctx;
  73    struct nvc0_graph_state save_state;
  74
  75    int num_occlusion_queries_active;
  76
  77    struct nouveau_bo *text;
  78    struct nouveau_bo *uniform_bo;
  79    struct nouveau_bo *tls;
  80    struct nouveau_bo *txc; /* TIC (offset 0) and TSC (65536) */
  81    struct nouveau_bo *poly_cache;
  82
  83    uint8_t gpc_count;
  84    uint16_t mp_count;
  85    uint16_t mp_count_compute; /* magic reg can make compute use fewer MPs */
  86
  87    struct nouveau_heap *text_heap;
  88    struct nouveau_heap *lib_code; /* allocated from text_heap */
  89
  90    struct nvc0_blitter *blitter;
  91
  92    struct nv50_tsc_entry *default_tsc;
  93
  94    struct {
  95       void **entries;
  96       int next;
  97       uint32_t lock[NVC0_TIC_MAX_ENTRIES / 32];
  98       bool maxwell;
  99    } tic;
 100
 101    struct {
 102       void **entries;
 103       int next;
 104       uint32_t lock[NVC0_TSC_MAX_ENTRIES / 32];
 105    } tsc;
 106
 107    struct {
 108       struct pipe_image_view **entries;
 109       int next;
 110    } img;
 111
 112    struct {
 113       struct nouveau_bo *bo;
 114       uint32_t *map;
 115    } fence;
 116
 117    struct {
 118       struct nvc0_program *prog; /* compute state object to read MP counters */
 119       struct nvc0_hw_sm_query *mp_counter[8]; /* counter to query allocation */
 120       uint8_t num_hw_sm_active[2];
 121       bool mp_counters_enabled;
 122    } pm;
 123
 124    /* only maintained on Maxwell+ */
 125    struct nvc0_cb_binding cb_bindings[5][NVC0_MAX_CONST_BUFFERS];
 126
 127    struct nouveau_object *eng3d; /* sqrt(1/2)|kepler> + sqrt(1/2)|fermi> */
 128    struct nouveau_object *eng2d;
 129    struct nouveau_object *m2mf;
 130    struct nouveau_object *compute;
 131    struct nouveau_object *nvsw;
 132 };
 133
 134 static inline struct nvc0_screen *
 135 nvc0_screen(struct pipe_screen *screen)
 136 {
 137    return (struct nvc0_screen *)screen;
 138 }
 139
 140 int nvc0_screen_get_driver_query_info(struct pipe_screen *, unsigned,
 141                                       struct pipe_driver_query_info *);
 142
 143 int nvc0_screen_get_driver_query_group_info(struct pipe_screen *, unsigned,
 144                                             struct pipe_driver_query_group_info *);
 145
 146 bool nvc0_blitter_create(struct nvc0_screen *);
 147 void nvc0_blitter_destroy(struct nvc0_screen *);
 148
 149 void nvc0_screen_make_buffers_resident(struct nvc0_screen *);
 150
 151 int nvc0_screen_tic_alloc(struct nvc0_screen *, void *);
 152 int nvc0_screen_tsc_alloc(struct nvc0_screen *, void *);
 153
 154 int nve4_screen_compute_setup(struct nvc0_screen *, struct nouveau_pushbuf *);
 155 int nvc0_screen_compute_setup(struct nvc0_screen *, struct nouveau_pushbuf *);
 156
 157 int nvc0_screen_resize_text_area(struct nvc0_screen *, uint64_t);
 158
 159 // 3D Only
 160 void nvc0_screen_bind_cb_3d(struct nvc0_screen *, bool *, int, int, int, uint64_t);
 161
 162 static inline void
 163 nvc0_resource_fence(struct nv04_resource *res, uint32_t flags)
 164 {
 165    struct nvc0_screen *screen = nvc0_screen(res->base.screen);
 166
 167    if (res->mm) {
 168       nouveau_fence_ref(screen->base.fence.current, &res->fence);
 169       if (flags & NOUVEAU_BO_WR)
 170          nouveau_fence_ref(screen->base.fence.current, &res->fence_wr);
 171    }
 172 }
 173
 174 static inline void
 175 nvc0_resource_validate(struct nv04_resource *res, uint32_t flags)
 176 {
 177    if (likely(res->bo)) {
 178       if (flags & NOUVEAU_BO_WR)
 179          res->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING |
 180             NOUVEAU_BUFFER_STATUS_DIRTY;
 181       if (flags & NOUVEAU_BO_RD)
 182          res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
 183
 184       nvc0_resource_fence(res, flags);
 185    }
 186 }
 187
 188 struct nvc0_format {
 189    uint32_t rt;
 190    struct {
 191       unsigned format:7;
 192       unsigned type_r:3;
 193       unsigned type_g:3;
 194       unsigned type_b:3;
 195       unsigned type_a:3;
 196       unsigned src_x:3;
 197       unsigned src_y:3;
 198       unsigned src_z:3;
 199       unsigned src_w:3;
 200    } tic;
 201    uint32_t usage;
 202 };
 203
 204 struct nvc0_vertex_format {
 205    uint32_t vtx;
 206    uint32_t usage;
 207 };
 208
 209 extern const struct nvc0_format nvc0_format_table[];
 210 extern const struct nvc0_vertex_format nvc0_vertex_format[];
 211
 212 static inline void
 213 nvc0_screen_tic_unlock(struct nvc0_screen *screen, struct nv50_tic_entry *tic)
 214 {
 215    if (tic->bindless)
 216       return;
 217    if (tic->id >= 0)
 218       screen->tic.lock[tic->id / 32] &= ~(1 << (tic->id % 32));
 219 }
 220
 221 static inline void
 222 nvc0_screen_tsc_unlock(struct nvc0_screen *screen, struct nv50_tsc_entry *tsc)
 223 {
 224    if (tsc->id >= 0)
 225       screen->tsc.lock[tsc->id / 32] &= ~(1 << (tsc->id % 32));
 226 }
 227
 228 static inline void
 229 nvc0_screen_tic_free(struct nvc0_screen *screen, struct nv50_tic_entry *tic)
 230 {
 231    if (tic->id >= 0) {
 232       screen->tic.entries[tic->id] = NULL;
 233       screen->tic.lock[tic->id / 32] &= ~(1 << (tic->id % 32));
 234    }
 235 }
 236
 237 static inline void
 238 nvc0_screen_tsc_free(struct nvc0_screen *screen, struct nv50_tsc_entry *tsc)
 239 {
 240    if (tsc->id >= 0) {
 241       screen->tsc.entries[tsc->id] = NULL;
 242       screen->tsc.lock[tsc->id / 32] &= ~(1 << (tsc->id % 32));
 243    }
 244 }
 245
 246 #endif