src/gallium/drivers/nouveau/nvc0/nvc0_screen.h

   1 #ifndef __NVC0_SCREEN_H__
   2 #define __NVC0_SCREEN_H__
   3
   4 #include "nouveau_screen.h"
   5 #include "nouveau_mm.h"
   6 #include "nouveau_fence.h"
   7 #include "nouveau_heap.h"
   8
   9 #include "nv_object.xml.h"
  10
  11 #include "nvc0/nvc0_winsys.h"
  12 #include "nvc0/nvc0_stateobj.h"
  13
  14 #define NVC0_TIC_MAX_ENTRIES 2048
  15 #define NVC0_TSC_MAX_ENTRIES 2048
  16
  17 /* doesn't count reserved slots (for auxiliary constants, immediates, etc.) */
  18 #define NVC0_MAX_PIPE_CONSTBUFS         14
  19 #define NVE4_MAX_PIPE_CONSTBUFS_COMPUTE  7
  20
  21 #define NVC0_MAX_SURFACE_SLOTS 16
  22
  23 #define NVC0_MAX_VIEWPORTS 16
  24
  25
  26 struct nvc0_context;
  27
  28 struct nvc0_blitter;
  29
  30 struct nvc0_screen {
  31    struct nouveau_screen base;
  32
  33    struct nvc0_context *cur_ctx;
  34
  35    int num_occlusion_queries_active;
  36
  37    struct nouveau_bo *text;
  38    struct nouveau_bo *parm;       /* for COMPUTE */
  39    struct nouveau_bo *uniform_bo; /* for 3D */
  40    struct nouveau_bo *tls;
  41    struct nouveau_bo *txc; /* TIC (offset 0) and TSC (65536) */
  42    struct nouveau_bo *poly_cache;
  43
  44    uint16_t mp_count;
  45    uint16_t mp_count_compute; /* magic reg can make compute use fewer MPs */
  46
  47    struct nouveau_heap *text_heap;
  48    struct nouveau_heap *lib_code; /* allocated from text_heap */
  49
  50    struct nvc0_blitter *blitter;
  51
  52    struct {
  53       void **entries;
  54       int next;
  55       uint32_t lock[NVC0_TIC_MAX_ENTRIES / 32];
  56    } tic;
  57
  58    struct {
  59       void **entries;
  60       int next;
  61       uint32_t lock[NVC0_TSC_MAX_ENTRIES / 32];
  62    } tsc;
  63
  64    struct {
  65       struct nouveau_bo *bo;
  66       uint32_t *map;
  67    } fence;
  68
  69    struct {
  70       struct nvc0_program *prog; /* compute state object to read MP counters */
  71       struct pipe_query *mp_counter[8]; /* counter to query allocation */
  72       uint8_t num_mp_pm_active[2];
  73       boolean mp_counters_enabled;
  74    } pm;
  75
  76    struct nouveau_object *eng3d; /* sqrt(1/2)|kepler> + sqrt(1/2)|fermi> */
  77    struct nouveau_object *eng2d;
  78    struct nouveau_object *m2mf;
  79    struct nouveau_object *compute;
  80    struct nouveau_object *nvsw;
  81 };
  82
  83 static INLINE struct nvc0_screen *
  84 nvc0_screen(struct pipe_screen *screen)
  85 {
  86    return (struct nvc0_screen *)screen;
  87 }
  88
  89 /*
  90  * Performance counters groups:
  91  */
  92 #define NVC0_QUERY_MP_COUNTER_GROUP 0
  93 #define NVC0_QUERY_DRV_STAT_GROUP   1
  94
  95 /* Performance counter queries:
  96  */
  97 #define NVE4_PM_QUERY_COUNT  49
  98 #define NVE4_PM_QUERY(i)    (PIPE_QUERY_DRIVER_SPECIFIC + (i))
  99 #define NVE4_PM_QUERY_LAST   NVE4_PM_QUERY(NVE4_PM_QUERY_COUNT - 1)
 100 #define NVE4_PM_QUERY_PROF_TRIGGER_0            0
 101 #define NVE4_PM_QUERY_PROF_TRIGGER_1            1
 102 #define NVE4_PM_QUERY_PROF_TRIGGER_2            2
 103 #define NVE4_PM_QUERY_PROF_TRIGGER_3            3
 104 #define NVE4_PM_QUERY_PROF_TRIGGER_4            4
 105 #define NVE4_PM_QUERY_PROF_TRIGGER_5            5
 106 #define NVE4_PM_QUERY_PROF_TRIGGER_6            6
 107 #define NVE4_PM_QUERY_PROF_TRIGGER_7            7
 108 #define NVE4_PM_QUERY_LAUNCHED_WARPS            8
 109 #define NVE4_PM_QUERY_LAUNCHED_THREADS          9
 110 #define NVE4_PM_QUERY_LAUNCHED_CTA              10
 111 #define NVE4_PM_QUERY_INST_ISSUED1              11
 112 #define NVE4_PM_QUERY_INST_ISSUED2              12
 113 #define NVE4_PM_QUERY_INST_EXECUTED             13
 114 #define NVE4_PM_QUERY_LD_LOCAL                  14
 115 #define NVE4_PM_QUERY_ST_LOCAL                  15
 116 #define NVE4_PM_QUERY_LD_SHARED                 16
 117 #define NVE4_PM_QUERY_ST_SHARED                 17
 118 #define NVE4_PM_QUERY_L1_LOCAL_LOAD_HIT         18
 119 #define NVE4_PM_QUERY_L1_LOCAL_LOAD_MISS        19
 120 #define NVE4_PM_QUERY_L1_LOCAL_STORE_HIT        20
 121 #define NVE4_PM_QUERY_L1_LOCAL_STORE_MISS       21
 122 #define NVE4_PM_QUERY_GLD_REQUEST               22
 123 #define NVE4_PM_QUERY_GST_REQUEST               23
 124 #define NVE4_PM_QUERY_L1_GLOBAL_LOAD_HIT        24
 125 #define NVE4_PM_QUERY_L1_GLOBAL_LOAD_MISS       25
 126 #define NVE4_PM_QUERY_GLD_TRANSACTIONS_UNCACHED 26
 127 #define NVE4_PM_QUERY_GST_TRANSACTIONS          27
 128 #define NVE4_PM_QUERY_BRANCH                    28
 129 #define NVE4_PM_QUERY_BRANCH_DIVERGENT          29
 130 #define NVE4_PM_QUERY_ACTIVE_WARPS              30
 131 #define NVE4_PM_QUERY_ACTIVE_CYCLES             31
 132 #define NVE4_PM_QUERY_INST_ISSUED               32
 133 #define NVE4_PM_QUERY_ATOM_COUNT                33
 134 #define NVE4_PM_QUERY_GRED_COUNT                34
 135 #define NVE4_PM_QUERY_LD_SHARED_REPLAY          35
 136 #define NVE4_PM_QUERY_ST_SHARED_REPLAY          36
 137 #define NVE4_PM_QUERY_LD_LOCAL_TRANSACTIONS     37
 138 #define NVE4_PM_QUERY_ST_LOCAL_TRANSACTIONS     38
 139 #define NVE4_PM_QUERY_L1_LD_SHARED_TRANSACTIONS 39
 140 #define NVE4_PM_QUERY_L1_ST_SHARED_TRANSACTIONS 40
 141 #define NVE4_PM_QUERY_GLD_MEM_DIV_REPLAY        41
 142 #define NVE4_PM_QUERY_GST_MEM_DIV_REPLAY        42
 143 #define NVE4_PM_QUERY_METRIC_IPC                43
 144 #define NVE4_PM_QUERY_METRIC_IPAC               44
 145 #define NVE4_PM_QUERY_METRIC_IPEC               45
 146 #define NVE4_PM_QUERY_METRIC_MP_OCCUPANCY       46
 147 #define NVE4_PM_QUERY_METRIC_MP_EFFICIENCY      47
 148 #define NVE4_PM_QUERY_METRIC_INST_REPLAY_OHEAD  48
 149
 150 /*
 151 #define NVE4_PM_QUERY_GR_IDLE                   50
 152 #define NVE4_PM_QUERY_BSP_IDLE                  51
 153 #define NVE4_PM_QUERY_VP_IDLE                   52
 154 #define NVE4_PM_QUERY_PPP_IDLE                  53
 155 #define NVE4_PM_QUERY_CE0_IDLE                  54
 156 #define NVE4_PM_QUERY_CE1_IDLE                  55
 157 #define NVE4_PM_QUERY_CE2_IDLE                  56
 158 */
 159 /* L2 queries (PCOUNTER) */
 160 /*
 161 #define NVE4_PM_QUERY_L2_SUBP_WRITE_L1_SECTOR_QUERIES 57
 162 ...
 163 */
 164 /* TEX queries (PCOUNTER) */
 165 /*
 166 #define NVE4_PM_QUERY_TEX0_CACHE_SECTOR_QUERIES 58
 167 ...
 168 */
 169
 170 #define NVC0_PM_QUERY_COUNT 31
 171 #define NVC0_PM_QUERY(i)    (PIPE_QUERY_DRIVER_SPECIFIC + 2048 + (i))
 172 #define NVC0_PM_QUERY_LAST   NVC0_PM_QUERY(NVC0_PM_QUERY_COUNT - 1)
 173 #define NVC0_PM_QUERY_INST_EXECUTED             0
 174 #define NVC0_PM_QUERY_BRANCH                    1
 175 #define NVC0_PM_QUERY_BRANCH_DIVERGENT          2
 176 #define NVC0_PM_QUERY_ACTIVE_WARPS              3
 177 #define NVC0_PM_QUERY_ACTIVE_CYCLES             4
 178 #define NVC0_PM_QUERY_LAUNCHED_WARPS            5
 179 #define NVC0_PM_QUERY_LAUNCHED_THREADS          6
 180 #define NVC0_PM_QUERY_LD_SHARED                 7
 181 #define NVC0_PM_QUERY_ST_SHARED                 8
 182 #define NVC0_PM_QUERY_LD_LOCAL                  9
 183 #define NVC0_PM_QUERY_ST_LOCAL                  10
 184 #define NVC0_PM_QUERY_GRED_COUNT                11
 185 #define NVC0_PM_QUERY_ATOM_COUNT                12
 186 #define NVC0_PM_QUERY_GLD_REQUEST               13
 187 #define NVC0_PM_QUERY_GST_REQUEST               14
 188 #define NVC0_PM_QUERY_INST_ISSUED1_0            15
 189 #define NVC0_PM_QUERY_INST_ISSUED1_1            16
 190 #define NVC0_PM_QUERY_INST_ISSUED2_0            17
 191 #define NVC0_PM_QUERY_INST_ISSUED2_1            18
 192 #define NVC0_PM_QUERY_TH_INST_EXECUTED_0        19
 193 #define NVC0_PM_QUERY_TH_INST_EXECUTED_1        20
 194 #define NVC0_PM_QUERY_TH_INST_EXECUTED_2        21
 195 #define NVC0_PM_QUERY_TH_INST_EXECUTED_3        22
 196 #define NVC0_PM_QUERY_PROF_TRIGGER_0            23
 197 #define NVC0_PM_QUERY_PROF_TRIGGER_1            24
 198 #define NVC0_PM_QUERY_PROF_TRIGGER_2            25
 199 #define NVC0_PM_QUERY_PROF_TRIGGER_3            26
 200 #define NVC0_PM_QUERY_PROF_TRIGGER_4            27
 201 #define NVC0_PM_QUERY_PROF_TRIGGER_5            28
 202 #define NVC0_PM_QUERY_PROF_TRIGGER_6            29
 203 #define NVC0_PM_QUERY_PROF_TRIGGER_7            30
 204
 205 /* Driver statistics queries:
 206  */
 207 #ifdef NOUVEAU_ENABLE_DRIVER_STATISTICS
 208
 209 #define NVC0_QUERY_DRV_STAT(i)    (PIPE_QUERY_DRIVER_SPECIFIC + 1024 + (i))
 210 #define NVC0_QUERY_DRV_STAT_COUNT  29
 211 #define NVC0_QUERY_DRV_STAT_LAST   NVC0_QUERY_DRV_STAT(NVC0_QUERY_DRV_STAT_COUNT - 1)
 212 #define NVC0_QUERY_DRV_STAT_TEX_OBJECT_CURRENT_COUNT         0
 213 #define NVC0_QUERY_DRV_STAT_TEX_OBJECT_CURRENT_BYTES         1
 214 #define NVC0_QUERY_DRV_STAT_BUF_OBJECT_CURRENT_COUNT         2
 215 #define NVC0_QUERY_DRV_STAT_BUF_OBJECT_CURRENT_BYTES_VID     3
 216 #define NVC0_QUERY_DRV_STAT_BUF_OBJECT_CURRENT_BYTES_SYS     4
 217 #define NVC0_QUERY_DRV_STAT_TEX_TRANSFERS_READ               5
 218 #define NVC0_QUERY_DRV_STAT_TEX_TRANSFERS_WRITE              6
 219 #define NVC0_QUERY_DRV_STAT_TEX_COPY_COUNT                   7
 220 #define NVC0_QUERY_DRV_STAT_TEX_BLIT_COUNT                   8
 221 #define NVC0_QUERY_DRV_STAT_TEX_CACHE_FLUSH_COUNT            9
 222 #define NVC0_QUERY_DRV_STAT_BUF_TRANSFERS_READ              10
 223 #define NVC0_QUERY_DRV_STAT_BUF_TRANSFERS_WRITE             11
 224 #define NVC0_QUERY_DRV_STAT_BUF_READ_BYTES_STAGING_VID      12
 225 #define NVC0_QUERY_DRV_STAT_BUF_WRITE_BYTES_DIRECT          13
 226 #define NVC0_QUERY_DRV_STAT_BUF_WRITE_BYTES_STAGING_VID     14
 227 #define NVC0_QUERY_DRV_STAT_BUF_WRITE_BYTES_STAGING_SYS     15
 228 #define NVC0_QUERY_DRV_STAT_BUF_COPY_BYTES                  16
 229 #define NVC0_QUERY_DRV_STAT_BUF_NON_KERNEL_FENCE_SYNC_COUNT 17
 230 #define NVC0_QUERY_DRV_STAT_ANY_NON_KERNEL_FENCE_SYNC_COUNT 18
 231 #define NVC0_QUERY_DRV_STAT_QUERY_SYNC_COUNT                19
 232 #define NVC0_QUERY_DRV_STAT_GPU_SERIALIZE_COUNT             20
 233 #define NVC0_QUERY_DRV_STAT_DRAW_CALLS_ARRAY                21
 234 #define NVC0_QUERY_DRV_STAT_DRAW_CALLS_INDEXED              22
 235 #define NVC0_QUERY_DRV_STAT_DRAW_CALLS_FALLBACK_COUNT       23
 236 #define NVC0_QUERY_DRV_STAT_USER_BUFFER_UPLOAD_BYTES        24
 237 #define NVC0_QUERY_DRV_STAT_CONSTBUF_UPLOAD_COUNT           25
 238 #define NVC0_QUERY_DRV_STAT_CONSTBUF_UPLOAD_BYTES           26
 239 #define NVC0_QUERY_DRV_STAT_PUSHBUF_COUNT                   27
 240 #define NVC0_QUERY_DRV_STAT_RESOURCE_VALIDATE_COUNT         28
 241
 242 #else
 243
 244 #define NVC0_QUERY_DRV_STAT_COUNT 0
 245
 246 #endif
 247
 248 int nvc0_screen_get_driver_query_info(struct pipe_screen *, unsigned,
 249                                       struct pipe_driver_query_info *);
 250
 251 int nvc0_screen_get_driver_query_group_info(struct pipe_screen *, unsigned,
 252                                             struct pipe_driver_query_group_info *);
 253
 254 boolean nvc0_blitter_create(struct nvc0_screen *);
 255 void nvc0_blitter_destroy(struct nvc0_screen *);
 256
 257 void nvc0_screen_make_buffers_resident(struct nvc0_screen *);
 258
 259 int nvc0_screen_tic_alloc(struct nvc0_screen *, void *);
 260 int nvc0_screen_tsc_alloc(struct nvc0_screen *, void *);
 261
 262 int nve4_screen_compute_setup(struct nvc0_screen *, struct nouveau_pushbuf *);
 263 int nvc0_screen_compute_setup(struct nvc0_screen *, struct nouveau_pushbuf *);
 264
 265 boolean nvc0_screen_resize_tls_area(struct nvc0_screen *, uint32_t lpos,
 266                                     uint32_t lneg, uint32_t cstack);
 267
 268 static INLINE void
 269 nvc0_resource_fence(struct nv04_resource *res, uint32_t flags)
 270 {
 271    struct nvc0_screen *screen = nvc0_screen(res->base.screen);
 272
 273    if (res->mm) {
 274       nouveau_fence_ref(screen->base.fence.current, &res->fence);
 275       if (flags & NOUVEAU_BO_WR)
 276          nouveau_fence_ref(screen->base.fence.current, &res->fence_wr);
 277    }
 278 }
 279
 280 static INLINE void
 281 nvc0_resource_validate(struct nv04_resource *res, uint32_t flags)
 282 {
 283    if (likely(res->bo)) {
 284       if (flags & NOUVEAU_BO_WR)
 285          res->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING |
 286             NOUVEAU_BUFFER_STATUS_DIRTY;
 287       if (flags & NOUVEAU_BO_RD)
 288          res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
 289
 290       nvc0_resource_fence(res, flags);
 291    }
 292 }
 293
 294 struct nvc0_format {
 295    uint32_t rt;
 296    uint32_t tic;
 297    uint32_t vtx;
 298    uint32_t usage;
 299 };
 300
 301 extern const struct nvc0_format nvc0_format_table[];
 302
 303 static INLINE void
 304 nvc0_screen_tic_unlock(struct nvc0_screen *screen, struct nv50_tic_entry *tic)
 305 {
 306    if (tic->id >= 0)
 307       screen->tic.lock[tic->id / 32] &= ~(1 << (tic->id % 32));
 308 }
 309
 310 static INLINE void
 311 nvc0_screen_tsc_unlock(struct nvc0_screen *screen, struct nv50_tsc_entry *tsc)
 312 {
 313    if (tsc->id >= 0)
 314       screen->tsc.lock[tsc->id / 32] &= ~(1 << (tsc->id % 32));
 315 }
 316
 317 static INLINE void
 318 nvc0_screen_tic_free(struct nvc0_screen *screen, struct nv50_tic_entry *tic)
 319 {
 320    if (tic->id >= 0) {
 321       screen->tic.entries[tic->id] = NULL;
 322       screen->tic.lock[tic->id / 32] &= ~(1 << (tic->id % 32));
 323    }
 324 }
 325
 326 static INLINE void
 327 nvc0_screen_tsc_free(struct nvc0_screen *screen, struct nv50_tsc_entry *tsc)
 328 {
 329    if (tsc->id >= 0) {
 330       screen->tsc.entries[tsc->id] = NULL;
 331       screen->tsc.lock[tsc->id / 32] &= ~(1 << (tsc->id % 32));
 332    }
 333 }
 334
 335 #endif