src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "pipe/p_context.h"
  24 #include "pipe/p_defines.h"
  25 #include "pipe/p_state.h"
  26 #include "util/u_inlines.h"
  27
  28 #include "nvc0/nvc0_context.h"
  29 #include "nvc0/nvc0_query_hw.h"
  30
  31 static inline void
  32 nvc0_program_update_context_state(struct nvc0_context *nvc0,
  33                                   struct nvc0_program *prog, int stage)
  34 {
  35    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
  36
  37    if (prog && prog->need_tls) {
  38       const uint32_t flags = NV_VRAM_DOMAIN(&nvc0->screen->base) | NOUVEAU_BO_RDWR;
  39       if (!nvc0->state.tls_required)
  40          BCTX_REFN_bo(nvc0->bufctx_3d, 3D_TLS, flags, nvc0->screen->tls);
  41       nvc0->state.tls_required |= 1 << stage;
  42    } else {
  43       if (nvc0->state.tls_required == (1 << stage))
  44          nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TLS);
  45       nvc0->state.tls_required &= ~(1 << stage);
  46    }
  47
  48    if (prog && prog->immd_size) {
  49       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
  50       /* NOTE: may overlap code of a different shader */
  51       PUSH_DATA (push, align(prog->immd_size, 0x100));
  52       PUSH_DATAh(push, nvc0->screen->text->offset + prog->immd_base);
  53       PUSH_DATA (push, nvc0->screen->text->offset + prog->immd_base);
  54       BEGIN_NVC0(push, NVC0_3D(CB_BIND(stage)), 1);
  55       PUSH_DATA (push, (14 << 4) | 1);
  56
  57       nvc0->state.c14_bound |= 1 << stage;
  58    } else
  59    if (nvc0->state.c14_bound & (1 << stage)) {
  60       BEGIN_NVC0(push, NVC0_3D(CB_BIND(stage)), 1);
  61       PUSH_DATA (push, (14 << 4) | 0);
  62
  63       nvc0->state.c14_bound &= ~(1 << stage);
  64    }
  65 }
  66
  67 static inline bool
  68 nvc0_program_validate(struct nvc0_context *nvc0, struct nvc0_program *prog)
  69 {
  70    if (prog->mem)
  71       return true;
  72
  73    if (!prog->translated) {
  74       prog->translated = nvc0_program_translate(
  75          prog, nvc0->screen->base.device->chipset, &nvc0->base.debug);
  76       if (!prog->translated)
  77          return false;
  78    }
  79
  80    if (likely(prog->code_size))
  81       return nvc0_program_upload_code(nvc0, prog);
  82    return true; /* stream output info only */
  83 }
  84
  85 void
  86 nvc0_vertprog_validate(struct nvc0_context *nvc0)
  87 {
  88    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
  89    struct nvc0_program *vp = nvc0->vertprog;
  90
  91    if (!nvc0_program_validate(nvc0, vp))
  92          return;
  93    nvc0_program_update_context_state(nvc0, vp, 0);
  94
  95    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(1)), 2);
  96    PUSH_DATA (push, 0x11);
  97    PUSH_DATA (push, vp->code_base);
  98    BEGIN_NVC0(push, NVC0_3D(SP_GPR_ALLOC(1)), 1);
  99    PUSH_DATA (push, vp->num_gprs);
 100
 101    // BEGIN_NVC0(push, NVC0_3D_(0x163c), 1);
 102    // PUSH_DATA (push, 0);
 103 }
 104
 105 void
 106 nvc0_fragprog_validate(struct nvc0_context *nvc0)
 107 {
 108    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 109    struct nvc0_program *fp = nvc0->fragprog;
 110    struct pipe_rasterizer_state *rast = &nvc0->rast->pipe;
 111
 112    if (fp->fp.force_persample_interp != rast->force_persample_interp) {
 113       /* Force the program to be reuploaded, which will trigger interp fixups
 114        * to get applied
 115        */
 116       if (fp->mem)
 117          nouveau_heap_free(&fp->mem);
 118
 119       fp->fp.force_persample_interp = rast->force_persample_interp;
 120    }
 121
 122    /* Shade model works well enough when both colors follow it. However if one
 123     * (or both) is explicitly set, then we have to go the patching route.
 124     */
 125    bool has_explicit_color = fp->fp.colors &&
 126       (((fp->fp.colors & 1) && !fp->fp.color_interp[0]) ||
 127        ((fp->fp.colors & 2) && !fp->fp.color_interp[1]));
 128    bool hwflatshade = false;
 129    if (has_explicit_color && fp->fp.flatshade != rast->flatshade) {
 130       /* Force re-upload */
 131       if (fp->mem)
 132          nouveau_heap_free(&fp->mem);
 133
 134       fp->fp.flatshade = rast->flatshade;
 135
 136       /* Always smooth-shade in this mode, the shader will decide on its own
 137        * when to flat-shade.
 138        */
 139    } else if (!has_explicit_color) {
 140       hwflatshade = rast->flatshade;
 141
 142       /* No need to binary-patch the shader each time, make sure that it's set
 143        * up for the default behaviour.
 144        */
 145       fp->fp.flatshade = 0;
 146    }
 147
 148    if (hwflatshade != nvc0->state.flatshade) {
 149       nvc0->state.flatshade = hwflatshade;
 150       BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
 151       PUSH_DATA (push, hwflatshade ? NVC0_3D_SHADE_MODEL_FLAT :
 152                                      NVC0_3D_SHADE_MODEL_SMOOTH);
 153    }
 154
 155    if (fp->mem && !(nvc0->dirty_3d & NVC0_NEW_3D_FRAGPROG)) {
 156       return;
 157    }
 158
 159    if (!nvc0_program_validate(nvc0, fp))
 160          return;
 161    nvc0_program_update_context_state(nvc0, fp, 4);
 162
 163    if (fp->fp.early_z != nvc0->state.early_z_forced) {
 164       nvc0->state.early_z_forced = fp->fp.early_z;
 165       IMMED_NVC0(push, NVC0_3D(FORCE_EARLY_FRAGMENT_TESTS), fp->fp.early_z);
 166    }
 167
 168    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(5)), 2);
 169    PUSH_DATA (push, 0x51);
 170    PUSH_DATA (push, fp->code_base);
 171    BEGIN_NVC0(push, NVC0_3D(SP_GPR_ALLOC(5)), 1);
 172    PUSH_DATA (push, fp->num_gprs);
 173
 174    BEGIN_NVC0(push, SUBC_3D(0x0360), 2);
 175    PUSH_DATA (push, 0x20164010);
 176    PUSH_DATA (push, 0x20);
 177    BEGIN_NVC0(push, NVC0_3D(ZCULL_TEST_MASK), 1);
 178    PUSH_DATA (push, fp->flags[0]);
 179 }
 180
 181 void
 182 nvc0_tctlprog_validate(struct nvc0_context *nvc0)
 183 {
 184    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 185    struct nvc0_program *tp = nvc0->tctlprog;
 186
 187    if (tp && nvc0_program_validate(nvc0, tp)) {
 188       if (tp->tp.tess_mode != ~0) {
 189          BEGIN_NVC0(push, NVC0_3D(TESS_MODE), 1);
 190          PUSH_DATA (push, tp->tp.tess_mode);
 191       }
 192       BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 2);
 193       PUSH_DATA (push, 0x21);
 194       PUSH_DATA (push, tp->code_base);
 195       BEGIN_NVC0(push, NVC0_3D(SP_GPR_ALLOC(2)), 1);
 196       PUSH_DATA (push, tp->num_gprs);
 197    } else {
 198       tp = nvc0->tcp_empty;
 199       /* not a whole lot we can do to handle this failure */
 200       if (!nvc0_program_validate(nvc0, tp))
 201          assert(!"unable to validate empty tcp");
 202       BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 2);
 203       PUSH_DATA (push, 0x20);
 204       PUSH_DATA (push, tp->code_base);
 205    }
 206    nvc0_program_update_context_state(nvc0, tp, 1);
 207 }
 208
 209 void
 210 nvc0_tevlprog_validate(struct nvc0_context *nvc0)
 211 {
 212    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 213    struct nvc0_program *tp = nvc0->tevlprog;
 214
 215    if (tp && nvc0_program_validate(nvc0, tp)) {
 216       if (tp->tp.tess_mode != ~0) {
 217          BEGIN_NVC0(push, NVC0_3D(TESS_MODE), 1);
 218          PUSH_DATA (push, tp->tp.tess_mode);
 219       }
 220       BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
 221       PUSH_DATA (push, 0x31);
 222       BEGIN_NVC0(push, NVC0_3D(SP_START_ID(3)), 1);
 223       PUSH_DATA (push, tp->code_base);
 224       BEGIN_NVC0(push, NVC0_3D(SP_GPR_ALLOC(3)), 1);
 225       PUSH_DATA (push, tp->num_gprs);
 226    } else {
 227       BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
 228       PUSH_DATA (push, 0x30);
 229    }
 230    nvc0_program_update_context_state(nvc0, tp, 2);
 231 }
 232
 233 void
 234 nvc0_gmtyprog_validate(struct nvc0_context *nvc0)
 235 {
 236    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 237    struct nvc0_program *gp = nvc0->gmtyprog;
 238
 239    /* we allow GPs with no code for specifying stream output state only */
 240    if (gp && nvc0_program_validate(nvc0, gp) && gp->code_size) {
 241       const bool gp_selects_layer = !!(gp->hdr[13] & (1 << 9));
 242
 243       BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
 244       PUSH_DATA (push, 0x41);
 245       BEGIN_NVC0(push, NVC0_3D(SP_START_ID(4)), 1);
 246       PUSH_DATA (push, gp->code_base);
 247       BEGIN_NVC0(push, NVC0_3D(SP_GPR_ALLOC(4)), 1);
 248       PUSH_DATA (push, gp->num_gprs);
 249       BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
 250       PUSH_DATA (push, gp_selects_layer ? NVC0_3D_LAYER_USE_GP : 0);
 251    } else {
 252       IMMED_NVC0(push, NVC0_3D(LAYER), 0);
 253       BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
 254       PUSH_DATA (push, 0x40);
 255    }
 256    nvc0_program_update_context_state(nvc0, gp, 3);
 257 }
 258
 259 void
 260 nvc0_tfb_validate(struct nvc0_context *nvc0)
 261 {
 262    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 263    struct nvc0_transform_feedback_state *tfb;
 264    unsigned b;
 265
 266    if (nvc0->gmtyprog) tfb = nvc0->gmtyprog->tfb;
 267    else
 268    if (nvc0->tevlprog) tfb = nvc0->tevlprog->tfb;
 269    else
 270       tfb = nvc0->vertprog->tfb;
 271
 272    IMMED_NVC0(push, NVC0_3D(TFB_ENABLE), (tfb && nvc0->num_tfbbufs) ? 1 : 0);
 273
 274    if (tfb && tfb != nvc0->state.tfb) {
 275       for (b = 0; b < 4; ++b) {
 276          if (tfb->varying_count[b]) {
 277             unsigned n = (tfb->varying_count[b] + 3) / 4;
 278
 279             BEGIN_NVC0(push, NVC0_3D(TFB_STREAM(b)), 3);
 280             PUSH_DATA (push, tfb->stream[b]);
 281             PUSH_DATA (push, tfb->varying_count[b]);
 282             PUSH_DATA (push, tfb->stride[b]);
 283             BEGIN_NVC0(push, NVC0_3D(TFB_VARYING_LOCS(b, 0)), n);
 284             PUSH_DATAp(push, tfb->varying_index[b], n);
 285
 286             if (nvc0->tfbbuf[b])
 287                nvc0_so_target(nvc0->tfbbuf[b])->stride = tfb->stride[b];
 288          } else {
 289             IMMED_NVC0(push, NVC0_3D(TFB_VARYING_COUNT(b)), 0);
 290          }
 291       }
 292    }
 293    nvc0->state.tfb = tfb;
 294
 295    if (!(nvc0->dirty_3d & NVC0_NEW_3D_TFB_TARGETS))
 296       return;
 297    nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TFB);
 298
 299    for (b = 0; b < nvc0->num_tfbbufs; ++b) {
 300       struct nvc0_so_target *targ = nvc0_so_target(nvc0->tfbbuf[b]);
 301       struct nv04_resource *buf;
 302
 303       if (!targ) {
 304          IMMED_NVC0(push, NVC0_3D(TFB_BUFFER_ENABLE(b)), 0);
 305          continue;
 306       }
 307
 308       if (tfb)
 309          targ->stride = tfb->stride[b];
 310
 311       buf = nv04_resource(targ->pipe.buffer);
 312
 313       BCTX_REFN(nvc0->bufctx_3d, 3D_TFB, buf, WR);
 314
 315       if (!(nvc0->tfbbuf_dirty & (1 << b)))
 316          continue;
 317
 318       if (!targ->clean)
 319          nvc0_hw_query_fifo_wait(nvc0, nvc0_query(targ->pq));
 320       nouveau_pushbuf_space(push, 0, 0, 1);
 321       BEGIN_NVC0(push, NVC0_3D(TFB_BUFFER_ENABLE(b)), 5);
 322       PUSH_DATA (push, 1);
 323       PUSH_DATAh(push, buf->address + targ->pipe.buffer_offset);
 324       PUSH_DATA (push, buf->address + targ->pipe.buffer_offset);
 325       PUSH_DATA (push, targ->pipe.buffer_size);
 326       if (!targ->clean) {
 327          nvc0_hw_query_pushbuf_submit(push, nvc0_query(targ->pq), 0x4);
 328       } else {
 329          PUSH_DATA(push, 0); /* TFB_BUFFER_OFFSET */
 330          targ->clean = false;
 331       }
 332    }
 333    for (; b < 4; ++b)
 334       IMMED_NVC0(push, NVC0_3D(TFB_BUFFER_ENABLE(b)), 0);
 335 }