2 * Copyright 2010 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include "pipe/p_defines.h"
24 #include "util/u_helpers.h"
25 #include "util/u_inlines.h"
26 #include "util/u_transfer.h"
28 #include "tgsi/tgsi_parse.h"
30 #include "nvc0/nvc0_stateobj.h"
31 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nvc0_3d.xml.h"
34 #include "nv50/nv50_texture.xml.h"
36 #include "nouveau_gldefs.h"
38 static INLINE
uint32_t
39 nvc0_colormask(unsigned mask
)
43 if (mask
& PIPE_MASK_R
)
45 if (mask
& PIPE_MASK_G
)
47 if (mask
& PIPE_MASK_B
)
49 if (mask
& PIPE_MASK_A
)
55 #define NVC0_BLEND_FACTOR_CASE(a, b) \
56 case PIPE_BLENDFACTOR_##a: return NV50_3D_BLEND_FACTOR_##b
58 static INLINE
uint32_t
59 nvc0_blend_fac(unsigned factor
)
62 NVC0_BLEND_FACTOR_CASE(ONE
, ONE
);
63 NVC0_BLEND_FACTOR_CASE(SRC_COLOR
, SRC_COLOR
);
64 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA
, SRC_ALPHA
);
65 NVC0_BLEND_FACTOR_CASE(DST_ALPHA
, DST_ALPHA
);
66 NVC0_BLEND_FACTOR_CASE(DST_COLOR
, DST_COLOR
);
67 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE
, SRC_ALPHA_SATURATE
);
68 NVC0_BLEND_FACTOR_CASE(CONST_COLOR
, CONSTANT_COLOR
);
69 NVC0_BLEND_FACTOR_CASE(CONST_ALPHA
, CONSTANT_ALPHA
);
70 NVC0_BLEND_FACTOR_CASE(SRC1_COLOR
, SRC1_COLOR
);
71 NVC0_BLEND_FACTOR_CASE(SRC1_ALPHA
, SRC1_ALPHA
);
72 NVC0_BLEND_FACTOR_CASE(ZERO
, ZERO
);
73 NVC0_BLEND_FACTOR_CASE(INV_SRC_COLOR
, ONE_MINUS_SRC_COLOR
);
74 NVC0_BLEND_FACTOR_CASE(INV_SRC_ALPHA
, ONE_MINUS_SRC_ALPHA
);
75 NVC0_BLEND_FACTOR_CASE(INV_DST_ALPHA
, ONE_MINUS_DST_ALPHA
);
76 NVC0_BLEND_FACTOR_CASE(INV_DST_COLOR
, ONE_MINUS_DST_COLOR
);
77 NVC0_BLEND_FACTOR_CASE(INV_CONST_COLOR
, ONE_MINUS_CONSTANT_COLOR
);
78 NVC0_BLEND_FACTOR_CASE(INV_CONST_ALPHA
, ONE_MINUS_CONSTANT_ALPHA
);
79 NVC0_BLEND_FACTOR_CASE(INV_SRC1_COLOR
, ONE_MINUS_SRC1_COLOR
);
80 NVC0_BLEND_FACTOR_CASE(INV_SRC1_ALPHA
, ONE_MINUS_SRC1_ALPHA
);
82 return NV50_3D_BLEND_FACTOR_ZERO
;
87 nvc0_blend_state_create(struct pipe_context
*pipe
,
88 const struct pipe_blend_state
*cso
)
90 struct nvc0_blend_stateobj
*so
= CALLOC_STRUCT(nvc0_blend_stateobj
);
92 int r
; /* reference */
95 boolean indep_masks
= FALSE
;
96 boolean indep_funcs
= FALSE
;
100 /* check which states actually have differing values */
101 if (cso
->independent_blend_enable
) {
102 for (r
= 0; r
< 8 && !cso
->rt
[r
].blend_enable
; ++r
);
104 for (i
= r
+ 1; i
< 8; ++i
) {
105 if (!cso
->rt
[i
].blend_enable
)
108 if (cso
->rt
[i
].rgb_func
!= cso
->rt
[r
].rgb_func
||
109 cso
->rt
[i
].rgb_src_factor
!= cso
->rt
[r
].rgb_src_factor
||
110 cso
->rt
[i
].rgb_dst_factor
!= cso
->rt
[r
].rgb_dst_factor
||
111 cso
->rt
[i
].alpha_func
!= cso
->rt
[r
].alpha_func
||
112 cso
->rt
[i
].alpha_src_factor
!= cso
->rt
[r
].alpha_src_factor
||
113 cso
->rt
[i
].alpha_dst_factor
!= cso
->rt
[r
].alpha_dst_factor
) {
119 blend_en
|= (cso
->rt
[i
].blend_enable
? 1 : 0) << i
;
121 for (i
= 1; i
< 8; ++i
) {
122 if (cso
->rt
[i
].colormask
!= cso
->rt
[0].colormask
) {
129 if (cso
->rt
[0].blend_enable
)
133 if (cso
->logicop_enable
) {
134 SB_BEGIN_3D(so
, LOGIC_OP_ENABLE
, 2);
136 SB_DATA (so
, nvgl_logicop_func(cso
->logicop_func
));
138 SB_IMMED_3D(so
, MACRO_BLEND_ENABLES
, 0);
140 SB_IMMED_3D(so
, LOGIC_OP_ENABLE
, 0);
142 SB_IMMED_3D(so
, BLEND_INDEPENDENT
, indep_funcs
);
143 SB_IMMED_3D(so
, MACRO_BLEND_ENABLES
, blend_en
);
145 for (i
= 0; i
< 8; ++i
) {
146 if (cso
->rt
[i
].blend_enable
) {
147 SB_BEGIN_3D(so
, IBLEND_EQUATION_RGB(i
), 6);
148 SB_DATA (so
, nvgl_blend_eqn(cso
->rt
[i
].rgb_func
));
149 SB_DATA (so
, nvc0_blend_fac(cso
->rt
[i
].rgb_src_factor
));
150 SB_DATA (so
, nvc0_blend_fac(cso
->rt
[i
].rgb_dst_factor
));
151 SB_DATA (so
, nvgl_blend_eqn(cso
->rt
[i
].alpha_func
));
152 SB_DATA (so
, nvc0_blend_fac(cso
->rt
[i
].alpha_src_factor
));
153 SB_DATA (so
, nvc0_blend_fac(cso
->rt
[i
].alpha_dst_factor
));
158 SB_BEGIN_3D(so
, BLEND_EQUATION_RGB
, 5);
159 SB_DATA (so
, nvgl_blend_eqn(cso
->rt
[r
].rgb_func
));
160 SB_DATA (so
, nvc0_blend_fac(cso
->rt
[r
].rgb_src_factor
));
161 SB_DATA (so
, nvc0_blend_fac(cso
->rt
[r
].rgb_dst_factor
));
162 SB_DATA (so
, nvgl_blend_eqn(cso
->rt
[r
].alpha_func
));
163 SB_DATA (so
, nvc0_blend_fac(cso
->rt
[r
].alpha_src_factor
));
164 SB_BEGIN_3D(so
, BLEND_FUNC_DST_ALPHA
, 1);
165 SB_DATA (so
, nvc0_blend_fac(cso
->rt
[r
].alpha_dst_factor
));
168 SB_IMMED_3D(so
, COLOR_MASK_COMMON
, !indep_masks
);
170 SB_BEGIN_3D(so
, COLOR_MASK(0), 8);
171 for (i
= 0; i
< 8; ++i
)
172 SB_DATA(so
, nvc0_colormask(cso
->rt
[i
].colormask
));
174 SB_BEGIN_3D(so
, COLOR_MASK(0), 1);
175 SB_DATA (so
, nvc0_colormask(cso
->rt
[0].colormask
));
180 if (cso
->alpha_to_coverage
)
181 ms
|= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE
;
182 if (cso
->alpha_to_one
)
183 ms
|= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE
;
185 SB_BEGIN_3D(so
, MULTISAMPLE_CTRL
, 1);
188 assert(so
->size
<= (sizeof(so
->state
) / sizeof(so
->state
[0])));
193 nvc0_blend_state_bind(struct pipe_context
*pipe
, void *hwcso
)
195 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
198 nvc0
->dirty
|= NVC0_NEW_BLEND
;
202 nvc0_blend_state_delete(struct pipe_context
*pipe
, void *hwcso
)
207 /* NOTE: ignoring line_last_pixel, using FALSE (set on screen init) */
209 nvc0_rasterizer_state_create(struct pipe_context
*pipe
,
210 const struct pipe_rasterizer_state
*cso
)
212 struct nvc0_rasterizer_stateobj
*so
;
215 so
= CALLOC_STRUCT(nvc0_rasterizer_stateobj
);
220 /* Scissor enables are handled in scissor state, we will not want to
221 * always emit 16 commands, one for each scissor rectangle, here.
224 SB_BEGIN_3D(so
, SHADE_MODEL
, 1);
225 SB_DATA (so
, cso
->flatshade
? NVC0_3D_SHADE_MODEL_FLAT
:
226 NVC0_3D_SHADE_MODEL_SMOOTH
);
227 SB_IMMED_3D(so
, PROVOKING_VERTEX_LAST
, !cso
->flatshade_first
);
228 SB_IMMED_3D(so
, VERTEX_TWO_SIDE_ENABLE
, cso
->light_twoside
);
230 SB_IMMED_3D(so
, VERT_COLOR_CLAMP_EN
, cso
->clamp_vertex_color
);
231 SB_BEGIN_3D(so
, FRAG_COLOR_CLAMP_EN
, 1);
232 SB_DATA (so
, cso
->clamp_fragment_color
? 0x11111111 : 0x00000000);
234 SB_IMMED_3D(so
, MULTISAMPLE_ENABLE
, cso
->multisample
);
236 SB_IMMED_3D(so
, LINE_SMOOTH_ENABLE
, cso
->line_smooth
);
237 if (cso
->line_smooth
)
238 SB_BEGIN_3D(so
, LINE_WIDTH_SMOOTH
, 1);
240 SB_BEGIN_3D(so
, LINE_WIDTH_ALIASED
, 1);
241 SB_DATA (so
, fui(cso
->line_width
));
243 SB_IMMED_3D(so
, LINE_STIPPLE_ENABLE
, cso
->line_stipple_enable
);
244 if (cso
->line_stipple_enable
) {
245 SB_BEGIN_3D(so
, LINE_STIPPLE_PATTERN
, 1);
246 SB_DATA (so
, (cso
->line_stipple_pattern
<< 8) |
247 cso
->line_stipple_factor
);
251 SB_IMMED_3D(so
, VP_POINT_SIZE_EN
, cso
->point_size_per_vertex
);
252 if (!cso
->point_size_per_vertex
) {
253 SB_BEGIN_3D(so
, POINT_SIZE
, 1);
254 SB_DATA (so
, fui(cso
->point_size
));
257 reg
= (cso
->sprite_coord_mode
== PIPE_SPRITE_COORD_UPPER_LEFT
) ?
258 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT
:
259 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT
;
261 SB_BEGIN_3D(so
, POINT_COORD_REPLACE
, 1);
262 SB_DATA (so
, ((cso
->sprite_coord_enable
& 0xff) << 3) | reg
);
263 SB_IMMED_3D(so
, POINT_SPRITE_ENABLE
, cso
->point_quad_rasterization
);
264 SB_IMMED_3D(so
, POINT_SMOOTH_ENABLE
, cso
->point_smooth
);
266 SB_BEGIN_3D(so
, MACRO_POLYGON_MODE_FRONT
, 1);
267 SB_DATA (so
, nvgl_polygon_mode(cso
->fill_front
));
268 SB_BEGIN_3D(so
, MACRO_POLYGON_MODE_BACK
, 1);
269 SB_DATA (so
, nvgl_polygon_mode(cso
->fill_back
));
270 SB_IMMED_3D(so
, POLYGON_SMOOTH_ENABLE
, cso
->poly_smooth
);
272 SB_BEGIN_3D(so
, CULL_FACE_ENABLE
, 3);
273 SB_DATA (so
, cso
->cull_face
!= PIPE_FACE_NONE
);
274 SB_DATA (so
, cso
->front_ccw
? NVC0_3D_FRONT_FACE_CCW
:
275 NVC0_3D_FRONT_FACE_CW
);
276 switch (cso
->cull_face
) {
277 case PIPE_FACE_FRONT_AND_BACK
:
278 SB_DATA(so
, NVC0_3D_CULL_FACE_FRONT_AND_BACK
);
280 case PIPE_FACE_FRONT
:
281 SB_DATA(so
, NVC0_3D_CULL_FACE_FRONT
);
285 SB_DATA(so
, NVC0_3D_CULL_FACE_BACK
);
289 SB_IMMED_3D(so
, POLYGON_STIPPLE_ENABLE
, cso
->poly_stipple_enable
);
290 SB_BEGIN_3D(so
, POLYGON_OFFSET_POINT_ENABLE
, 3);
291 SB_DATA (so
, cso
->offset_point
);
292 SB_DATA (so
, cso
->offset_line
);
293 SB_DATA (so
, cso
->offset_tri
);
295 if (cso
->offset_point
|| cso
->offset_line
|| cso
->offset_tri
) {
296 SB_BEGIN_3D(so
, POLYGON_OFFSET_FACTOR
, 1);
297 SB_DATA (so
, fui(cso
->offset_scale
));
298 SB_BEGIN_3D(so
, POLYGON_OFFSET_UNITS
, 1);
299 SB_DATA (so
, fui(cso
->offset_units
* 2.0f
));
300 SB_BEGIN_3D(so
, POLYGON_OFFSET_CLAMP
, 1);
301 SB_DATA (so
, fui(cso
->offset_clamp
));
305 reg
= NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1
;
308 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1
|
309 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR
|
310 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR
|
311 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2
;
313 SB_BEGIN_3D(so
, VIEW_VOLUME_CLIP_CTRL
, 1);
316 SB_IMMED_3D(so
, DEPTH_CLIP_NEGATIVE_Z
, cso
->clip_halfz
);
318 assert(so
->size
<= (sizeof(so
->state
) / sizeof(so
->state
[0])));
323 nvc0_rasterizer_state_bind(struct pipe_context
*pipe
, void *hwcso
)
325 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
328 nvc0
->dirty
|= NVC0_NEW_RASTERIZER
;
332 nvc0_rasterizer_state_delete(struct pipe_context
*pipe
, void *hwcso
)
338 nvc0_zsa_state_create(struct pipe_context
*pipe
,
339 const struct pipe_depth_stencil_alpha_state
*cso
)
341 struct nvc0_zsa_stateobj
*so
= CALLOC_STRUCT(nvc0_zsa_stateobj
);
345 SB_IMMED_3D(so
, DEPTH_TEST_ENABLE
, cso
->depth
.enabled
);
346 if (cso
->depth
.enabled
) {
347 SB_IMMED_3D(so
, DEPTH_WRITE_ENABLE
, cso
->depth
.writemask
);
348 SB_BEGIN_3D(so
, DEPTH_TEST_FUNC
, 1);
349 SB_DATA (so
, nvgl_comparison_op(cso
->depth
.func
));
352 if (cso
->stencil
[0].enabled
) {
353 SB_BEGIN_3D(so
, STENCIL_ENABLE
, 5);
355 SB_DATA (so
, nvgl_stencil_op(cso
->stencil
[0].fail_op
));
356 SB_DATA (so
, nvgl_stencil_op(cso
->stencil
[0].zfail_op
));
357 SB_DATA (so
, nvgl_stencil_op(cso
->stencil
[0].zpass_op
));
358 SB_DATA (so
, nvgl_comparison_op(cso
->stencil
[0].func
));
359 SB_BEGIN_3D(so
, STENCIL_FRONT_FUNC_MASK
, 2);
360 SB_DATA (so
, cso
->stencil
[0].valuemask
);
361 SB_DATA (so
, cso
->stencil
[0].writemask
);
363 SB_IMMED_3D(so
, STENCIL_ENABLE
, 0);
366 if (cso
->stencil
[1].enabled
) {
367 assert(cso
->stencil
[0].enabled
);
368 SB_BEGIN_3D(so
, STENCIL_TWO_SIDE_ENABLE
, 5);
370 SB_DATA (so
, nvgl_stencil_op(cso
->stencil
[1].fail_op
));
371 SB_DATA (so
, nvgl_stencil_op(cso
->stencil
[1].zfail_op
));
372 SB_DATA (so
, nvgl_stencil_op(cso
->stencil
[1].zpass_op
));
373 SB_DATA (so
, nvgl_comparison_op(cso
->stencil
[1].func
));
374 SB_BEGIN_3D(so
, STENCIL_BACK_MASK
, 2);
375 SB_DATA (so
, cso
->stencil
[1].writemask
);
376 SB_DATA (so
, cso
->stencil
[1].valuemask
);
378 if (cso
->stencil
[0].enabled
) {
379 SB_IMMED_3D(so
, STENCIL_TWO_SIDE_ENABLE
, 0);
382 SB_IMMED_3D(so
, ALPHA_TEST_ENABLE
, cso
->alpha
.enabled
);
383 if (cso
->alpha
.enabled
) {
384 SB_BEGIN_3D(so
, ALPHA_TEST_REF
, 2);
385 SB_DATA (so
, fui(cso
->alpha
.ref_value
));
386 SB_DATA (so
, nvgl_comparison_op(cso
->alpha
.func
));
389 assert(so
->size
<= (sizeof(so
->state
) / sizeof(so
->state
[0])));
394 nvc0_zsa_state_bind(struct pipe_context
*pipe
, void *hwcso
)
396 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
399 nvc0
->dirty
|= NVC0_NEW_ZSA
;
403 nvc0_zsa_state_delete(struct pipe_context
*pipe
, void *hwcso
)
408 /* ====================== SAMPLERS AND TEXTURES ================================
411 #define NV50_TSC_WRAP_CASE(n) \
412 case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n
414 static INLINE
unsigned
415 nv50_tsc_wrap_mode(unsigned wrap
)
418 NV50_TSC_WRAP_CASE(REPEAT
);
419 NV50_TSC_WRAP_CASE(MIRROR_REPEAT
);
420 NV50_TSC_WRAP_CASE(CLAMP_TO_EDGE
);
421 NV50_TSC_WRAP_CASE(CLAMP_TO_BORDER
);
422 NV50_TSC_WRAP_CASE(CLAMP
);
423 NV50_TSC_WRAP_CASE(MIRROR_CLAMP_TO_EDGE
);
424 NV50_TSC_WRAP_CASE(MIRROR_CLAMP_TO_BORDER
);
425 NV50_TSC_WRAP_CASE(MIRROR_CLAMP
);
427 NOUVEAU_ERR("unknown wrap mode: %d\n", wrap
);
428 return NV50_TSC_WRAP_REPEAT
;
433 nvc0_sampler_state_delete(struct pipe_context
*pipe
, void *hwcso
)
437 for (s
= 0; s
< 5; ++s
)
438 for (i
= 0; i
< nvc0_context(pipe
)->num_samplers
[s
]; ++i
)
439 if (nvc0_context(pipe
)->samplers
[s
][i
] == hwcso
)
440 nvc0_context(pipe
)->samplers
[s
][i
] = NULL
;
442 nvc0_screen_tsc_free(nvc0_context(pipe
)->screen
, nv50_tsc_entry(hwcso
));
448 nvc0_stage_sampler_states_bind(struct nvc0_context
*nvc0
, int s
,
449 unsigned nr
, void **hwcso
)
453 for (i
= 0; i
< nr
; ++i
) {
454 struct nv50_tsc_entry
*old
= nvc0
->samplers
[s
][i
];
458 nvc0
->samplers_dirty
[s
] |= 1 << i
;
460 nvc0
->samplers
[s
][i
] = nv50_tsc_entry(hwcso
[i
]);
462 nvc0_screen_tsc_unlock(nvc0
->screen
, old
);
464 for (; i
< nvc0
->num_samplers
[s
]; ++i
) {
465 if (nvc0
->samplers
[s
][i
]) {
466 nvc0_screen_tsc_unlock(nvc0
->screen
, nvc0
->samplers
[s
][i
]);
467 nvc0
->samplers
[s
][i
] = NULL
;
471 nvc0
->num_samplers
[s
] = nr
;
473 nvc0
->dirty
|= NVC0_NEW_SAMPLERS
;
477 nvc0_stage_sampler_states_bind_range(struct nvc0_context
*nvc0
,
479 unsigned start
, unsigned nr
, void **cso
)
481 const unsigned end
= start
+ nr
;
486 for (i
= start
; i
< end
; ++i
) {
487 const unsigned p
= i
- start
;
490 if (cso
[p
] == nvc0
->samplers
[s
][i
])
492 nvc0
->samplers_dirty
[s
] |= 1 << i
;
494 if (nvc0
->samplers
[s
][i
])
495 nvc0_screen_tsc_unlock(nvc0
->screen
, nvc0
->samplers
[s
][i
]);
496 nvc0
->samplers
[s
][i
] = cso
[p
];
499 for (i
= start
; i
< end
; ++i
) {
500 if (nvc0
->samplers
[s
][i
]) {
501 nvc0_screen_tsc_unlock(nvc0
->screen
, nvc0
->samplers
[s
][i
]);
502 nvc0
->samplers
[s
][i
] = NULL
;
503 nvc0
->samplers_dirty
[s
] |= 1 << i
;
508 if (nvc0
->num_samplers
[s
] <= end
) {
509 if (last_valid
< 0) {
510 for (i
= start
; i
&& !nvc0
->samplers
[s
][i
- 1]; --i
);
511 nvc0
->num_samplers
[s
] = i
;
513 nvc0
->num_samplers
[s
] = last_valid
+ 1;
519 nvc0_bind_sampler_states(struct pipe_context
*pipe
, unsigned shader
,
520 unsigned start
, unsigned nr
, void **s
)
523 case PIPE_SHADER_VERTEX
:
525 nvc0_stage_sampler_states_bind(nvc0_context(pipe
), 0, nr
, s
);
527 case PIPE_SHADER_GEOMETRY
:
529 nvc0_stage_sampler_states_bind(nvc0_context(pipe
), 3, nr
, s
);
531 case PIPE_SHADER_FRAGMENT
:
533 nvc0_stage_sampler_states_bind(nvc0_context(pipe
), 4, nr
, s
);
535 case PIPE_SHADER_COMPUTE
:
536 nvc0_stage_sampler_states_bind_range(nvc0_context(pipe
), 5,
538 nvc0_context(pipe
)->dirty_cp
|= NVC0_NEW_CP_SAMPLERS
;
544 /* NOTE: only called when not referenced anywhere, won't be bound */
546 nvc0_sampler_view_destroy(struct pipe_context
*pipe
,
547 struct pipe_sampler_view
*view
)
549 pipe_resource_reference(&view
->texture
, NULL
);
551 nvc0_screen_tic_free(nvc0_context(pipe
)->screen
, nv50_tic_entry(view
));
553 FREE(nv50_tic_entry(view
));
557 nvc0_stage_set_sampler_views(struct nvc0_context
*nvc0
, int s
,
559 struct pipe_sampler_view
**views
)
563 for (i
= 0; i
< nr
; ++i
) {
564 struct nv50_tic_entry
*old
= nv50_tic_entry(nvc0
->textures
[s
][i
]);
566 if (views
[i
] == nvc0
->textures
[s
][i
])
568 nvc0
->textures_dirty
[s
] |= 1 << i
;
571 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_TEX(s
, i
));
572 nvc0_screen_tic_unlock(nvc0
->screen
, old
);
575 pipe_sampler_view_reference(&nvc0
->textures
[s
][i
], views
[i
]);
578 for (i
= nr
; i
< nvc0
->num_textures
[s
]; ++i
) {
579 struct nv50_tic_entry
*old
= nv50_tic_entry(nvc0
->textures
[s
][i
]);
581 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_TEX(s
, i
));
582 nvc0_screen_tic_unlock(nvc0
->screen
, old
);
583 pipe_sampler_view_reference(&nvc0
->textures
[s
][i
], NULL
);
587 nvc0
->num_textures
[s
] = nr
;
589 nvc0
->dirty
|= NVC0_NEW_TEXTURES
;
593 nvc0_stage_set_sampler_views_range(struct nvc0_context
*nvc0
, const unsigned s
,
594 unsigned start
, unsigned nr
,
595 struct pipe_sampler_view
**views
)
597 struct nouveau_bufctx
*bctx
= (s
== 5) ? nvc0
->bufctx_cp
: nvc0
->bufctx_3d
;
598 const unsigned end
= start
+ nr
;
599 const unsigned bin
= (s
== 5) ? NVC0_BIND_CP_TEX(0) : NVC0_BIND_TEX(s
, 0);
604 for (i
= start
; i
< end
; ++i
) {
605 const unsigned p
= i
- start
;
608 if (views
[p
] == nvc0
->textures
[s
][i
])
610 nvc0
->textures_dirty
[s
] |= 1 << i
;
612 if (nvc0
->textures
[s
][i
]) {
613 struct nv50_tic_entry
*old
= nv50_tic_entry(nvc0
->textures
[s
][i
]);
614 nouveau_bufctx_reset(bctx
, bin
+ i
);
615 nvc0_screen_tic_unlock(nvc0
->screen
, old
);
617 pipe_sampler_view_reference(&nvc0
->textures
[s
][i
], views
[p
]);
620 for (i
= start
; i
< end
; ++i
) {
621 struct nv50_tic_entry
*old
= nv50_tic_entry(nvc0
->textures
[s
][i
]);
624 nvc0
->textures_dirty
[s
] |= 1 << i
;
626 nvc0_screen_tic_unlock(nvc0
->screen
, old
);
627 pipe_sampler_view_reference(&nvc0
->textures
[s
][i
], NULL
);
628 nouveau_bufctx_reset(bctx
, bin
+ i
);
632 if (nvc0
->num_textures
[s
] <= end
) {
633 if (last_valid
< 0) {
634 for (i
= start
; i
&& !nvc0
->textures
[s
][i
- 1]; --i
);
635 nvc0
->num_textures
[s
] = i
;
637 nvc0
->num_textures
[s
] = last_valid
+ 1;
643 nvc0_set_sampler_views(struct pipe_context
*pipe
, unsigned shader
,
644 unsigned start
, unsigned nr
,
645 struct pipe_sampler_view
**views
)
649 case PIPE_SHADER_VERTEX
:
650 nvc0_stage_set_sampler_views(nvc0_context(pipe
), 0, nr
, views
);
652 case PIPE_SHADER_GEOMETRY
:
653 nvc0_stage_set_sampler_views(nvc0_context(pipe
), 3, nr
, views
);
655 case PIPE_SHADER_FRAGMENT
:
656 nvc0_stage_set_sampler_views(nvc0_context(pipe
), 4, nr
, views
);
658 case PIPE_SHADER_COMPUTE
:
659 nvc0_stage_set_sampler_views_range(nvc0_context(pipe
), 5,
661 nvc0_context(pipe
)->dirty_cp
|= NVC0_NEW_CP_TEXTURES
;
669 /* ============================= SHADERS =======================================
673 nvc0_sp_state_create(struct pipe_context
*pipe
,
674 const struct pipe_shader_state
*cso
, unsigned type
)
676 struct nvc0_program
*prog
;
678 prog
= CALLOC_STRUCT(nvc0_program
);
685 prog
->pipe
.tokens
= tgsi_dup_tokens(cso
->tokens
);
687 if (cso
->stream_output
.num_outputs
)
688 prog
->pipe
.stream_output
= cso
->stream_output
;
694 nvc0_sp_state_delete(struct pipe_context
*pipe
, void *hwcso
)
696 struct nvc0_program
*prog
= (struct nvc0_program
*)hwcso
;
698 nvc0_program_destroy(nvc0_context(pipe
), prog
);
700 FREE((void *)prog
->pipe
.tokens
);
705 nvc0_vp_state_create(struct pipe_context
*pipe
,
706 const struct pipe_shader_state
*cso
)
708 return nvc0_sp_state_create(pipe
, cso
, PIPE_SHADER_VERTEX
);
712 nvc0_vp_state_bind(struct pipe_context
*pipe
, void *hwcso
)
714 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
716 nvc0
->vertprog
= hwcso
;
717 nvc0
->dirty
|= NVC0_NEW_VERTPROG
;
721 nvc0_fp_state_create(struct pipe_context
*pipe
,
722 const struct pipe_shader_state
*cso
)
724 return nvc0_sp_state_create(pipe
, cso
, PIPE_SHADER_FRAGMENT
);
728 nvc0_fp_state_bind(struct pipe_context
*pipe
, void *hwcso
)
730 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
732 nvc0
->fragprog
= hwcso
;
733 nvc0
->dirty
|= NVC0_NEW_FRAGPROG
;
737 nvc0_gp_state_create(struct pipe_context
*pipe
,
738 const struct pipe_shader_state
*cso
)
740 return nvc0_sp_state_create(pipe
, cso
, PIPE_SHADER_GEOMETRY
);
744 nvc0_gp_state_bind(struct pipe_context
*pipe
, void *hwcso
)
746 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
748 nvc0
->gmtyprog
= hwcso
;
749 nvc0
->dirty
|= NVC0_NEW_GMTYPROG
;
753 nvc0_cp_state_create(struct pipe_context
*pipe
,
754 const struct pipe_compute_state
*cso
)
756 struct nvc0_program
*prog
;
758 prog
= CALLOC_STRUCT(nvc0_program
);
761 prog
->type
= PIPE_SHADER_COMPUTE
;
763 prog
->cp
.smem_size
= cso
->req_local_mem
;
764 prog
->cp
.lmem_size
= cso
->req_private_mem
;
765 prog
->parm_size
= cso
->req_input_mem
;
767 prog
->pipe
.tokens
= tgsi_dup_tokens((const struct tgsi_token
*)cso
->prog
);
773 nvc0_cp_state_bind(struct pipe_context
*pipe
, void *hwcso
)
775 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
777 nvc0
->compprog
= hwcso
;
778 nvc0
->dirty_cp
|= NVC0_NEW_CP_PROGRAM
;
782 nvc0_set_constant_buffer(struct pipe_context
*pipe
, uint shader
, uint index
,
783 struct pipe_constant_buffer
*cb
)
785 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
786 struct pipe_resource
*res
= cb
? cb
->buffer
: NULL
;
787 const unsigned s
= nvc0_shader_stage(shader
);
788 const unsigned i
= index
;
790 if (unlikely(shader
== PIPE_SHADER_COMPUTE
)) {
791 assert(!cb
|| !cb
->user_buffer
);
792 if (nvc0
->constbuf
[s
][i
].u
.buf
)
793 nouveau_bufctx_reset(nvc0
->bufctx_cp
, NVC0_BIND_CP_CB(i
));
795 nvc0
->dirty_cp
|= NVC0_NEW_CP_CONSTBUF
;
797 if (nvc0
->constbuf
[s
][i
].user
)
798 nvc0
->constbuf
[s
][i
].u
.buf
= NULL
;
800 if (nvc0
->constbuf
[s
][i
].u
.buf
)
801 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_CB(s
, i
));
803 nvc0
->dirty
|= NVC0_NEW_CONSTBUF
;
805 nvc0
->constbuf_dirty
[s
] |= 1 << i
;
807 pipe_resource_reference(&nvc0
->constbuf
[s
][i
].u
.buf
, res
);
809 nvc0
->constbuf
[s
][i
].user
= (cb
&& cb
->user_buffer
) ? TRUE
: FALSE
;
810 if (nvc0
->constbuf
[s
][i
].user
) {
811 nvc0
->constbuf
[s
][i
].u
.data
= cb
->user_buffer
;
812 nvc0
->constbuf
[s
][i
].size
= cb
->buffer_size
;
813 nvc0
->constbuf_valid
[s
] |= 1 << i
;
816 nvc0
->constbuf
[s
][i
].offset
= cb
->buffer_offset
;
817 nvc0
->constbuf
[s
][i
].size
= align(cb
->buffer_size
, 0x100);
818 nvc0
->constbuf_valid
[s
] |= 1 << i
;
821 nvc0
->constbuf_valid
[s
] &= ~(1 << i
);
825 /* =============================================================================
829 nvc0_set_blend_color(struct pipe_context
*pipe
,
830 const struct pipe_blend_color
*bcol
)
832 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
834 nvc0
->blend_colour
= *bcol
;
835 nvc0
->dirty
|= NVC0_NEW_BLEND_COLOUR
;
839 nvc0_set_stencil_ref(struct pipe_context
*pipe
,
840 const struct pipe_stencil_ref
*sr
)
842 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
844 nvc0
->stencil_ref
= *sr
;
845 nvc0
->dirty
|= NVC0_NEW_STENCIL_REF
;
849 nvc0_set_clip_state(struct pipe_context
*pipe
,
850 const struct pipe_clip_state
*clip
)
852 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
854 memcpy(nvc0
->clip
.ucp
, clip
->ucp
, sizeof(clip
->ucp
));
856 nvc0
->dirty
|= NVC0_NEW_CLIP
;
860 nvc0_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
862 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
864 nvc0
->sample_mask
= sample_mask
;
865 nvc0
->dirty
|= NVC0_NEW_SAMPLE_MASK
;
869 nvc0_set_min_samples(struct pipe_context
*pipe
, unsigned min_samples
)
871 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
873 if (nvc0
->min_samples
!= min_samples
) {
874 nvc0
->min_samples
= min_samples
;
875 nvc0
->dirty
|= NVC0_NEW_MIN_SAMPLES
;
880 nvc0_set_framebuffer_state(struct pipe_context
*pipe
,
881 const struct pipe_framebuffer_state
*fb
)
883 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
886 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_FB
);
888 for (i
= 0; i
< fb
->nr_cbufs
; ++i
)
889 pipe_surface_reference(&nvc0
->framebuffer
.cbufs
[i
], fb
->cbufs
[i
]);
890 for (; i
< nvc0
->framebuffer
.nr_cbufs
; ++i
)
891 pipe_surface_reference(&nvc0
->framebuffer
.cbufs
[i
], NULL
);
893 nvc0
->framebuffer
.nr_cbufs
= fb
->nr_cbufs
;
895 nvc0
->framebuffer
.width
= fb
->width
;
896 nvc0
->framebuffer
.height
= fb
->height
;
898 pipe_surface_reference(&nvc0
->framebuffer
.zsbuf
, fb
->zsbuf
);
900 nvc0
->dirty
|= NVC0_NEW_FRAMEBUFFER
;
904 nvc0_set_polygon_stipple(struct pipe_context
*pipe
,
905 const struct pipe_poly_stipple
*stipple
)
907 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
909 nvc0
->stipple
= *stipple
;
910 nvc0
->dirty
|= NVC0_NEW_STIPPLE
;
914 nvc0_set_scissor_states(struct pipe_context
*pipe
,
916 unsigned num_scissors
,
917 const struct pipe_scissor_state
*scissor
)
919 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
922 assert(start_slot
+ num_scissors
<= NVC0_MAX_VIEWPORTS
);
923 for (i
= 0; i
< num_scissors
; i
++) {
924 if (!memcmp(&nvc0
->scissors
[start_slot
+ i
], &scissor
[i
], sizeof(*scissor
)))
926 nvc0
->scissors
[start_slot
+ i
] = scissor
[i
];
927 nvc0
->scissors_dirty
|= 1 << (start_slot
+ i
);
928 nvc0
->dirty
|= NVC0_NEW_SCISSOR
;
933 nvc0_set_viewport_states(struct pipe_context
*pipe
,
935 unsigned num_viewports
,
936 const struct pipe_viewport_state
*vpt
)
938 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
941 assert(start_slot
+ num_viewports
<= NVC0_MAX_VIEWPORTS
);
942 for (i
= 0; i
< num_viewports
; i
++) {
943 if (!memcmp(&nvc0
->viewports
[start_slot
+ i
], &vpt
[i
], sizeof(*vpt
)))
945 nvc0
->viewports
[start_slot
+ i
] = vpt
[i
];
946 nvc0
->viewports_dirty
|= 1 << (start_slot
+ i
);
947 nvc0
->dirty
|= NVC0_NEW_VIEWPORT
;
953 nvc0_set_vertex_buffers(struct pipe_context
*pipe
,
954 unsigned start_slot
, unsigned count
,
955 const struct pipe_vertex_buffer
*vb
)
957 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
960 util_set_vertex_buffers_count(nvc0
->vtxbuf
, &nvc0
->num_vtxbufs
, vb
,
964 nvc0
->vbo_user
&= ~(((1ull << count
) - 1) << start_slot
);
965 nvc0
->constant_vbos
&= ~(((1ull << count
) - 1) << start_slot
);
969 for (i
= 0; i
< count
; ++i
) {
970 unsigned dst_index
= start_slot
+ i
;
972 if (vb
[i
].user_buffer
) {
973 nvc0
->vbo_user
|= 1 << dst_index
;
974 if (!vb
[i
].stride
&& nvc0
->screen
->eng3d
->oclass
< GM107_3D_CLASS
)
975 nvc0
->constant_vbos
|= 1 << dst_index
;
977 nvc0
->constant_vbos
&= ~(1 << dst_index
);
979 nvc0
->vbo_user
&= ~(1 << dst_index
);
980 nvc0
->constant_vbos
&= ~(1 << dst_index
);
984 nvc0
->dirty
|= NVC0_NEW_ARRAYS
;
985 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_VTX
);
989 nvc0_set_index_buffer(struct pipe_context
*pipe
,
990 const struct pipe_index_buffer
*ib
)
992 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
994 if (nvc0
->idxbuf
.buffer
)
995 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_IDX
);
998 pipe_resource_reference(&nvc0
->idxbuf
.buffer
, ib
->buffer
);
999 nvc0
->idxbuf
.index_size
= ib
->index_size
;
1001 nvc0
->idxbuf
.offset
= ib
->offset
;
1002 nvc0
->dirty
|= NVC0_NEW_IDXBUF
;
1004 nvc0
->idxbuf
.user_buffer
= ib
->user_buffer
;
1005 nvc0
->dirty
&= ~NVC0_NEW_IDXBUF
;
1008 nvc0
->dirty
&= ~NVC0_NEW_IDXBUF
;
1009 pipe_resource_reference(&nvc0
->idxbuf
.buffer
, NULL
);
1014 nvc0_vertex_state_bind(struct pipe_context
*pipe
, void *hwcso
)
1016 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
1018 nvc0
->vertex
= hwcso
;
1019 nvc0
->dirty
|= NVC0_NEW_VERTEX
;
1022 static struct pipe_stream_output_target
*
1023 nvc0_so_target_create(struct pipe_context
*pipe
,
1024 struct pipe_resource
*res
,
1025 unsigned offset
, unsigned size
)
1027 struct nv04_resource
*buf
= (struct nv04_resource
*)res
;
1028 struct nvc0_so_target
*targ
= MALLOC_STRUCT(nvc0_so_target
);
1032 targ
->pq
= pipe
->create_query(pipe
, NVC0_QUERY_TFB_BUFFER_OFFSET
, 0);
1039 targ
->pipe
.buffer_size
= size
;
1040 targ
->pipe
.buffer_offset
= offset
;
1041 targ
->pipe
.context
= pipe
;
1042 targ
->pipe
.buffer
= NULL
;
1043 pipe_resource_reference(&targ
->pipe
.buffer
, res
);
1044 pipe_reference_init(&targ
->pipe
.reference
, 1);
1046 assert(buf
->base
.target
== PIPE_BUFFER
);
1047 util_range_add(&buf
->valid_buffer_range
, offset
, offset
+ size
);
1053 nvc0_so_target_destroy(struct pipe_context
*pipe
,
1054 struct pipe_stream_output_target
*ptarg
)
1056 struct nvc0_so_target
*targ
= nvc0_so_target(ptarg
);
1057 pipe
->destroy_query(pipe
, targ
->pq
);
1058 pipe_resource_reference(&targ
->pipe
.buffer
, NULL
);
1063 nvc0_set_transform_feedback_targets(struct pipe_context
*pipe
,
1064 unsigned num_targets
,
1065 struct pipe_stream_output_target
**targets
,
1066 const unsigned *offsets
)
1068 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
1070 boolean serialize
= TRUE
;
1072 assert(num_targets
<= 4);
1074 for (i
= 0; i
< num_targets
; ++i
) {
1075 const boolean changed
= nvc0
->tfbbuf
[i
] != targets
[i
];
1076 const boolean append
= (offsets
[i
] == ((unsigned)-1));
1077 if (!changed
&& append
)
1079 nvc0
->tfbbuf_dirty
|= 1 << i
;
1081 if (nvc0
->tfbbuf
[i
] && changed
)
1082 nvc0_so_target_save_offset(pipe
, nvc0
->tfbbuf
[i
], i
, &serialize
);
1084 if (targets
[i
] && !append
)
1085 nvc0_so_target(targets
[i
])->clean
= TRUE
;
1087 pipe_so_target_reference(&nvc0
->tfbbuf
[i
], targets
[i
]);
1089 for (; i
< nvc0
->num_tfbbufs
; ++i
) {
1090 nvc0
->tfbbuf_dirty
|= 1 << i
;
1091 nvc0_so_target_save_offset(pipe
, nvc0
->tfbbuf
[i
], i
, &serialize
);
1092 pipe_so_target_reference(&nvc0
->tfbbuf
[i
], NULL
);
1094 nvc0
->num_tfbbufs
= num_targets
;
1096 if (nvc0
->tfbbuf_dirty
)
1097 nvc0
->dirty
|= NVC0_NEW_TFB_TARGETS
;
1101 nvc0_bind_surfaces_range(struct nvc0_context
*nvc0
, const unsigned t
,
1102 unsigned start
, unsigned nr
,
1103 struct pipe_surface
**psurfaces
)
1105 const unsigned end
= start
+ nr
;
1106 const unsigned mask
= ((1 << nr
) - 1) << start
;
1110 for (i
= start
; i
< end
; ++i
) {
1111 const unsigned p
= i
- start
;
1113 nvc0
->surfaces_valid
[t
] |= (1 << i
);
1115 nvc0
->surfaces_valid
[t
] &= ~(1 << i
);
1116 pipe_surface_reference(&nvc0
->surfaces
[t
][i
], psurfaces
[p
]);
1119 for (i
= start
; i
< end
; ++i
)
1120 pipe_surface_reference(&nvc0
->surfaces
[t
][i
], NULL
);
1121 nvc0
->surfaces_valid
[t
] &= ~mask
;
1123 nvc0
->surfaces_dirty
[t
] |= mask
;
1126 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_SUF
);
1128 nouveau_bufctx_reset(nvc0
->bufctx_cp
, NVC0_BIND_CP_SUF
);
1132 nvc0_set_compute_resources(struct pipe_context
*pipe
,
1133 unsigned start
, unsigned nr
,
1134 struct pipe_surface
**resources
)
1136 nvc0_bind_surfaces_range(nvc0_context(pipe
), 1, start
, nr
, resources
);
1138 nvc0_context(pipe
)->dirty_cp
|= NVC0_NEW_CP_SURFACES
;
1142 nvc0_set_shader_resources(struct pipe_context
*pipe
,
1143 unsigned start
, unsigned nr
,
1144 struct pipe_surface
**resources
)
1146 nvc0_bind_surfaces_range(nvc0_context(pipe
), 0, start
, nr
, resources
);
1148 nvc0_context(pipe
)->dirty
|= NVC0_NEW_SURFACES
;
1152 nvc0_set_global_handle(uint32_t *phandle
, struct pipe_resource
*res
)
1154 struct nv04_resource
*buf
= nv04_resource(res
);
1156 uint64_t limit
= (buf
->address
+ buf
->base
.width0
) - 1;
1157 if (limit
< (1ULL << 32)) {
1158 *phandle
= (uint32_t)buf
->address
;
1160 NOUVEAU_ERR("Cannot map into TGSI_RESOURCE_GLOBAL: "
1161 "resource not contained within 32-bit address space !\n");
1170 nvc0_set_global_bindings(struct pipe_context
*pipe
,
1171 unsigned start
, unsigned nr
,
1172 struct pipe_resource
**resources
,
1175 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
1176 struct pipe_resource
**ptr
;
1178 const unsigned end
= start
+ nr
;
1180 if (nvc0
->global_residents
.size
<= (end
* sizeof(struct pipe_resource
*))) {
1181 const unsigned old_size
= nvc0
->global_residents
.size
;
1182 const unsigned req_size
= end
* sizeof(struct pipe_resource
*);
1183 util_dynarray_resize(&nvc0
->global_residents
, req_size
);
1184 memset((uint8_t *)nvc0
->global_residents
.data
+ old_size
, 0,
1185 req_size
- old_size
);
1189 ptr
= util_dynarray_element(
1190 &nvc0
->global_residents
, struct pipe_resource
*, start
);
1191 for (i
= 0; i
< nr
; ++i
) {
1192 pipe_resource_reference(&ptr
[i
], resources
[i
]);
1193 nvc0_set_global_handle(handles
[i
], resources
[i
]);
1196 ptr
= util_dynarray_element(
1197 &nvc0
->global_residents
, struct pipe_resource
*, start
);
1198 for (i
= 0; i
< nr
; ++i
)
1199 pipe_resource_reference(&ptr
[i
], NULL
);
1202 nouveau_bufctx_reset(nvc0
->bufctx_cp
, NVC0_BIND_CP_GLOBAL
);
1204 nvc0
->dirty_cp
= NVC0_NEW_CP_GLOBALS
;
1208 nvc0_init_state_functions(struct nvc0_context
*nvc0
)
1210 struct pipe_context
*pipe
= &nvc0
->base
.pipe
;
1212 pipe
->create_blend_state
= nvc0_blend_state_create
;
1213 pipe
->bind_blend_state
= nvc0_blend_state_bind
;
1214 pipe
->delete_blend_state
= nvc0_blend_state_delete
;
1216 pipe
->create_rasterizer_state
= nvc0_rasterizer_state_create
;
1217 pipe
->bind_rasterizer_state
= nvc0_rasterizer_state_bind
;
1218 pipe
->delete_rasterizer_state
= nvc0_rasterizer_state_delete
;
1220 pipe
->create_depth_stencil_alpha_state
= nvc0_zsa_state_create
;
1221 pipe
->bind_depth_stencil_alpha_state
= nvc0_zsa_state_bind
;
1222 pipe
->delete_depth_stencil_alpha_state
= nvc0_zsa_state_delete
;
1224 pipe
->create_sampler_state
= nv50_sampler_state_create
;
1225 pipe
->delete_sampler_state
= nvc0_sampler_state_delete
;
1226 pipe
->bind_sampler_states
= nvc0_bind_sampler_states
;
1228 pipe
->create_sampler_view
= nvc0_create_sampler_view
;
1229 pipe
->sampler_view_destroy
= nvc0_sampler_view_destroy
;
1230 pipe
->set_sampler_views
= nvc0_set_sampler_views
;
1232 pipe
->create_vs_state
= nvc0_vp_state_create
;
1233 pipe
->create_fs_state
= nvc0_fp_state_create
;
1234 pipe
->create_gs_state
= nvc0_gp_state_create
;
1235 pipe
->bind_vs_state
= nvc0_vp_state_bind
;
1236 pipe
->bind_fs_state
= nvc0_fp_state_bind
;
1237 pipe
->bind_gs_state
= nvc0_gp_state_bind
;
1238 pipe
->delete_vs_state
= nvc0_sp_state_delete
;
1239 pipe
->delete_fs_state
= nvc0_sp_state_delete
;
1240 pipe
->delete_gs_state
= nvc0_sp_state_delete
;
1242 pipe
->create_compute_state
= nvc0_cp_state_create
;
1243 pipe
->bind_compute_state
= nvc0_cp_state_bind
;
1244 pipe
->delete_compute_state
= nvc0_sp_state_delete
;
1246 pipe
->set_blend_color
= nvc0_set_blend_color
;
1247 pipe
->set_stencil_ref
= nvc0_set_stencil_ref
;
1248 pipe
->set_clip_state
= nvc0_set_clip_state
;
1249 pipe
->set_sample_mask
= nvc0_set_sample_mask
;
1250 pipe
->set_min_samples
= nvc0_set_min_samples
;
1251 pipe
->set_constant_buffer
= nvc0_set_constant_buffer
;
1252 pipe
->set_framebuffer_state
= nvc0_set_framebuffer_state
;
1253 pipe
->set_polygon_stipple
= nvc0_set_polygon_stipple
;
1254 pipe
->set_scissor_states
= nvc0_set_scissor_states
;
1255 pipe
->set_viewport_states
= nvc0_set_viewport_states
;
1257 pipe
->create_vertex_elements_state
= nvc0_vertex_state_create
;
1258 pipe
->delete_vertex_elements_state
= nvc0_vertex_state_delete
;
1259 pipe
->bind_vertex_elements_state
= nvc0_vertex_state_bind
;
1261 pipe
->set_vertex_buffers
= nvc0_set_vertex_buffers
;
1262 pipe
->set_index_buffer
= nvc0_set_index_buffer
;
1264 pipe
->create_stream_output_target
= nvc0_so_target_create
;
1265 pipe
->stream_output_target_destroy
= nvc0_so_target_destroy
;
1266 pipe
->set_stream_output_targets
= nvc0_set_transform_feedback_targets
;
1268 pipe
->set_global_binding
= nvc0_set_global_bindings
;
1269 pipe
->set_compute_resources
= nvc0_set_compute_resources
;
1270 pipe
->set_shader_resources
= nvc0_set_shader_resources
;
1272 nvc0
->sample_mask
= ~0;
1273 nvc0
->min_samples
= 1;