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gallium: add a cap for VIEWPORT_SUBPIXEL_BITS (v2)
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_state_validate.c
1
2 #include "util/u_format.h"
3 #include "util/u_framebuffer.h"
4 #include "util/u_math.h"
5
6 #include "nvc0/nvc0_context.h"
7
8 #if 0
9 static void
10 nvc0_validate_zcull(struct nvc0_context *nvc0)
11 {
12 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
13 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
14 struct nv50_surface *sf = nv50_surface(fb->zsbuf);
15 struct nv50_miptree *mt = nv50_miptree(sf->base.texture);
16 struct nouveau_bo *bo = mt->base.bo;
17 uint32_t size;
18 uint32_t offset = align(mt->total_size, 1 << 17);
19 unsigned width, height;
20
21 assert(mt->base.base.depth0 == 1 && mt->base.base.array_size < 2);
22
23 size = mt->total_size * 2;
24
25 height = align(fb->height, 32);
26 width = fb->width % 224;
27 if (width)
28 width = fb->width + (224 - width);
29 else
30 width = fb->width;
31
32 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1);
33 PUSH_DATA (push, 0);
34 BEGIN_NVC0(push, NVC0_3D(ZCULL_ADDRESS_HIGH), 2);
35 PUSH_DATAh(push, bo->offset + offset);
36 PUSH_DATA (push, bo->offset + offset);
37 offset += 1 << 17;
38 BEGIN_NVC0(push, NVC0_3D(ZCULL_LIMIT_HIGH), 2);
39 PUSH_DATAh(push, bo->offset + offset);
40 PUSH_DATA (push, bo->offset + offset);
41 BEGIN_NVC0(push, SUBC_3D(0x07e0), 2);
42 PUSH_DATA (push, size);
43 PUSH_DATA (push, size >> 16);
44 BEGIN_NVC0(push, SUBC_3D(0x15c8), 1); /* bits 0x3 */
45 PUSH_DATA (push, 2);
46 BEGIN_NVC0(push, NVC0_3D(ZCULL_WIDTH), 4);
47 PUSH_DATA (push, width);
48 PUSH_DATA (push, height);
49 PUSH_DATA (push, 1);
50 PUSH_DATA (push, 0);
51 BEGIN_NVC0(push, NVC0_3D(ZCULL_WINDOW_OFFSET_X), 2);
52 PUSH_DATA (push, 0);
53 PUSH_DATA (push, 0);
54 BEGIN_NVC0(push, NVC0_3D(ZCULL_INVALIDATE), 1);
55 PUSH_DATA (push, 0);
56 }
57 #endif
58
59 static inline void
60 nvc0_fb_set_null_rt(struct nouveau_pushbuf *push, unsigned i, unsigned layers)
61 {
62 BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(i)), 9);
63 PUSH_DATA (push, 0);
64 PUSH_DATA (push, 0);
65 PUSH_DATA (push, 64); // width
66 PUSH_DATA (push, 0); // height
67 PUSH_DATA (push, 0); // format
68 PUSH_DATA (push, 0); // tile mode
69 PUSH_DATA (push, layers); // layers
70 PUSH_DATA (push, 0); // layer stride
71 PUSH_DATA (push, 0); // base layer
72 }
73
74 static void
75 nvc0_validate_fb(struct nvc0_context *nvc0)
76 {
77 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
78 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
79 struct nvc0_screen *screen = nvc0->screen;
80 unsigned i, ms;
81 unsigned ms_mode = NVC0_3D_MULTISAMPLE_MODE_MS1;
82 unsigned nr_cbufs = fb->nr_cbufs;
83 bool serialize = false;
84
85 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_FB);
86
87 BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
88 PUSH_DATA (push, fb->width << 16);
89 PUSH_DATA (push, fb->height << 16);
90
91 for (i = 0; i < fb->nr_cbufs; ++i) {
92 struct nv50_surface *sf;
93 struct nv04_resource *res;
94 struct nouveau_bo *bo;
95
96 if (!fb->cbufs[i]) {
97 nvc0_fb_set_null_rt(push, i, 0);
98 continue;
99 }
100
101 sf = nv50_surface(fb->cbufs[i]);
102 res = nv04_resource(sf->base.texture);
103 bo = res->bo;
104
105 BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(i)), 9);
106 PUSH_DATAh(push, res->address + sf->offset);
107 PUSH_DATA (push, res->address + sf->offset);
108 if (likely(nouveau_bo_memtype(bo))) {
109 struct nv50_miptree *mt = nv50_miptree(sf->base.texture);
110
111 assert(sf->base.texture->target != PIPE_BUFFER);
112
113 PUSH_DATA(push, sf->width);
114 PUSH_DATA(push, sf->height);
115 PUSH_DATA(push, nvc0_format_table[sf->base.format].rt);
116 PUSH_DATA(push, (mt->layout_3d << 16) |
117 mt->level[sf->base.u.tex.level].tile_mode);
118 PUSH_DATA(push, sf->base.u.tex.first_layer + sf->depth);
119 PUSH_DATA(push, mt->layer_stride >> 2);
120 PUSH_DATA(push, sf->base.u.tex.first_layer);
121
122 ms_mode = mt->ms_mode;
123 } else {
124 if (res->base.target == PIPE_BUFFER) {
125 PUSH_DATA(push, 262144);
126 PUSH_DATA(push, 1);
127 } else {
128 PUSH_DATA(push, nv50_miptree(sf->base.texture)->level[0].pitch);
129 PUSH_DATA(push, sf->height);
130 }
131 PUSH_DATA(push, nvc0_format_table[sf->base.format].rt);
132 PUSH_DATA(push, 1 << 12);
133 PUSH_DATA(push, 1);
134 PUSH_DATA(push, 0);
135 PUSH_DATA(push, 0);
136
137 nvc0_resource_fence(res, NOUVEAU_BO_WR);
138
139 assert(!fb->zsbuf);
140 }
141
142 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_READING)
143 serialize = true;
144 res->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
145 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING;
146
147 /* only register for writing, otherwise we'd always serialize here */
148 BCTX_REFN(nvc0->bufctx_3d, 3D_FB, res, WR);
149 }
150
151 if (fb->zsbuf) {
152 struct nv50_miptree *mt = nv50_miptree(fb->zsbuf->texture);
153 struct nv50_surface *sf = nv50_surface(fb->zsbuf);
154 int unk = mt->base.base.target == PIPE_TEXTURE_2D;
155
156 BEGIN_NVC0(push, NVC0_3D(ZETA_ADDRESS_HIGH), 5);
157 PUSH_DATAh(push, mt->base.address + sf->offset);
158 PUSH_DATA (push, mt->base.address + sf->offset);
159 PUSH_DATA (push, nvc0_format_table[fb->zsbuf->format].rt);
160 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
161 PUSH_DATA (push, mt->layer_stride >> 2);
162 BEGIN_NVC0(push, NVC0_3D(ZETA_ENABLE), 1);
163 PUSH_DATA (push, 1);
164 BEGIN_NVC0(push, NVC0_3D(ZETA_HORIZ), 3);
165 PUSH_DATA (push, sf->width);
166 PUSH_DATA (push, sf->height);
167 PUSH_DATA (push, (unk << 16) |
168 (sf->base.u.tex.first_layer + sf->depth));
169 BEGIN_NVC0(push, NVC0_3D(ZETA_BASE_LAYER), 1);
170 PUSH_DATA (push, sf->base.u.tex.first_layer);
171
172 ms_mode = mt->ms_mode;
173
174 if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING)
175 serialize = true;
176 mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
177 mt->base.status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING;
178
179 BCTX_REFN(nvc0->bufctx_3d, 3D_FB, &mt->base, WR);
180 } else {
181 BEGIN_NVC0(push, NVC0_3D(ZETA_ENABLE), 1);
182 PUSH_DATA (push, 0);
183 }
184
185 if (nr_cbufs == 0 && !fb->zsbuf) {
186 assert(util_is_power_of_two(fb->samples));
187 assert(fb->samples <= 8);
188
189 nvc0_fb_set_null_rt(push, 0, fb->layers);
190
191 if (fb->samples > 1)
192 ms_mode = ffs(fb->samples) - 1;
193 nr_cbufs = 1;
194 }
195
196 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
197 PUSH_DATA (push, (076543210 << 4) | nr_cbufs);
198 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), ms_mode);
199
200 ms = 1 << ms_mode;
201 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
202 PUSH_DATA (push, NVC0_CB_AUX_SIZE);
203 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(4));
204 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(4));
205 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * ms);
206 PUSH_DATA (push, NVC0_CB_AUX_SAMPLE_INFO);
207 for (i = 0; i < ms; i++) {
208 float xy[2];
209 nvc0->base.pipe.get_sample_position(&nvc0->base.pipe, ms, i, xy);
210 PUSH_DATAf(push, xy[0]);
211 PUSH_DATAf(push, xy[1]);
212 }
213
214 if (serialize)
215 IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
216
217 NOUVEAU_DRV_STAT(&nvc0->screen->base, gpu_serialize_count, serialize);
218 }
219
220 static void
221 nvc0_validate_blend_colour(struct nvc0_context *nvc0)
222 {
223 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
224
225 BEGIN_NVC0(push, NVC0_3D(BLEND_COLOR(0)), 4);
226 PUSH_DATAf(push, nvc0->blend_colour.color[0]);
227 PUSH_DATAf(push, nvc0->blend_colour.color[1]);
228 PUSH_DATAf(push, nvc0->blend_colour.color[2]);
229 PUSH_DATAf(push, nvc0->blend_colour.color[3]);
230 }
231
232 static void
233 nvc0_validate_stencil_ref(struct nvc0_context *nvc0)
234 {
235 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
236 const ubyte *ref = &nvc0->stencil_ref.ref_value[0];
237
238 IMMED_NVC0(push, NVC0_3D(STENCIL_FRONT_FUNC_REF), ref[0]);
239 IMMED_NVC0(push, NVC0_3D(STENCIL_BACK_FUNC_REF), ref[1]);
240 }
241
242 static void
243 nvc0_validate_stipple(struct nvc0_context *nvc0)
244 {
245 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
246 unsigned i;
247
248 BEGIN_NVC0(push, NVC0_3D(POLYGON_STIPPLE_PATTERN(0)), 32);
249 for (i = 0; i < 32; ++i)
250 PUSH_DATA(push, util_bswap32(nvc0->stipple.stipple[i]));
251 }
252
253 static void
254 nvc0_validate_scissor(struct nvc0_context *nvc0)
255 {
256 int i;
257 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
258
259 if (!(nvc0->dirty_3d & NVC0_NEW_3D_SCISSOR) &&
260 nvc0->rast->pipe.scissor == nvc0->state.scissor)
261 return;
262
263 if (nvc0->state.scissor != nvc0->rast->pipe.scissor)
264 nvc0->scissors_dirty = (1 << NVC0_MAX_VIEWPORTS) - 1;
265
266 nvc0->state.scissor = nvc0->rast->pipe.scissor;
267
268 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
269 struct pipe_scissor_state *s = &nvc0->scissors[i];
270 if (!(nvc0->scissors_dirty & (1 << i)))
271 continue;
272
273 BEGIN_NVC0(push, NVC0_3D(SCISSOR_HORIZ(i)), 2);
274 if (nvc0->rast->pipe.scissor) {
275 PUSH_DATA(push, (s->maxx << 16) | s->minx);
276 PUSH_DATA(push, (s->maxy << 16) | s->miny);
277 } else {
278 PUSH_DATA(push, (0xffff << 16) | 0);
279 PUSH_DATA(push, (0xffff << 16) | 0);
280 }
281 }
282 nvc0->scissors_dirty = 0;
283 }
284
285 static void
286 nvc0_validate_viewport(struct nvc0_context *nvc0)
287 {
288 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
289 int x, y, w, h, i;
290 float zmin, zmax;
291
292 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
293 struct pipe_viewport_state *vp = &nvc0->viewports[i];
294
295 if (!(nvc0->viewports_dirty & (1 << i)))
296 continue;
297
298 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSLATE_X(i)), 3);
299 PUSH_DATAf(push, vp->translate[0]);
300 PUSH_DATAf(push, vp->translate[1]);
301 PUSH_DATAf(push, vp->translate[2]);
302
303 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_SCALE_X(i)), 3);
304 PUSH_DATAf(push, vp->scale[0]);
305 PUSH_DATAf(push, vp->scale[1]);
306 PUSH_DATAf(push, vp->scale[2]);
307
308 /* now set the viewport rectangle to viewport dimensions for clipping */
309
310 x = util_iround(MAX2(0.0f, vp->translate[0] - fabsf(vp->scale[0])));
311 y = util_iround(MAX2(0.0f, vp->translate[1] - fabsf(vp->scale[1])));
312 w = util_iround(vp->translate[0] + fabsf(vp->scale[0])) - x;
313 h = util_iround(vp->translate[1] + fabsf(vp->scale[1])) - y;
314
315 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_HORIZ(i)), 2);
316 PUSH_DATA (push, (w << 16) | x);
317 PUSH_DATA (push, (h << 16) | y);
318
319 zmin = vp->translate[2] - fabsf(vp->scale[2]);
320 zmax = vp->translate[2] + fabsf(vp->scale[2]);
321
322 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
323 PUSH_DATAf(push, zmin);
324 PUSH_DATAf(push, zmax);
325 }
326 nvc0->viewports_dirty = 0;
327 }
328
329 static void
330 nvc0_validate_window_rects(struct nvc0_context *nvc0)
331 {
332 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
333 bool enable = nvc0->window_rect.rects > 0 || nvc0->window_rect.inclusive;
334 int i;
335
336 IMMED_NVC0(push, NVC0_3D(CLIP_RECTS_EN), enable);
337 if (!enable)
338 return;
339
340 IMMED_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), !nvc0->window_rect.inclusive);
341 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), NVC0_MAX_WINDOW_RECTANGLES * 2);
342 for (i = 0; i < nvc0->window_rect.rects; i++) {
343 struct pipe_scissor_state *s = &nvc0->window_rect.rect[i];
344 PUSH_DATA(push, (s->maxx << 16) | s->minx);
345 PUSH_DATA(push, (s->maxy << 16) | s->miny);
346 }
347 for (; i < NVC0_MAX_WINDOW_RECTANGLES; i++) {
348 PUSH_DATA(push, 0);
349 PUSH_DATA(push, 0);
350 }
351 }
352
353 static inline void
354 nvc0_upload_uclip_planes(struct nvc0_context *nvc0, unsigned s)
355 {
356 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
357 struct nvc0_screen *screen = nvc0->screen;
358
359 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
360 PUSH_DATA (push, NVC0_CB_AUX_SIZE);
361 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s));
362 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s));
363 BEGIN_1IC0(push, NVC0_3D(CB_POS), PIPE_MAX_CLIP_PLANES * 4 + 1);
364 PUSH_DATA (push, NVC0_CB_AUX_UCP_INFO);
365 PUSH_DATAp(push, &nvc0->clip.ucp[0][0], PIPE_MAX_CLIP_PLANES * 4);
366 }
367
368 static inline void
369 nvc0_check_program_ucps(struct nvc0_context *nvc0,
370 struct nvc0_program *vp, uint8_t mask)
371 {
372 const unsigned n = util_logbase2(mask) + 1;
373
374 if (vp->vp.num_ucps >= n)
375 return;
376 nvc0_program_destroy(nvc0, vp);
377
378 vp->vp.num_ucps = n;
379 if (likely(vp == nvc0->vertprog))
380 nvc0_vertprog_validate(nvc0);
381 else
382 if (likely(vp == nvc0->gmtyprog))
383 nvc0_gmtyprog_validate(nvc0);
384 else
385 nvc0_tevlprog_validate(nvc0);
386 }
387
388 static void
389 nvc0_validate_clip(struct nvc0_context *nvc0)
390 {
391 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
392 struct nvc0_program *vp;
393 unsigned stage;
394 uint8_t clip_enable = nvc0->rast->pipe.clip_plane_enable;
395
396 if (nvc0->gmtyprog) {
397 stage = 3;
398 vp = nvc0->gmtyprog;
399 } else
400 if (nvc0->tevlprog) {
401 stage = 2;
402 vp = nvc0->tevlprog;
403 } else {
404 stage = 0;
405 vp = nvc0->vertprog;
406 }
407
408 if (clip_enable && vp->vp.num_ucps < PIPE_MAX_CLIP_PLANES)
409 nvc0_check_program_ucps(nvc0, vp, clip_enable);
410
411 if (nvc0->dirty_3d & (NVC0_NEW_3D_CLIP | (NVC0_NEW_3D_VERTPROG << stage)))
412 if (vp->vp.num_ucps > 0 && vp->vp.num_ucps <= PIPE_MAX_CLIP_PLANES)
413 nvc0_upload_uclip_planes(nvc0, stage);
414
415 clip_enable &= vp->vp.clip_enable;
416 clip_enable |= vp->vp.cull_enable;
417
418 if (nvc0->state.clip_enable != clip_enable) {
419 nvc0->state.clip_enable = clip_enable;
420 IMMED_NVC0(push, NVC0_3D(CLIP_DISTANCE_ENABLE), clip_enable);
421 }
422 if (nvc0->state.clip_mode != vp->vp.clip_mode) {
423 nvc0->state.clip_mode = vp->vp.clip_mode;
424 BEGIN_NVC0(push, NVC0_3D(CLIP_DISTANCE_MODE), 1);
425 PUSH_DATA (push, vp->vp.clip_mode);
426 }
427 }
428
429 static void
430 nvc0_validate_blend(struct nvc0_context *nvc0)
431 {
432 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
433
434 PUSH_SPACE(push, nvc0->blend->size);
435 PUSH_DATAp(push, nvc0->blend->state, nvc0->blend->size);
436 }
437
438 static void
439 nvc0_validate_zsa(struct nvc0_context *nvc0)
440 {
441 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
442
443 PUSH_SPACE(push, nvc0->zsa->size);
444 PUSH_DATAp(push, nvc0->zsa->state, nvc0->zsa->size);
445 }
446
447 static void
448 nvc0_validate_rasterizer(struct nvc0_context *nvc0)
449 {
450 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
451
452 PUSH_SPACE(push, nvc0->rast->size);
453 PUSH_DATAp(push, nvc0->rast->state, nvc0->rast->size);
454 }
455
456 static void
457 nvc0_constbufs_validate(struct nvc0_context *nvc0)
458 {
459 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
460 unsigned s;
461
462 for (s = 0; s < 5; ++s) {
463 while (nvc0->constbuf_dirty[s]) {
464 int i = ffs(nvc0->constbuf_dirty[s]) - 1;
465 nvc0->constbuf_dirty[s] &= ~(1 << i);
466
467 if (nvc0->constbuf[s][i].user) {
468 struct nouveau_bo *bo = nvc0->screen->uniform_bo;
469 const unsigned base = NVC0_CB_USR_INFO(s);
470 const unsigned size = nvc0->constbuf[s][0].size;
471 assert(i == 0); /* we really only want OpenGL uniforms here */
472 assert(nvc0->constbuf[s][0].u.data);
473
474 if (nvc0->state.uniform_buffer_bound[s] < size) {
475 nvc0->state.uniform_buffer_bound[s] = align(size, 0x100);
476
477 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
478 PUSH_DATA (push, nvc0->state.uniform_buffer_bound[s]);
479 PUSH_DATAh(push, bo->offset + base);
480 PUSH_DATA (push, bo->offset + base);
481 BEGIN_NVC0(push, NVC0_3D(CB_BIND(s)), 1);
482 PUSH_DATA (push, (0 << 4) | 1);
483 }
484 nvc0_cb_bo_push(&nvc0->base, bo, NV_VRAM_DOMAIN(&nvc0->screen->base),
485 base, nvc0->state.uniform_buffer_bound[s],
486 0, (size + 3) / 4,
487 nvc0->constbuf[s][0].u.data);
488 } else {
489 struct nv04_resource *res =
490 nv04_resource(nvc0->constbuf[s][i].u.buf);
491 if (res) {
492 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
493 PUSH_DATA (push, nvc0->constbuf[s][i].size);
494 PUSH_DATAh(push, res->address + nvc0->constbuf[s][i].offset);
495 PUSH_DATA (push, res->address + nvc0->constbuf[s][i].offset);
496 BEGIN_NVC0(push, NVC0_3D(CB_BIND(s)), 1);
497 PUSH_DATA (push, (i << 4) | 1);
498
499 BCTX_REFN(nvc0->bufctx_3d, 3D_CB(s, i), res, RD);
500
501 nvc0->cb_dirty = 1; /* Force cache flush for UBO. */
502 res->cb_bindings[s] |= 1 << i;
503 } else {
504 BEGIN_NVC0(push, NVC0_3D(CB_BIND(s)), 1);
505 PUSH_DATA (push, (i << 4) | 0);
506 }
507 if (i == 0)
508 nvc0->state.uniform_buffer_bound[s] = 0;
509 }
510 }
511 }
512
513 if (nvc0->screen->base.class_3d < NVE4_3D_CLASS) {
514 /* Invalidate all COMPUTE constbufs because they are aliased with 3D. */
515 nvc0->dirty_cp |= NVC0_NEW_CP_CONSTBUF;
516 nvc0->constbuf_dirty[5] |= nvc0->constbuf_valid[5];
517 nvc0->state.uniform_buffer_bound[5] = 0;
518 }
519 }
520
521 static void
522 nvc0_validate_buffers(struct nvc0_context *nvc0)
523 {
524 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
525 struct nvc0_screen *screen = nvc0->screen;
526 int i, s;
527
528 for (s = 0; s < 5; s++) {
529 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
530 PUSH_DATA (push, NVC0_CB_AUX_SIZE);
531 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s));
532 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s));
533 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 4 * NVC0_MAX_BUFFERS);
534 PUSH_DATA (push, NVC0_CB_AUX_BUF_INFO(0));
535 for (i = 0; i < NVC0_MAX_BUFFERS; i++) {
536 if (nvc0->buffers[s][i].buffer) {
537 struct nv04_resource *res =
538 nv04_resource(nvc0->buffers[s][i].buffer);
539 PUSH_DATA (push, res->address + nvc0->buffers[s][i].buffer_offset);
540 PUSH_DATAh(push, res->address + nvc0->buffers[s][i].buffer_offset);
541 PUSH_DATA (push, nvc0->buffers[s][i].buffer_size);
542 PUSH_DATA (push, 0);
543 BCTX_REFN(nvc0->bufctx_3d, 3D_BUF, res, RDWR);
544 util_range_add(&res->valid_buffer_range,
545 nvc0->buffers[s][i].buffer_offset,
546 nvc0->buffers[s][i].buffer_size);
547 } else {
548 PUSH_DATA (push, 0);
549 PUSH_DATA (push, 0);
550 PUSH_DATA (push, 0);
551 PUSH_DATA (push, 0);
552 }
553 }
554 }
555
556 }
557
558 static void
559 nvc0_validate_sample_mask(struct nvc0_context *nvc0)
560 {
561 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
562
563 unsigned mask[4] =
564 {
565 nvc0->sample_mask & 0xffff,
566 nvc0->sample_mask & 0xffff,
567 nvc0->sample_mask & 0xffff,
568 nvc0->sample_mask & 0xffff
569 };
570
571 BEGIN_NVC0(push, NVC0_3D(MSAA_MASK(0)), 4);
572 PUSH_DATA (push, mask[0]);
573 PUSH_DATA (push, mask[1]);
574 PUSH_DATA (push, mask[2]);
575 PUSH_DATA (push, mask[3]);
576 }
577
578 static void
579 nvc0_validate_min_samples(struct nvc0_context *nvc0)
580 {
581 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
582 int samples;
583
584 samples = util_next_power_of_two(nvc0->min_samples);
585 if (samples > 1) {
586 // If we're using the incoming sample mask and doing sample shading, we
587 // have to do sample shading "to the max", otherwise there's no way to
588 // tell which sets of samples are covered by the current invocation.
589 if (nvc0->fragprog->fp.sample_mask_in)
590 samples = util_framebuffer_get_num_samples(&nvc0->framebuffer);
591 samples |= NVC0_3D_SAMPLE_SHADING_ENABLE;
592 }
593
594 IMMED_NVC0(push, NVC0_3D(SAMPLE_SHADING), samples);
595 }
596
597 static void
598 nvc0_validate_driverconst(struct nvc0_context *nvc0)
599 {
600 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
601 struct nvc0_screen *screen = nvc0->screen;
602 int i;
603
604 for (i = 0; i < 5; ++i) {
605 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
606 PUSH_DATA (push, NVC0_CB_AUX_SIZE);
607 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
608 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
609 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
610 PUSH_DATA (push, (15 << 4) | 1);
611 }
612
613 nvc0->dirty_cp |= NVC0_NEW_CP_DRIVERCONST;
614 }
615
616 static void
617 nvc0_validate_fp_zsa_rast(struct nvc0_context *nvc0)
618 {
619 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
620 bool rasterizer_discard;
621
622 if (nvc0->rast && nvc0->rast->pipe.rasterizer_discard) {
623 rasterizer_discard = true;
624 } else {
625 bool zs = nvc0->zsa &&
626 (nvc0->zsa->pipe.depth.enabled || nvc0->zsa->pipe.stencil[0].enabled);
627 rasterizer_discard = !zs &&
628 (!nvc0->fragprog || !nvc0->fragprog->hdr[18]);
629 }
630
631 if (rasterizer_discard != nvc0->state.rasterizer_discard) {
632 nvc0->state.rasterizer_discard = rasterizer_discard;
633 IMMED_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), !rasterizer_discard);
634 }
635 }
636
637 /* alpha test is disabled if there are no color RTs, so make sure we have at
638 * least one if alpha test is enabled. Note that this must run after
639 * nvc0_validate_fb, otherwise that will override the RT count setting.
640 */
641 static void
642 nvc0_validate_zsa_fb(struct nvc0_context *nvc0)
643 {
644 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
645
646 if (nvc0->zsa && nvc0->zsa->pipe.alpha.enabled &&
647 nvc0->framebuffer.zsbuf &&
648 nvc0->framebuffer.nr_cbufs == 0) {
649 nvc0_fb_set_null_rt(push, 0, 0);
650 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
651 PUSH_DATA (push, (076543210 << 4) | 1);
652 }
653 }
654
655 static void
656 nvc0_validate_blend_fb(struct nvc0_context *nvc0)
657 {
658 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
659 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
660 uint32_t ms = 0;
661
662 if ((!fb->nr_cbufs || !fb->cbufs[0] ||
663 !util_format_is_pure_integer(fb->cbufs[0]->format)) && nvc0->blend) {
664 if (nvc0->blend->pipe.alpha_to_coverage)
665 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE;
666 if (nvc0->blend->pipe.alpha_to_one)
667 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE;
668 }
669
670 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
671 PUSH_DATA (push, ms);
672 }
673
674 static void
675 nvc0_validate_rast_fb(struct nvc0_context *nvc0)
676 {
677 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
678 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
679 struct pipe_rasterizer_state *rast = &nvc0->rast->pipe;
680
681 if (!rast)
682 return;
683
684 if (rast->offset_units_unscaled) {
685 BEGIN_NVC0(push, NVC0_3D(POLYGON_OFFSET_UNITS), 1);
686 if (fb->zsbuf && fb->zsbuf->format == PIPE_FORMAT_Z16_UNORM)
687 PUSH_DATAf(push, rast->offset_units * (1 << 16));
688 else
689 PUSH_DATAf(push, rast->offset_units * (1 << 24));
690 }
691 }
692
693
694 static void
695 nvc0_validate_tess_state(struct nvc0_context *nvc0)
696 {
697 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
698
699 BEGIN_NVC0(push, NVC0_3D(TESS_LEVEL_OUTER(0)), 6);
700 PUSH_DATAp(push, nvc0->default_tess_outer, 4);
701 PUSH_DATAp(push, nvc0->default_tess_inner, 2);
702 }
703
704 static void
705 nvc0_switch_pipe_context(struct nvc0_context *ctx_to)
706 {
707 struct nvc0_context *ctx_from = ctx_to->screen->cur_ctx;
708 unsigned s;
709
710 if (ctx_from)
711 ctx_to->state = ctx_from->state;
712 else
713 ctx_to->state = ctx_to->screen->save_state;
714
715 ctx_to->dirty_3d = ~0;
716 ctx_to->dirty_cp = ~0;
717 ctx_to->viewports_dirty = ~0;
718 ctx_to->scissors_dirty = ~0;
719
720 for (s = 0; s < 6; ++s) {
721 ctx_to->samplers_dirty[s] = ~0;
722 ctx_to->textures_dirty[s] = ~0;
723 ctx_to->constbuf_dirty[s] = (1 << NVC0_MAX_PIPE_CONSTBUFS) - 1;
724 ctx_to->buffers_dirty[s] = ~0;
725 ctx_to->images_dirty[s] = ~0;
726 }
727
728 /* Reset tfb as the shader that owns it may have been deleted. */
729 ctx_to->state.tfb = NULL;
730
731 if (!ctx_to->vertex)
732 ctx_to->dirty_3d &= ~(NVC0_NEW_3D_VERTEX | NVC0_NEW_3D_ARRAYS);
733 if (!ctx_to->idxbuf.buffer)
734 ctx_to->dirty_3d &= ~NVC0_NEW_3D_IDXBUF;
735
736 if (!ctx_to->vertprog)
737 ctx_to->dirty_3d &= ~NVC0_NEW_3D_VERTPROG;
738 if (!ctx_to->fragprog)
739 ctx_to->dirty_3d &= ~NVC0_NEW_3D_FRAGPROG;
740
741 if (!ctx_to->blend)
742 ctx_to->dirty_3d &= ~NVC0_NEW_3D_BLEND;
743 if (!ctx_to->rast)
744 ctx_to->dirty_3d &= ~(NVC0_NEW_3D_RASTERIZER | NVC0_NEW_3D_SCISSOR);
745 if (!ctx_to->zsa)
746 ctx_to->dirty_3d &= ~NVC0_NEW_3D_ZSA;
747
748 ctx_to->screen->cur_ctx = ctx_to;
749 }
750
751 static struct nvc0_state_validate
752 validate_list_3d[] = {
753 { nvc0_validate_fb, NVC0_NEW_3D_FRAMEBUFFER },
754 { nvc0_validate_blend, NVC0_NEW_3D_BLEND },
755 { nvc0_validate_zsa, NVC0_NEW_3D_ZSA },
756 { nvc0_validate_sample_mask, NVC0_NEW_3D_SAMPLE_MASK },
757 { nvc0_validate_rasterizer, NVC0_NEW_3D_RASTERIZER },
758 { nvc0_validate_blend_colour, NVC0_NEW_3D_BLEND_COLOUR },
759 { nvc0_validate_stencil_ref, NVC0_NEW_3D_STENCIL_REF },
760 { nvc0_validate_stipple, NVC0_NEW_3D_STIPPLE },
761 { nvc0_validate_scissor, NVC0_NEW_3D_SCISSOR | NVC0_NEW_3D_RASTERIZER },
762 { nvc0_validate_viewport, NVC0_NEW_3D_VIEWPORT },
763 { nvc0_validate_window_rects, NVC0_NEW_3D_WINDOW_RECTS },
764 { nvc0_vertprog_validate, NVC0_NEW_3D_VERTPROG },
765 { nvc0_tctlprog_validate, NVC0_NEW_3D_TCTLPROG },
766 { nvc0_tevlprog_validate, NVC0_NEW_3D_TEVLPROG },
767 { nvc0_validate_tess_state, NVC0_NEW_3D_TESSFACTOR },
768 { nvc0_gmtyprog_validate, NVC0_NEW_3D_GMTYPROG },
769 { nvc0_validate_min_samples, NVC0_NEW_3D_MIN_SAMPLES |
770 NVC0_NEW_3D_FRAGPROG |
771 NVC0_NEW_3D_FRAMEBUFFER },
772 { nvc0_fragprog_validate, NVC0_NEW_3D_FRAGPROG | NVC0_NEW_3D_RASTERIZER },
773 { nvc0_validate_fp_zsa_rast, NVC0_NEW_3D_FRAGPROG | NVC0_NEW_3D_ZSA |
774 NVC0_NEW_3D_RASTERIZER },
775 { nvc0_validate_zsa_fb, NVC0_NEW_3D_ZSA | NVC0_NEW_3D_FRAMEBUFFER },
776 { nvc0_validate_blend_fb, NVC0_NEW_3D_BLEND | NVC0_NEW_3D_FRAMEBUFFER },
777 { nvc0_validate_rast_fb, NVC0_NEW_3D_RASTERIZER | NVC0_NEW_3D_FRAMEBUFFER },
778 { nvc0_validate_clip, NVC0_NEW_3D_CLIP | NVC0_NEW_3D_RASTERIZER |
779 NVC0_NEW_3D_VERTPROG |
780 NVC0_NEW_3D_TEVLPROG |
781 NVC0_NEW_3D_GMTYPROG },
782 { nvc0_constbufs_validate, NVC0_NEW_3D_CONSTBUF },
783 { nvc0_validate_textures, NVC0_NEW_3D_TEXTURES },
784 { nvc0_validate_samplers, NVC0_NEW_3D_SAMPLERS },
785 { nve4_set_tex_handles, NVC0_NEW_3D_TEXTURES | NVC0_NEW_3D_SAMPLERS },
786 { nvc0_vertex_arrays_validate, NVC0_NEW_3D_VERTEX | NVC0_NEW_3D_ARRAYS },
787 { nvc0_validate_surfaces, NVC0_NEW_3D_SURFACES },
788 { nvc0_validate_buffers, NVC0_NEW_3D_BUFFERS },
789 { nvc0_idxbuf_validate, NVC0_NEW_3D_IDXBUF },
790 { nvc0_tfb_validate, NVC0_NEW_3D_TFB_TARGETS | NVC0_NEW_3D_GMTYPROG },
791 { nvc0_validate_driverconst, NVC0_NEW_3D_DRIVERCONST },
792 };
793
794 bool
795 nvc0_state_validate(struct nvc0_context *nvc0, uint32_t mask,
796 struct nvc0_state_validate *validate_list, int size,
797 uint32_t *dirty, struct nouveau_bufctx *bufctx)
798 {
799 uint32_t state_mask;
800 int ret;
801 unsigned i;
802
803 if (nvc0->screen->cur_ctx != nvc0)
804 nvc0_switch_pipe_context(nvc0);
805
806 state_mask = *dirty & mask;
807
808 if (state_mask) {
809 for (i = 0; i < size; ++i) {
810 struct nvc0_state_validate *validate = &validate_list[i];
811
812 if (state_mask & validate->states)
813 validate->func(nvc0);
814 }
815 *dirty &= ~state_mask;
816
817 nvc0_bufctx_fence(nvc0, bufctx, false);
818 }
819
820 nouveau_pushbuf_bufctx(nvc0->base.pushbuf, bufctx);
821 ret = nouveau_pushbuf_validate(nvc0->base.pushbuf);
822
823 return !ret;
824 }
825
826 bool
827 nvc0_state_validate_3d(struct nvc0_context *nvc0, uint32_t mask)
828 {
829 bool ret;
830
831 ret = nvc0_state_validate(nvc0, mask, validate_list_3d,
832 ARRAY_SIZE(validate_list_3d), &nvc0->dirty_3d,
833 nvc0->bufctx_3d);
834
835 if (unlikely(nvc0->state.flushed)) {
836 nvc0->state.flushed = false;
837 nvc0_bufctx_fence(nvc0, nvc0->bufctx_3d, true);
838 }
839 return ret;
840 }