projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
nvc0: add support for VOTE tgsi opcodes
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_state_validate.c
1
2 #include "util/u_format.h"
3 #include "util/u_framebuffer.h"
4 #include "util/u_math.h"
5
6 #include "nvc0/nvc0_context.h"
7
8 #if 0
9 static void
10 nvc0_validate_zcull(struct nvc0_context *nvc0)
11 {
12 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
13 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
14 struct nv50_surface *sf = nv50_surface(fb->zsbuf);
15 struct nv50_miptree *mt = nv50_miptree(sf->base.texture);
16 struct nouveau_bo *bo = mt->base.bo;
17 uint32_t size;
18 uint32_t offset = align(mt->total_size, 1 << 17);
19 unsigned width, height;
20
21 assert(mt->base.base.depth0 == 1 && mt->base.base.array_size < 2);
22
23 size = mt->total_size * 2;
24
25 height = align(fb->height, 32);
26 width = fb->width % 224;
27 if (width)
28 width = fb->width + (224 - width);
29 else
30 width = fb->width;
31
32 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1);
33 PUSH_DATA (push, 0);
34 BEGIN_NVC0(push, NVC0_3D(ZCULL_ADDRESS_HIGH), 2);
35 PUSH_DATAh(push, bo->offset + offset);
36 PUSH_DATA (push, bo->offset + offset);
37 offset += 1 << 17;
38 BEGIN_NVC0(push, NVC0_3D(ZCULL_LIMIT_HIGH), 2);
39 PUSH_DATAh(push, bo->offset + offset);
40 PUSH_DATA (push, bo->offset + offset);
41 BEGIN_NVC0(push, SUBC_3D(0x07e0), 2);
42 PUSH_DATA (push, size);
43 PUSH_DATA (push, size >> 16);
44 BEGIN_NVC0(push, SUBC_3D(0x15c8), 1); /* bits 0x3 */
45 PUSH_DATA (push, 2);
46 BEGIN_NVC0(push, NVC0_3D(ZCULL_WIDTH), 4);
47 PUSH_DATA (push, width);
48 PUSH_DATA (push, height);
49 PUSH_DATA (push, 1);
50 PUSH_DATA (push, 0);
51 BEGIN_NVC0(push, NVC0_3D(ZCULL_WINDOW_OFFSET_X), 2);
52 PUSH_DATA (push, 0);
53 PUSH_DATA (push, 0);
54 BEGIN_NVC0(push, NVC0_3D(ZCULL_INVALIDATE), 1);
55 PUSH_DATA (push, 0);
56 }
57 #endif
58
59 static inline void
60 nvc0_fb_set_null_rt(struct nouveau_pushbuf *push, unsigned i, unsigned layers)
61 {
62 BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(i)), 9);
63 PUSH_DATA (push, 0);
64 PUSH_DATA (push, 0);
65 PUSH_DATA (push, 64); // width
66 PUSH_DATA (push, 0); // height
67 PUSH_DATA (push, 0); // format
68 PUSH_DATA (push, 0); // tile mode
69 PUSH_DATA (push, layers); // layers
70 PUSH_DATA (push, 0); // layer stride
71 PUSH_DATA (push, 0); // base layer
72 }
73
74 static void
75 nvc0_validate_fb(struct nvc0_context *nvc0)
76 {
77 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
78 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
79 struct nvc0_screen *screen = nvc0->screen;
80 unsigned i, ms;
81 unsigned ms_mode = NVC0_3D_MULTISAMPLE_MODE_MS1;
82 unsigned nr_cbufs = fb->nr_cbufs;
83 bool serialize = false;
84
85 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_FB);
86
87 BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
88 PUSH_DATA (push, fb->width << 16);
89 PUSH_DATA (push, fb->height << 16);
90
91 for (i = 0; i < fb->nr_cbufs; ++i) {
92 struct nv50_surface *sf;
93 struct nv04_resource *res;
94 struct nouveau_bo *bo;
95
96 if (!fb->cbufs[i]) {
97 nvc0_fb_set_null_rt(push, i, 0);
98 continue;
99 }
100
101 sf = nv50_surface(fb->cbufs[i]);
102 res = nv04_resource(sf->base.texture);
103 bo = res->bo;
104
105 BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(i)), 9);
106 PUSH_DATAh(push, res->address + sf->offset);
107 PUSH_DATA (push, res->address + sf->offset);
108 if (likely(nouveau_bo_memtype(bo))) {
109 struct nv50_miptree *mt = nv50_miptree(sf->base.texture);
110
111 assert(sf->base.texture->target != PIPE_BUFFER);
112
113 PUSH_DATA(push, sf->width);
114 PUSH_DATA(push, sf->height);
115 PUSH_DATA(push, nvc0_format_table[sf->base.format].rt);
116 PUSH_DATA(push, (mt->layout_3d << 16) |
117 mt->level[sf->base.u.tex.level].tile_mode);
118 PUSH_DATA(push, sf->base.u.tex.first_layer + sf->depth);
119 PUSH_DATA(push, mt->layer_stride >> 2);
120 PUSH_DATA(push, sf->base.u.tex.first_layer);
121
122 ms_mode = mt->ms_mode;
123 } else {
124 if (res->base.target == PIPE_BUFFER) {
125 PUSH_DATA(push, 262144);
126 PUSH_DATA(push, 1);
127 } else {
128 PUSH_DATA(push, nv50_miptree(sf->base.texture)->level[0].pitch);
129 PUSH_DATA(push, sf->height);
130 }
131 PUSH_DATA(push, nvc0_format_table[sf->base.format].rt);
132 PUSH_DATA(push, 1 << 12);
133 PUSH_DATA(push, 1);
134 PUSH_DATA(push, 0);
135 PUSH_DATA(push, 0);
136
137 nvc0_resource_fence(res, NOUVEAU_BO_WR);
138
139 assert(!fb->zsbuf);
140 }
141
142 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_READING)
143 serialize = true;
144 res->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
145 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING;
146
147 /* only register for writing, otherwise we'd always serialize here */
148 BCTX_REFN(nvc0->bufctx_3d, 3D_FB, res, WR);
149 }
150
151 if (fb->zsbuf) {
152 struct nv50_miptree *mt = nv50_miptree(fb->zsbuf->texture);
153 struct nv50_surface *sf = nv50_surface(fb->zsbuf);
154 int unk = mt->base.base.target == PIPE_TEXTURE_2D;
155
156 BEGIN_NVC0(push, NVC0_3D(ZETA_ADDRESS_HIGH), 5);
157 PUSH_DATAh(push, mt->base.address + sf->offset);
158 PUSH_DATA (push, mt->base.address + sf->offset);
159 PUSH_DATA (push, nvc0_format_table[fb->zsbuf->format].rt);
160 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
161 PUSH_DATA (push, mt->layer_stride >> 2);
162 BEGIN_NVC0(push, NVC0_3D(ZETA_ENABLE), 1);
163 PUSH_DATA (push, 1);
164 BEGIN_NVC0(push, NVC0_3D(ZETA_HORIZ), 3);
165 PUSH_DATA (push, sf->width);
166 PUSH_DATA (push, sf->height);
167 PUSH_DATA (push, (unk << 16) |
168 (sf->base.u.tex.first_layer + sf->depth));
169 BEGIN_NVC0(push, NVC0_3D(ZETA_BASE_LAYER), 1);
170 PUSH_DATA (push, sf->base.u.tex.first_layer);
171
172 ms_mode = mt->ms_mode;
173
174 if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING)
175 serialize = true;
176 mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
177 mt->base.status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING;
178
179 BCTX_REFN(nvc0->bufctx_3d, 3D_FB, &mt->base, WR);
180 } else {
181 BEGIN_NVC0(push, NVC0_3D(ZETA_ENABLE), 1);
182 PUSH_DATA (push, 0);
183 }
184
185 if (nr_cbufs == 0 && !fb->zsbuf) {
186 assert(util_is_power_of_two(fb->samples));
187 assert(fb->samples <= 8);
188
189 nvc0_fb_set_null_rt(push, 0, fb->layers);
190
191 if (fb->samples > 1)
192 ms_mode = ffs(fb->samples) - 1;
193 nr_cbufs = 1;
194 }
195
196 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
197 PUSH_DATA (push, (076543210 << 4) | nr_cbufs);
198 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), ms_mode);
199
200 ms = 1 << ms_mode;
201 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
202 PUSH_DATA (push, 2048);
203 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(4));
204 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(4));
205 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * ms);
206 PUSH_DATA (push, NVC0_CB_AUX_SAMPLE_INFO);
207 for (i = 0; i < ms; i++) {
208 float xy[2];
209 nvc0->base.pipe.get_sample_position(&nvc0->base.pipe, ms, i, xy);
210 PUSH_DATAf(push, xy[0]);
211 PUSH_DATAf(push, xy[1]);
212 }
213
214 if (serialize)
215 IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
216
217 NOUVEAU_DRV_STAT(&nvc0->screen->base, gpu_serialize_count, serialize);
218 }
219
220 static void
221 nvc0_validate_blend_colour(struct nvc0_context *nvc0)
222 {
223 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
224
225 BEGIN_NVC0(push, NVC0_3D(BLEND_COLOR(0)), 4);
226 PUSH_DATAf(push, nvc0->blend_colour.color[0]);
227 PUSH_DATAf(push, nvc0->blend_colour.color[1]);
228 PUSH_DATAf(push, nvc0->blend_colour.color[2]);
229 PUSH_DATAf(push, nvc0->blend_colour.color[3]);
230 }
231
232 static void
233 nvc0_validate_stencil_ref(struct nvc0_context *nvc0)
234 {
235 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
236 const ubyte *ref = &nvc0->stencil_ref.ref_value[0];
237
238 IMMED_NVC0(push, NVC0_3D(STENCIL_FRONT_FUNC_REF), ref[0]);
239 IMMED_NVC0(push, NVC0_3D(STENCIL_BACK_FUNC_REF), ref[1]);
240 }
241
242 static void
243 nvc0_validate_stipple(struct nvc0_context *nvc0)
244 {
245 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
246 unsigned i;
247
248 BEGIN_NVC0(push, NVC0_3D(POLYGON_STIPPLE_PATTERN(0)), 32);
249 for (i = 0; i < 32; ++i)
250 PUSH_DATA(push, util_bswap32(nvc0->stipple.stipple[i]));
251 }
252
253 static void
254 nvc0_validate_scissor(struct nvc0_context *nvc0)
255 {
256 int i;
257 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
258
259 if (!(nvc0->dirty_3d & NVC0_NEW_3D_SCISSOR) &&
260 nvc0->rast->pipe.scissor == nvc0->state.scissor)
261 return;
262
263 if (nvc0->state.scissor != nvc0->rast->pipe.scissor)
264 nvc0->scissors_dirty = (1 << NVC0_MAX_VIEWPORTS) - 1;
265
266 nvc0->state.scissor = nvc0->rast->pipe.scissor;
267
268 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
269 struct pipe_scissor_state *s = &nvc0->scissors[i];
270 if (!(nvc0->scissors_dirty & (1 << i)))
271 continue;
272
273 BEGIN_NVC0(push, NVC0_3D(SCISSOR_HORIZ(i)), 2);
274 if (nvc0->rast->pipe.scissor) {
275 PUSH_DATA(push, (s->maxx << 16) | s->minx);
276 PUSH_DATA(push, (s->maxy << 16) | s->miny);
277 } else {
278 PUSH_DATA(push, (0xffff << 16) | 0);
279 PUSH_DATA(push, (0xffff << 16) | 0);
280 }
281 }
282 nvc0->scissors_dirty = 0;
283 }
284
285 static void
286 nvc0_validate_viewport(struct nvc0_context *nvc0)
287 {
288 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
289 int x, y, w, h, i;
290 float zmin, zmax;
291
292 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
293 struct pipe_viewport_state *vp = &nvc0->viewports[i];
294
295 if (!(nvc0->viewports_dirty & (1 << i)))
296 continue;
297
298 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSLATE_X(i)), 3);
299 PUSH_DATAf(push, vp->translate[0]);
300 PUSH_DATAf(push, vp->translate[1]);
301 PUSH_DATAf(push, vp->translate[2]);
302
303 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_SCALE_X(i)), 3);
304 PUSH_DATAf(push, vp->scale[0]);
305 PUSH_DATAf(push, vp->scale[1]);
306 PUSH_DATAf(push, vp->scale[2]);
307
308 /* now set the viewport rectangle to viewport dimensions for clipping */
309
310 x = util_iround(MAX2(0.0f, vp->translate[0] - fabsf(vp->scale[0])));
311 y = util_iround(MAX2(0.0f, vp->translate[1] - fabsf(vp->scale[1])));
312 w = util_iround(vp->translate[0] + fabsf(vp->scale[0])) - x;
313 h = util_iround(vp->translate[1] + fabsf(vp->scale[1])) - y;
314
315 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_HORIZ(i)), 2);
316 PUSH_DATA (push, (w << 16) | x);
317 PUSH_DATA (push, (h << 16) | y);
318
319 zmin = vp->translate[2] - fabsf(vp->scale[2]);
320 zmax = vp->translate[2] + fabsf(vp->scale[2]);
321
322 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
323 PUSH_DATAf(push, zmin);
324 PUSH_DATAf(push, zmax);
325 }
326 nvc0->viewports_dirty = 0;
327 }
328
329 static inline void
330 nvc0_upload_uclip_planes(struct nvc0_context *nvc0, unsigned s)
331 {
332 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
333 struct nvc0_screen *screen = nvc0->screen;
334
335 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
336 PUSH_DATA (push, 2048);
337 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s));
338 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s));
339 BEGIN_1IC0(push, NVC0_3D(CB_POS), PIPE_MAX_CLIP_PLANES * 4 + 1);
340 PUSH_DATA (push, NVC0_CB_AUX_UCP_INFO);
341 PUSH_DATAp(push, &nvc0->clip.ucp[0][0], PIPE_MAX_CLIP_PLANES * 4);
342 }
343
344 static inline void
345 nvc0_check_program_ucps(struct nvc0_context *nvc0,
346 struct nvc0_program *vp, uint8_t mask)
347 {
348 const unsigned n = util_logbase2(mask) + 1;
349
350 if (vp->vp.num_ucps >= n)
351 return;
352 nvc0_program_destroy(nvc0, vp);
353
354 vp->vp.num_ucps = n;
355 if (likely(vp == nvc0->vertprog))
356 nvc0_vertprog_validate(nvc0);
357 else
358 if (likely(vp == nvc0->gmtyprog))
359 nvc0_gmtyprog_validate(nvc0);
360 else
361 nvc0_tevlprog_validate(nvc0);
362 }
363
364 static void
365 nvc0_validate_clip(struct nvc0_context *nvc0)
366 {
367 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
368 struct nvc0_program *vp;
369 unsigned stage;
370 uint8_t clip_enable = nvc0->rast->pipe.clip_plane_enable;
371
372 if (nvc0->gmtyprog) {
373 stage = 3;
374 vp = nvc0->gmtyprog;
375 } else
376 if (nvc0->tevlprog) {
377 stage = 2;
378 vp = nvc0->tevlprog;
379 } else {
380 stage = 0;
381 vp = nvc0->vertprog;
382 }
383
384 if (clip_enable && vp->vp.num_ucps < PIPE_MAX_CLIP_PLANES)
385 nvc0_check_program_ucps(nvc0, vp, clip_enable);
386
387 if (nvc0->dirty_3d & (NVC0_NEW_3D_CLIP | (NVC0_NEW_3D_VERTPROG << stage)))
388 if (vp->vp.num_ucps > 0 && vp->vp.num_ucps <= PIPE_MAX_CLIP_PLANES)
389 nvc0_upload_uclip_planes(nvc0, stage);
390
391 clip_enable &= vp->vp.clip_enable;
392 clip_enable |= vp->vp.cull_enable;
393
394 if (nvc0->state.clip_enable != clip_enable) {
395 nvc0->state.clip_enable = clip_enable;
396 IMMED_NVC0(push, NVC0_3D(CLIP_DISTANCE_ENABLE), clip_enable);
397 }
398 if (nvc0->state.clip_mode != vp->vp.clip_mode) {
399 nvc0->state.clip_mode = vp->vp.clip_mode;
400 BEGIN_NVC0(push, NVC0_3D(CLIP_DISTANCE_MODE), 1);
401 PUSH_DATA (push, vp->vp.clip_mode);
402 }
403 }
404
405 static void
406 nvc0_validate_blend(struct nvc0_context *nvc0)
407 {
408 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
409
410 PUSH_SPACE(push, nvc0->blend->size);
411 PUSH_DATAp(push, nvc0->blend->state, nvc0->blend->size);
412 }
413
414 static void
415 nvc0_validate_zsa(struct nvc0_context *nvc0)
416 {
417 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
418
419 PUSH_SPACE(push, nvc0->zsa->size);
420 PUSH_DATAp(push, nvc0->zsa->state, nvc0->zsa->size);
421 }
422
423 static void
424 nvc0_validate_rasterizer(struct nvc0_context *nvc0)
425 {
426 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
427
428 PUSH_SPACE(push, nvc0->rast->size);
429 PUSH_DATAp(push, nvc0->rast->state, nvc0->rast->size);
430 }
431
432 static void
433 nvc0_constbufs_validate(struct nvc0_context *nvc0)
434 {
435 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
436 unsigned s;
437
438 for (s = 0; s < 5; ++s) {
439 while (nvc0->constbuf_dirty[s]) {
440 int i = ffs(nvc0->constbuf_dirty[s]) - 1;
441 nvc0->constbuf_dirty[s] &= ~(1 << i);
442
443 if (nvc0->constbuf[s][i].user) {
444 struct nouveau_bo *bo = nvc0->screen->uniform_bo;
445 const unsigned base = NVC0_CB_USR_INFO(s);
446 const unsigned size = nvc0->constbuf[s][0].size;
447 assert(i == 0); /* we really only want OpenGL uniforms here */
448 assert(nvc0->constbuf[s][0].u.data);
449
450 if (nvc0->state.uniform_buffer_bound[s] < size) {
451 nvc0->state.uniform_buffer_bound[s] = align(size, 0x100);
452
453 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
454 PUSH_DATA (push, nvc0->state.uniform_buffer_bound[s]);
455 PUSH_DATAh(push, bo->offset + base);
456 PUSH_DATA (push, bo->offset + base);
457 BEGIN_NVC0(push, NVC0_3D(CB_BIND(s)), 1);
458 PUSH_DATA (push, (0 << 4) | 1);
459 }
460 nvc0_cb_bo_push(&nvc0->base, bo, NV_VRAM_DOMAIN(&nvc0->screen->base),
461 base, nvc0->state.uniform_buffer_bound[s],
462 0, (size + 3) / 4,
463 nvc0->constbuf[s][0].u.data);
464 } else {
465 struct nv04_resource *res =
466 nv04_resource(nvc0->constbuf[s][i].u.buf);
467 if (res) {
468 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
469 PUSH_DATA (push, nvc0->constbuf[s][i].size);
470 PUSH_DATAh(push, res->address + nvc0->constbuf[s][i].offset);
471 PUSH_DATA (push, res->address + nvc0->constbuf[s][i].offset);
472 BEGIN_NVC0(push, NVC0_3D(CB_BIND(s)), 1);
473 PUSH_DATA (push, (i << 4) | 1);
474
475 BCTX_REFN(nvc0->bufctx_3d, 3D_CB(s, i), res, RD);
476
477 nvc0->cb_dirty = 1; /* Force cache flush for UBO. */
478 res->cb_bindings[s] |= 1 << i;
479 } else {
480 BEGIN_NVC0(push, NVC0_3D(CB_BIND(s)), 1);
481 PUSH_DATA (push, (i << 4) | 0);
482 }
483 if (i == 0)
484 nvc0->state.uniform_buffer_bound[s] = 0;
485 }
486 }
487 }
488
489 if (nvc0->screen->base.class_3d < NVE4_3D_CLASS) {
490 /* Invalidate all COMPUTE constbufs because they are aliased with 3D. */
491 nvc0->dirty_cp |= NVC0_NEW_CP_CONSTBUF;
492 nvc0->constbuf_dirty[5] |= nvc0->constbuf_valid[5];
493 nvc0->state.uniform_buffer_bound[5] = 0;
494 }
495 }
496
497 static void
498 nvc0_validate_buffers(struct nvc0_context *nvc0)
499 {
500 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
501 struct nvc0_screen *screen = nvc0->screen;
502 int i, s;
503
504 for (s = 0; s < 5; s++) {
505 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
506 PUSH_DATA (push, 2048);
507 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s));
508 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s));
509 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 4 * NVC0_MAX_BUFFERS);
510 PUSH_DATA (push, NVC0_CB_AUX_BUF_INFO(0));
511 for (i = 0; i < NVC0_MAX_BUFFERS; i++) {
512 if (nvc0->buffers[s][i].buffer) {
513 struct nv04_resource *res =
514 nv04_resource(nvc0->buffers[s][i].buffer);
515 PUSH_DATA (push, res->address + nvc0->buffers[s][i].buffer_offset);
516 PUSH_DATAh(push, res->address + nvc0->buffers[s][i].buffer_offset);
517 PUSH_DATA (push, nvc0->buffers[s][i].buffer_size);
518 PUSH_DATA (push, 0);
519 BCTX_REFN(nvc0->bufctx_3d, 3D_BUF, res, RDWR);
520 util_range_add(&res->valid_buffer_range,
521 nvc0->buffers[s][i].buffer_offset,
522 nvc0->buffers[s][i].buffer_size);
523 } else {
524 PUSH_DATA (push, 0);
525 PUSH_DATA (push, 0);
526 PUSH_DATA (push, 0);
527 PUSH_DATA (push, 0);
528 }
529 }
530 }
531
532 }
533
534 static void
535 nvc0_validate_sample_mask(struct nvc0_context *nvc0)
536 {
537 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
538
539 unsigned mask[4] =
540 {
541 nvc0->sample_mask & 0xffff,
542 nvc0->sample_mask & 0xffff,
543 nvc0->sample_mask & 0xffff,
544 nvc0->sample_mask & 0xffff
545 };
546
547 BEGIN_NVC0(push, NVC0_3D(MSAA_MASK(0)), 4);
548 PUSH_DATA (push, mask[0]);
549 PUSH_DATA (push, mask[1]);
550 PUSH_DATA (push, mask[2]);
551 PUSH_DATA (push, mask[3]);
552 }
553
554 static void
555 nvc0_validate_min_samples(struct nvc0_context *nvc0)
556 {
557 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
558 int samples;
559
560 samples = util_next_power_of_two(nvc0->min_samples);
561 if (samples > 1) {
562 // If we're using the incoming sample mask and doing sample shading, we
563 // have to do sample shading "to the max", otherwise there's no way to
564 // tell which sets of samples are covered by the current invocation.
565 if (nvc0->fragprog->fp.sample_mask_in)
566 samples = util_framebuffer_get_num_samples(&nvc0->framebuffer);
567 samples |= NVC0_3D_SAMPLE_SHADING_ENABLE;
568 }
569
570 IMMED_NVC0(push, NVC0_3D(SAMPLE_SHADING), samples);
571 }
572
573 static void
574 nvc0_validate_driverconst(struct nvc0_context *nvc0)
575 {
576 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
577 struct nvc0_screen *screen = nvc0->screen;
578 int i;
579
580 for (i = 0; i < 5; ++i) {
581 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
582 PUSH_DATA (push, 2048);
583 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
584 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
585 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
586 PUSH_DATA (push, (15 << 4) | 1);
587 }
588
589 nvc0->dirty_cp |= NVC0_NEW_CP_DRIVERCONST;
590 }
591
592 static void
593 nvc0_validate_derived_1(struct nvc0_context *nvc0)
594 {
595 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
596 bool rasterizer_discard;
597
598 if (nvc0->rast && nvc0->rast->pipe.rasterizer_discard) {
599 rasterizer_discard = true;
600 } else {
601 bool zs = nvc0->zsa &&
602 (nvc0->zsa->pipe.depth.enabled || nvc0->zsa->pipe.stencil[0].enabled);
603 rasterizer_discard = !zs &&
604 (!nvc0->fragprog || !nvc0->fragprog->hdr[18]);
605 }
606
607 if (rasterizer_discard != nvc0->state.rasterizer_discard) {
608 nvc0->state.rasterizer_discard = rasterizer_discard;
609 IMMED_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), !rasterizer_discard);
610 }
611 }
612
613 /* alpha test is disabled if there are no color RTs, so make sure we have at
614 * least one if alpha test is enabled. Note that this must run after
615 * nvc0_validate_fb, otherwise that will override the RT count setting.
616 */
617 static void
618 nvc0_validate_derived_2(struct nvc0_context *nvc0)
619 {
620 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
621
622 if (nvc0->zsa && nvc0->zsa->pipe.alpha.enabled &&
623 nvc0->framebuffer.zsbuf &&
624 nvc0->framebuffer.nr_cbufs == 0) {
625 nvc0_fb_set_null_rt(push, 0, 0);
626 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
627 PUSH_DATA (push, (076543210 << 4) | 1);
628 }
629 }
630
631 static void
632 nvc0_validate_derived_3(struct nvc0_context *nvc0)
633 {
634 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
635 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
636 uint32_t ms = 0;
637
638 if ((!fb->nr_cbufs || !fb->cbufs[0] ||
639 !util_format_is_pure_integer(fb->cbufs[0]->format)) && nvc0->blend) {
640 if (nvc0->blend->pipe.alpha_to_coverage)
641 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE;
642 if (nvc0->blend->pipe.alpha_to_one)
643 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE;
644 }
645
646 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
647 PUSH_DATA (push, ms);
648 }
649
650 static void
651 nvc0_validate_tess_state(struct nvc0_context *nvc0)
652 {
653 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
654
655 BEGIN_NVC0(push, NVC0_3D(TESS_LEVEL_OUTER(0)), 6);
656 PUSH_DATAp(push, nvc0->default_tess_outer, 4);
657 PUSH_DATAp(push, nvc0->default_tess_inner, 2);
658 }
659
660 static void
661 nvc0_switch_pipe_context(struct nvc0_context *ctx_to)
662 {
663 struct nvc0_context *ctx_from = ctx_to->screen->cur_ctx;
664 unsigned s;
665
666 if (ctx_from)
667 ctx_to->state = ctx_from->state;
668 else
669 ctx_to->state = ctx_to->screen->save_state;
670
671 ctx_to->dirty_3d = ~0;
672 ctx_to->dirty_cp = ~0;
673 ctx_to->viewports_dirty = ~0;
674 ctx_to->scissors_dirty = ~0;
675
676 for (s = 0; s < 6; ++s) {
677 ctx_to->samplers_dirty[s] = ~0;
678 ctx_to->textures_dirty[s] = ~0;
679 ctx_to->constbuf_dirty[s] = (1 << NVC0_MAX_PIPE_CONSTBUFS) - 1;
680 ctx_to->buffers_dirty[s] = ~0;
681 ctx_to->images_dirty[s] = ~0;
682 }
683
684 /* Reset tfb as the shader that owns it may have been deleted. */
685 ctx_to->state.tfb = NULL;
686
687 if (!ctx_to->vertex)
688 ctx_to->dirty_3d &= ~(NVC0_NEW_3D_VERTEX | NVC0_NEW_3D_ARRAYS);
689 if (!ctx_to->idxbuf.buffer)
690 ctx_to->dirty_3d &= ~NVC0_NEW_3D_IDXBUF;
691
692 if (!ctx_to->vertprog)
693 ctx_to->dirty_3d &= ~NVC0_NEW_3D_VERTPROG;
694 if (!ctx_to->fragprog)
695 ctx_to->dirty_3d &= ~NVC0_NEW_3D_FRAGPROG;
696
697 if (!ctx_to->blend)
698 ctx_to->dirty_3d &= ~NVC0_NEW_3D_BLEND;
699 if (!ctx_to->rast)
700 ctx_to->dirty_3d &= ~(NVC0_NEW_3D_RASTERIZER | NVC0_NEW_3D_SCISSOR);
701 if (!ctx_to->zsa)
702 ctx_to->dirty_3d &= ~NVC0_NEW_3D_ZSA;
703
704 ctx_to->screen->cur_ctx = ctx_to;
705 }
706
707 static struct nvc0_state_validate
708 validate_list_3d[] = {
709 { nvc0_validate_fb, NVC0_NEW_3D_FRAMEBUFFER },
710 { nvc0_validate_blend, NVC0_NEW_3D_BLEND },
711 { nvc0_validate_zsa, NVC0_NEW_3D_ZSA },
712 { nvc0_validate_sample_mask, NVC0_NEW_3D_SAMPLE_MASK },
713 { nvc0_validate_rasterizer, NVC0_NEW_3D_RASTERIZER },
714 { nvc0_validate_blend_colour, NVC0_NEW_3D_BLEND_COLOUR },
715 { nvc0_validate_stencil_ref, NVC0_NEW_3D_STENCIL_REF },
716 { nvc0_validate_stipple, NVC0_NEW_3D_STIPPLE },
717 { nvc0_validate_scissor, NVC0_NEW_3D_SCISSOR | NVC0_NEW_3D_RASTERIZER },
718 { nvc0_validate_viewport, NVC0_NEW_3D_VIEWPORT },
719 { nvc0_vertprog_validate, NVC0_NEW_3D_VERTPROG },
720 { nvc0_tctlprog_validate, NVC0_NEW_3D_TCTLPROG },
721 { nvc0_tevlprog_validate, NVC0_NEW_3D_TEVLPROG },
722 { nvc0_validate_tess_state, NVC0_NEW_3D_TESSFACTOR },
723 { nvc0_gmtyprog_validate, NVC0_NEW_3D_GMTYPROG },
724 { nvc0_validate_min_samples, NVC0_NEW_3D_MIN_SAMPLES |
725 NVC0_NEW_3D_FRAGPROG |
726 NVC0_NEW_3D_FRAMEBUFFER },
727 { nvc0_fragprog_validate, NVC0_NEW_3D_FRAGPROG | NVC0_NEW_3D_RASTERIZER },
728 { nvc0_validate_derived_1, NVC0_NEW_3D_FRAGPROG | NVC0_NEW_3D_ZSA |
729 NVC0_NEW_3D_RASTERIZER },
730 { nvc0_validate_derived_2, NVC0_NEW_3D_ZSA | NVC0_NEW_3D_FRAMEBUFFER },
731 { nvc0_validate_derived_3, NVC0_NEW_3D_BLEND | NVC0_NEW_3D_FRAMEBUFFER },
732 { nvc0_validate_clip, NVC0_NEW_3D_CLIP | NVC0_NEW_3D_RASTERIZER |
733 NVC0_NEW_3D_VERTPROG |
734 NVC0_NEW_3D_TEVLPROG |
735 NVC0_NEW_3D_GMTYPROG },
736 { nvc0_constbufs_validate, NVC0_NEW_3D_CONSTBUF },
737 { nvc0_validate_textures, NVC0_NEW_3D_TEXTURES },
738 { nvc0_validate_samplers, NVC0_NEW_3D_SAMPLERS },
739 { nve4_set_tex_handles, NVC0_NEW_3D_TEXTURES | NVC0_NEW_3D_SAMPLERS },
740 { nvc0_vertex_arrays_validate, NVC0_NEW_3D_VERTEX | NVC0_NEW_3D_ARRAYS },
741 { nvc0_validate_surfaces, NVC0_NEW_3D_SURFACES },
742 { nvc0_validate_buffers, NVC0_NEW_3D_BUFFERS },
743 { nvc0_idxbuf_validate, NVC0_NEW_3D_IDXBUF },
744 { nvc0_tfb_validate, NVC0_NEW_3D_TFB_TARGETS | NVC0_NEW_3D_GMTYPROG },
745 { nvc0_validate_driverconst, NVC0_NEW_3D_DRIVERCONST },
746 };
747
748 bool
749 nvc0_state_validate(struct nvc0_context *nvc0, uint32_t mask,
750 struct nvc0_state_validate *validate_list, int size,
751 uint32_t *dirty, struct nouveau_bufctx *bufctx)
752 {
753 uint32_t state_mask;
754 int ret;
755 unsigned i;
756
757 if (nvc0->screen->cur_ctx != nvc0)
758 nvc0_switch_pipe_context(nvc0);
759
760 state_mask = *dirty & mask;
761
762 if (state_mask) {
763 for (i = 0; i < size; ++i) {
764 struct nvc0_state_validate *validate = &validate_list[i];
765
766 if (state_mask & validate->states)
767 validate->func(nvc0);
768 }
769 *dirty &= ~state_mask;
770
771 nvc0_bufctx_fence(nvc0, bufctx, false);
772 }
773
774 nouveau_pushbuf_bufctx(nvc0->base.pushbuf, bufctx);
775 ret = nouveau_pushbuf_validate(nvc0->base.pushbuf);
776
777 return !ret;
778 }
779
780 bool
781 nvc0_state_validate_3d(struct nvc0_context *nvc0, uint32_t mask)
782 {
783 bool ret;
784
785 ret = nvc0_state_validate(nvc0, mask, validate_list_3d,
786 ARRAY_SIZE(validate_list_3d), &nvc0->dirty_3d,
787 nvc0->bufctx_3d);
788
789 if (unlikely(nvc0->state.flushed)) {
790 nvc0->state.flushed = false;
791 nvc0_bufctx_fence(nvc0, nvc0->bufctx_3d, true);
792 }
793 return ret;
794 }