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nvc0: add a new bin for the code segment
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_state_validate.c
1
2 #include "util/u_format.h"
3 #include "util/u_framebuffer.h"
4 #include "util/u_math.h"
5 #include "util/u_viewport.h"
6
7 #include "nvc0/nvc0_context.h"
8
9 #if 0
10 static void
11 nvc0_validate_zcull(struct nvc0_context *nvc0)
12 {
13 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
14 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
15 struct nv50_surface *sf = nv50_surface(fb->zsbuf);
16 struct nv50_miptree *mt = nv50_miptree(sf->base.texture);
17 struct nouveau_bo *bo = mt->base.bo;
18 uint32_t size;
19 uint32_t offset = align(mt->total_size, 1 << 17);
20 unsigned width, height;
21
22 assert(mt->base.base.depth0 == 1 && mt->base.base.array_size < 2);
23
24 size = mt->total_size * 2;
25
26 height = align(fb->height, 32);
27 width = fb->width % 224;
28 if (width)
29 width = fb->width + (224 - width);
30 else
31 width = fb->width;
32
33 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1);
34 PUSH_DATA (push, 0);
35 BEGIN_NVC0(push, NVC0_3D(ZCULL_ADDRESS_HIGH), 2);
36 PUSH_DATAh(push, bo->offset + offset);
37 PUSH_DATA (push, bo->offset + offset);
38 offset += 1 << 17;
39 BEGIN_NVC0(push, NVC0_3D(ZCULL_LIMIT_HIGH), 2);
40 PUSH_DATAh(push, bo->offset + offset);
41 PUSH_DATA (push, bo->offset + offset);
42 BEGIN_NVC0(push, SUBC_3D(0x07e0), 2);
43 PUSH_DATA (push, size);
44 PUSH_DATA (push, size >> 16);
45 BEGIN_NVC0(push, SUBC_3D(0x15c8), 1); /* bits 0x3 */
46 PUSH_DATA (push, 2);
47 BEGIN_NVC0(push, NVC0_3D(ZCULL_WIDTH), 4);
48 PUSH_DATA (push, width);
49 PUSH_DATA (push, height);
50 PUSH_DATA (push, 1);
51 PUSH_DATA (push, 0);
52 BEGIN_NVC0(push, NVC0_3D(ZCULL_WINDOW_OFFSET_X), 2);
53 PUSH_DATA (push, 0);
54 PUSH_DATA (push, 0);
55 BEGIN_NVC0(push, NVC0_3D(ZCULL_INVALIDATE), 1);
56 PUSH_DATA (push, 0);
57 }
58 #endif
59
60 static inline void
61 nvc0_fb_set_null_rt(struct nouveau_pushbuf *push, unsigned i, unsigned layers)
62 {
63 BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(i)), 9);
64 PUSH_DATA (push, 0);
65 PUSH_DATA (push, 0);
66 PUSH_DATA (push, 64); // width
67 PUSH_DATA (push, 0); // height
68 PUSH_DATA (push, 0); // format
69 PUSH_DATA (push, 0); // tile mode
70 PUSH_DATA (push, layers); // layers
71 PUSH_DATA (push, 0); // layer stride
72 PUSH_DATA (push, 0); // base layer
73 }
74
75 static void
76 nvc0_validate_fb(struct nvc0_context *nvc0)
77 {
78 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
79 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
80 struct nvc0_screen *screen = nvc0->screen;
81 unsigned i, ms;
82 unsigned ms_mode = NVC0_3D_MULTISAMPLE_MODE_MS1;
83 unsigned nr_cbufs = fb->nr_cbufs;
84 bool serialize = false;
85
86 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_FB);
87
88 BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
89 PUSH_DATA (push, fb->width << 16);
90 PUSH_DATA (push, fb->height << 16);
91
92 for (i = 0; i < fb->nr_cbufs; ++i) {
93 struct nv50_surface *sf;
94 struct nv04_resource *res;
95 struct nouveau_bo *bo;
96
97 if (!fb->cbufs[i]) {
98 nvc0_fb_set_null_rt(push, i, 0);
99 continue;
100 }
101
102 sf = nv50_surface(fb->cbufs[i]);
103 res = nv04_resource(sf->base.texture);
104 bo = res->bo;
105
106 BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(i)), 9);
107 PUSH_DATAh(push, res->address + sf->offset);
108 PUSH_DATA (push, res->address + sf->offset);
109 if (likely(nouveau_bo_memtype(bo))) {
110 struct nv50_miptree *mt = nv50_miptree(sf->base.texture);
111
112 assert(sf->base.texture->target != PIPE_BUFFER);
113
114 PUSH_DATA(push, sf->width);
115 PUSH_DATA(push, sf->height);
116 PUSH_DATA(push, nvc0_format_table[sf->base.format].rt);
117 PUSH_DATA(push, (mt->layout_3d << 16) |
118 mt->level[sf->base.u.tex.level].tile_mode);
119 PUSH_DATA(push, sf->base.u.tex.first_layer + sf->depth);
120 PUSH_DATA(push, mt->layer_stride >> 2);
121 PUSH_DATA(push, sf->base.u.tex.first_layer);
122
123 ms_mode = mt->ms_mode;
124 } else {
125 if (res->base.target == PIPE_BUFFER) {
126 PUSH_DATA(push, 262144);
127 PUSH_DATA(push, 1);
128 } else {
129 PUSH_DATA(push, nv50_miptree(sf->base.texture)->level[0].pitch);
130 PUSH_DATA(push, sf->height);
131 }
132 PUSH_DATA(push, nvc0_format_table[sf->base.format].rt);
133 PUSH_DATA(push, 1 << 12);
134 PUSH_DATA(push, 1);
135 PUSH_DATA(push, 0);
136 PUSH_DATA(push, 0);
137
138 nvc0_resource_fence(res, NOUVEAU_BO_WR);
139
140 assert(!fb->zsbuf);
141 }
142
143 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_READING)
144 serialize = true;
145 res->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
146 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING;
147
148 /* only register for writing, otherwise we'd always serialize here */
149 BCTX_REFN(nvc0->bufctx_3d, 3D_FB, res, WR);
150 }
151
152 if (fb->zsbuf) {
153 struct nv50_miptree *mt = nv50_miptree(fb->zsbuf->texture);
154 struct nv50_surface *sf = nv50_surface(fb->zsbuf);
155 int unk = mt->base.base.target == PIPE_TEXTURE_2D;
156
157 BEGIN_NVC0(push, NVC0_3D(ZETA_ADDRESS_HIGH), 5);
158 PUSH_DATAh(push, mt->base.address + sf->offset);
159 PUSH_DATA (push, mt->base.address + sf->offset);
160 PUSH_DATA (push, nvc0_format_table[fb->zsbuf->format].rt);
161 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
162 PUSH_DATA (push, mt->layer_stride >> 2);
163 BEGIN_NVC0(push, NVC0_3D(ZETA_ENABLE), 1);
164 PUSH_DATA (push, 1);
165 BEGIN_NVC0(push, NVC0_3D(ZETA_HORIZ), 3);
166 PUSH_DATA (push, sf->width);
167 PUSH_DATA (push, sf->height);
168 PUSH_DATA (push, (unk << 16) |
169 (sf->base.u.tex.first_layer + sf->depth));
170 BEGIN_NVC0(push, NVC0_3D(ZETA_BASE_LAYER), 1);
171 PUSH_DATA (push, sf->base.u.tex.first_layer);
172
173 ms_mode = mt->ms_mode;
174
175 if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING)
176 serialize = true;
177 mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
178 mt->base.status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING;
179
180 BCTX_REFN(nvc0->bufctx_3d, 3D_FB, &mt->base, WR);
181 } else {
182 BEGIN_NVC0(push, NVC0_3D(ZETA_ENABLE), 1);
183 PUSH_DATA (push, 0);
184 }
185
186 if (nr_cbufs == 0 && !fb->zsbuf) {
187 assert(util_is_power_of_two(fb->samples));
188 assert(fb->samples <= 8);
189
190 nvc0_fb_set_null_rt(push, 0, fb->layers);
191
192 if (fb->samples > 1)
193 ms_mode = ffs(fb->samples) - 1;
194 nr_cbufs = 1;
195 }
196
197 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
198 PUSH_DATA (push, (076543210 << 4) | nr_cbufs);
199 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), ms_mode);
200
201 ms = 1 << ms_mode;
202 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
203 PUSH_DATA (push, NVC0_CB_AUX_SIZE);
204 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(4));
205 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(4));
206 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * ms);
207 PUSH_DATA (push, NVC0_CB_AUX_SAMPLE_INFO);
208 for (i = 0; i < ms; i++) {
209 float xy[2];
210 nvc0->base.pipe.get_sample_position(&nvc0->base.pipe, ms, i, xy);
211 PUSH_DATAf(push, xy[0]);
212 PUSH_DATAf(push, xy[1]);
213 }
214
215 if (screen->base.class_3d >= GM200_3D_CLASS) {
216 const uint8_t (*ptr)[2] = nvc0_get_sample_locations(ms);
217 uint32_t val[4] = {};
218
219 for (i = 0; i < 16; i++) {
220 val[i / 4] |= ptr[i % ms][0] << (((i % 4) * 8) + 0);
221 val[i / 4] |= ptr[i % ms][1] << (((i % 4) * 8) + 4);
222 }
223
224 BEGIN_NVC0(push, SUBC_3D(0x11e0), 4);
225 PUSH_DATAp(push, val, 4);
226 }
227
228 if (serialize)
229 IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
230
231 NOUVEAU_DRV_STAT(&nvc0->screen->base, gpu_serialize_count, serialize);
232 }
233
234 static void
235 nvc0_validate_blend_colour(struct nvc0_context *nvc0)
236 {
237 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
238
239 BEGIN_NVC0(push, NVC0_3D(BLEND_COLOR(0)), 4);
240 PUSH_DATAf(push, nvc0->blend_colour.color[0]);
241 PUSH_DATAf(push, nvc0->blend_colour.color[1]);
242 PUSH_DATAf(push, nvc0->blend_colour.color[2]);
243 PUSH_DATAf(push, nvc0->blend_colour.color[3]);
244 }
245
246 static void
247 nvc0_validate_stencil_ref(struct nvc0_context *nvc0)
248 {
249 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
250 const ubyte *ref = &nvc0->stencil_ref.ref_value[0];
251
252 IMMED_NVC0(push, NVC0_3D(STENCIL_FRONT_FUNC_REF), ref[0]);
253 IMMED_NVC0(push, NVC0_3D(STENCIL_BACK_FUNC_REF), ref[1]);
254 }
255
256 static void
257 nvc0_validate_stipple(struct nvc0_context *nvc0)
258 {
259 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
260 unsigned i;
261
262 BEGIN_NVC0(push, NVC0_3D(POLYGON_STIPPLE_PATTERN(0)), 32);
263 for (i = 0; i < 32; ++i)
264 PUSH_DATA(push, util_bswap32(nvc0->stipple.stipple[i]));
265 }
266
267 static void
268 nvc0_validate_scissor(struct nvc0_context *nvc0)
269 {
270 int i;
271 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
272
273 if (!(nvc0->dirty_3d & NVC0_NEW_3D_SCISSOR) &&
274 nvc0->rast->pipe.scissor == nvc0->state.scissor)
275 return;
276
277 if (nvc0->state.scissor != nvc0->rast->pipe.scissor)
278 nvc0->scissors_dirty = (1 << NVC0_MAX_VIEWPORTS) - 1;
279
280 nvc0->state.scissor = nvc0->rast->pipe.scissor;
281
282 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
283 struct pipe_scissor_state *s = &nvc0->scissors[i];
284 if (!(nvc0->scissors_dirty & (1 << i)))
285 continue;
286
287 BEGIN_NVC0(push, NVC0_3D(SCISSOR_HORIZ(i)), 2);
288 if (nvc0->rast->pipe.scissor) {
289 PUSH_DATA(push, (s->maxx << 16) | s->minx);
290 PUSH_DATA(push, (s->maxy << 16) | s->miny);
291 } else {
292 PUSH_DATA(push, (0xffff << 16) | 0);
293 PUSH_DATA(push, (0xffff << 16) | 0);
294 }
295 }
296 nvc0->scissors_dirty = 0;
297 }
298
299 static void
300 nvc0_validate_viewport(struct nvc0_context *nvc0)
301 {
302 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
303 int x, y, w, h, i;
304 float zmin, zmax;
305
306 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
307 struct pipe_viewport_state *vp = &nvc0->viewports[i];
308
309 if (!(nvc0->viewports_dirty & (1 << i)))
310 continue;
311
312 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSLATE_X(i)), 3);
313 PUSH_DATAf(push, vp->translate[0]);
314 PUSH_DATAf(push, vp->translate[1]);
315 PUSH_DATAf(push, vp->translate[2]);
316
317 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_SCALE_X(i)), 3);
318 PUSH_DATAf(push, vp->scale[0]);
319 PUSH_DATAf(push, vp->scale[1]);
320 PUSH_DATAf(push, vp->scale[2]);
321
322 /* now set the viewport rectangle to viewport dimensions for clipping */
323
324 x = util_iround(MAX2(0.0f, vp->translate[0] - fabsf(vp->scale[0])));
325 y = util_iround(MAX2(0.0f, vp->translate[1] - fabsf(vp->scale[1])));
326 w = util_iround(vp->translate[0] + fabsf(vp->scale[0])) - x;
327 h = util_iround(vp->translate[1] + fabsf(vp->scale[1])) - y;
328
329 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_HORIZ(i)), 2);
330 PUSH_DATA (push, (w << 16) | x);
331 PUSH_DATA (push, (h << 16) | y);
332
333 /* If the halfz setting ever changes, the viewports will also get
334 * updated. The rast will get updated before the validate function has a
335 * chance to hit, so we can just use it directly without an atom
336 * dependency.
337 */
338 util_viewport_zmin_zmax(vp, nvc0->rast->pipe.clip_halfz, &zmin, &zmax);
339
340 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
341 PUSH_DATAf(push, zmin);
342 PUSH_DATAf(push, zmax);
343 }
344 nvc0->viewports_dirty = 0;
345 }
346
347 static void
348 nvc0_validate_window_rects(struct nvc0_context *nvc0)
349 {
350 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
351 bool enable = nvc0->window_rect.rects > 0 || nvc0->window_rect.inclusive;
352 int i;
353
354 IMMED_NVC0(push, NVC0_3D(CLIP_RECTS_EN), enable);
355 if (!enable)
356 return;
357
358 IMMED_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), !nvc0->window_rect.inclusive);
359 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), NVC0_MAX_WINDOW_RECTANGLES * 2);
360 for (i = 0; i < nvc0->window_rect.rects; i++) {
361 struct pipe_scissor_state *s = &nvc0->window_rect.rect[i];
362 PUSH_DATA(push, (s->maxx << 16) | s->minx);
363 PUSH_DATA(push, (s->maxy << 16) | s->miny);
364 }
365 for (; i < NVC0_MAX_WINDOW_RECTANGLES; i++) {
366 PUSH_DATA(push, 0);
367 PUSH_DATA(push, 0);
368 }
369 }
370
371 static inline void
372 nvc0_upload_uclip_planes(struct nvc0_context *nvc0, unsigned s)
373 {
374 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
375 struct nvc0_screen *screen = nvc0->screen;
376
377 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
378 PUSH_DATA (push, NVC0_CB_AUX_SIZE);
379 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s));
380 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s));
381 BEGIN_1IC0(push, NVC0_3D(CB_POS), PIPE_MAX_CLIP_PLANES * 4 + 1);
382 PUSH_DATA (push, NVC0_CB_AUX_UCP_INFO);
383 PUSH_DATAp(push, &nvc0->clip.ucp[0][0], PIPE_MAX_CLIP_PLANES * 4);
384 }
385
386 static inline void
387 nvc0_check_program_ucps(struct nvc0_context *nvc0,
388 struct nvc0_program *vp, uint8_t mask)
389 {
390 const unsigned n = util_logbase2(mask) + 1;
391
392 if (vp->vp.num_ucps >= n)
393 return;
394 nvc0_program_destroy(nvc0, vp);
395
396 vp->vp.num_ucps = n;
397 if (likely(vp == nvc0->vertprog))
398 nvc0_vertprog_validate(nvc0);
399 else
400 if (likely(vp == nvc0->gmtyprog))
401 nvc0_gmtyprog_validate(nvc0);
402 else
403 nvc0_tevlprog_validate(nvc0);
404 }
405
406 static void
407 nvc0_validate_clip(struct nvc0_context *nvc0)
408 {
409 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
410 struct nvc0_program *vp;
411 unsigned stage;
412 uint8_t clip_enable = nvc0->rast->pipe.clip_plane_enable;
413
414 if (nvc0->gmtyprog) {
415 stage = 3;
416 vp = nvc0->gmtyprog;
417 } else
418 if (nvc0->tevlprog) {
419 stage = 2;
420 vp = nvc0->tevlprog;
421 } else {
422 stage = 0;
423 vp = nvc0->vertprog;
424 }
425
426 if (clip_enable && vp->vp.num_ucps < PIPE_MAX_CLIP_PLANES)
427 nvc0_check_program_ucps(nvc0, vp, clip_enable);
428
429 if (nvc0->dirty_3d & (NVC0_NEW_3D_CLIP | (NVC0_NEW_3D_VERTPROG << stage)))
430 if (vp->vp.num_ucps > 0 && vp->vp.num_ucps <= PIPE_MAX_CLIP_PLANES)
431 nvc0_upload_uclip_planes(nvc0, stage);
432
433 clip_enable &= vp->vp.clip_enable;
434 clip_enable |= vp->vp.cull_enable;
435
436 if (nvc0->state.clip_enable != clip_enable) {
437 nvc0->state.clip_enable = clip_enable;
438 IMMED_NVC0(push, NVC0_3D(CLIP_DISTANCE_ENABLE), clip_enable);
439 }
440 if (nvc0->state.clip_mode != vp->vp.clip_mode) {
441 nvc0->state.clip_mode = vp->vp.clip_mode;
442 BEGIN_NVC0(push, NVC0_3D(CLIP_DISTANCE_MODE), 1);
443 PUSH_DATA (push, vp->vp.clip_mode);
444 }
445 }
446
447 static void
448 nvc0_validate_blend(struct nvc0_context *nvc0)
449 {
450 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
451
452 PUSH_SPACE(push, nvc0->blend->size);
453 PUSH_DATAp(push, nvc0->blend->state, nvc0->blend->size);
454 }
455
456 static void
457 nvc0_validate_zsa(struct nvc0_context *nvc0)
458 {
459 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
460
461 PUSH_SPACE(push, nvc0->zsa->size);
462 PUSH_DATAp(push, nvc0->zsa->state, nvc0->zsa->size);
463 }
464
465 static void
466 nvc0_validate_rasterizer(struct nvc0_context *nvc0)
467 {
468 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
469
470 PUSH_SPACE(push, nvc0->rast->size);
471 PUSH_DATAp(push, nvc0->rast->state, nvc0->rast->size);
472 }
473
474 static void
475 nvc0_constbufs_validate(struct nvc0_context *nvc0)
476 {
477 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
478 unsigned s;
479
480 for (s = 0; s < 5; ++s) {
481 while (nvc0->constbuf_dirty[s]) {
482 int i = ffs(nvc0->constbuf_dirty[s]) - 1;
483 nvc0->constbuf_dirty[s] &= ~(1 << i);
484
485 if (nvc0->constbuf[s][i].user) {
486 struct nouveau_bo *bo = nvc0->screen->uniform_bo;
487 const unsigned base = NVC0_CB_USR_INFO(s);
488 const unsigned size = nvc0->constbuf[s][0].size;
489 assert(i == 0); /* we really only want OpenGL uniforms here */
490 assert(nvc0->constbuf[s][0].u.data);
491
492 if (nvc0->state.uniform_buffer_bound[s] < size) {
493 nvc0->state.uniform_buffer_bound[s] = align(size, 0x100);
494
495 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
496 PUSH_DATA (push, nvc0->state.uniform_buffer_bound[s]);
497 PUSH_DATAh(push, bo->offset + base);
498 PUSH_DATA (push, bo->offset + base);
499 BEGIN_NVC0(push, NVC0_3D(CB_BIND(s)), 1);
500 PUSH_DATA (push, (0 << 4) | 1);
501 }
502 nvc0_cb_bo_push(&nvc0->base, bo, NV_VRAM_DOMAIN(&nvc0->screen->base),
503 base, nvc0->state.uniform_buffer_bound[s],
504 0, (size + 3) / 4,
505 nvc0->constbuf[s][0].u.data);
506 } else {
507 struct nv04_resource *res =
508 nv04_resource(nvc0->constbuf[s][i].u.buf);
509 if (res) {
510 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
511 PUSH_DATA (push, nvc0->constbuf[s][i].size);
512 PUSH_DATAh(push, res->address + nvc0->constbuf[s][i].offset);
513 PUSH_DATA (push, res->address + nvc0->constbuf[s][i].offset);
514 BEGIN_NVC0(push, NVC0_3D(CB_BIND(s)), 1);
515 PUSH_DATA (push, (i << 4) | 1);
516
517 BCTX_REFN(nvc0->bufctx_3d, 3D_CB(s, i), res, RD);
518
519 nvc0->cb_dirty = 1; /* Force cache flush for UBO. */
520 res->cb_bindings[s] |= 1 << i;
521 } else {
522 BEGIN_NVC0(push, NVC0_3D(CB_BIND(s)), 1);
523 PUSH_DATA (push, (i << 4) | 0);
524 }
525 if (i == 0)
526 nvc0->state.uniform_buffer_bound[s] = 0;
527 }
528 }
529 }
530
531 if (nvc0->screen->base.class_3d < NVE4_3D_CLASS) {
532 /* Invalidate all COMPUTE constbufs because they are aliased with 3D. */
533 nvc0->dirty_cp |= NVC0_NEW_CP_CONSTBUF;
534 nvc0->constbuf_dirty[5] |= nvc0->constbuf_valid[5];
535 nvc0->state.uniform_buffer_bound[5] = 0;
536 }
537 }
538
539 static void
540 nvc0_validate_buffers(struct nvc0_context *nvc0)
541 {
542 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
543 struct nvc0_screen *screen = nvc0->screen;
544 int i, s;
545
546 for (s = 0; s < 5; s++) {
547 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
548 PUSH_DATA (push, NVC0_CB_AUX_SIZE);
549 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s));
550 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s));
551 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 4 * NVC0_MAX_BUFFERS);
552 PUSH_DATA (push, NVC0_CB_AUX_BUF_INFO(0));
553 for (i = 0; i < NVC0_MAX_BUFFERS; i++) {
554 if (nvc0->buffers[s][i].buffer) {
555 struct nv04_resource *res =
556 nv04_resource(nvc0->buffers[s][i].buffer);
557 PUSH_DATA (push, res->address + nvc0->buffers[s][i].buffer_offset);
558 PUSH_DATAh(push, res->address + nvc0->buffers[s][i].buffer_offset);
559 PUSH_DATA (push, nvc0->buffers[s][i].buffer_size);
560 PUSH_DATA (push, 0);
561 BCTX_REFN(nvc0->bufctx_3d, 3D_BUF, res, RDWR);
562 util_range_add(&res->valid_buffer_range,
563 nvc0->buffers[s][i].buffer_offset,
564 nvc0->buffers[s][i].buffer_size);
565 } else {
566 PUSH_DATA (push, 0);
567 PUSH_DATA (push, 0);
568 PUSH_DATA (push, 0);
569 PUSH_DATA (push, 0);
570 }
571 }
572 }
573
574 }
575
576 static void
577 nvc0_validate_sample_mask(struct nvc0_context *nvc0)
578 {
579 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
580
581 unsigned mask[4] =
582 {
583 nvc0->sample_mask & 0xffff,
584 nvc0->sample_mask & 0xffff,
585 nvc0->sample_mask & 0xffff,
586 nvc0->sample_mask & 0xffff
587 };
588
589 BEGIN_NVC0(push, NVC0_3D(MSAA_MASK(0)), 4);
590 PUSH_DATA (push, mask[0]);
591 PUSH_DATA (push, mask[1]);
592 PUSH_DATA (push, mask[2]);
593 PUSH_DATA (push, mask[3]);
594 }
595
596 static void
597 nvc0_validate_min_samples(struct nvc0_context *nvc0)
598 {
599 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
600 int samples;
601
602 samples = util_next_power_of_two(nvc0->min_samples);
603 if (samples > 1) {
604 // If we're using the incoming sample mask and doing sample shading, we
605 // have to do sample shading "to the max", otherwise there's no way to
606 // tell which sets of samples are covered by the current invocation.
607 if (nvc0->fragprog->fp.sample_mask_in)
608 samples = util_framebuffer_get_num_samples(&nvc0->framebuffer);
609 samples |= NVC0_3D_SAMPLE_SHADING_ENABLE;
610 }
611
612 IMMED_NVC0(push, NVC0_3D(SAMPLE_SHADING), samples);
613 }
614
615 static void
616 nvc0_validate_driverconst(struct nvc0_context *nvc0)
617 {
618 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
619 struct nvc0_screen *screen = nvc0->screen;
620 int i;
621
622 for (i = 0; i < 5; ++i) {
623 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
624 PUSH_DATA (push, NVC0_CB_AUX_SIZE);
625 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
626 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
627 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
628 PUSH_DATA (push, (15 << 4) | 1);
629 }
630
631 nvc0->dirty_cp |= NVC0_NEW_CP_DRIVERCONST;
632 }
633
634 static void
635 nvc0_validate_fp_zsa_rast(struct nvc0_context *nvc0)
636 {
637 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
638 bool rasterizer_discard;
639
640 if (nvc0->rast && nvc0->rast->pipe.rasterizer_discard) {
641 rasterizer_discard = true;
642 } else {
643 bool zs = nvc0->zsa &&
644 (nvc0->zsa->pipe.depth.enabled || nvc0->zsa->pipe.stencil[0].enabled);
645 rasterizer_discard = !zs &&
646 (!nvc0->fragprog || !nvc0->fragprog->hdr[18]);
647 }
648
649 if (rasterizer_discard != nvc0->state.rasterizer_discard) {
650 nvc0->state.rasterizer_discard = rasterizer_discard;
651 IMMED_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), !rasterizer_discard);
652 }
653 }
654
655 /* alpha test is disabled if there are no color RTs, so make sure we have at
656 * least one if alpha test is enabled. Note that this must run after
657 * nvc0_validate_fb, otherwise that will override the RT count setting.
658 */
659 static void
660 nvc0_validate_zsa_fb(struct nvc0_context *nvc0)
661 {
662 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
663
664 if (nvc0->zsa && nvc0->zsa->pipe.alpha.enabled &&
665 nvc0->framebuffer.zsbuf &&
666 nvc0->framebuffer.nr_cbufs == 0) {
667 nvc0_fb_set_null_rt(push, 0, 0);
668 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
669 PUSH_DATA (push, (076543210 << 4) | 1);
670 }
671 }
672
673 static void
674 nvc0_validate_blend_fb(struct nvc0_context *nvc0)
675 {
676 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
677 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
678 uint32_t ms = 0;
679
680 if ((!fb->nr_cbufs || !fb->cbufs[0] ||
681 !util_format_is_pure_integer(fb->cbufs[0]->format)) && nvc0->blend) {
682 if (nvc0->blend->pipe.alpha_to_coverage)
683 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE;
684 if (nvc0->blend->pipe.alpha_to_one)
685 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE;
686 }
687
688 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
689 PUSH_DATA (push, ms);
690 }
691
692 static void
693 nvc0_validate_rast_fb(struct nvc0_context *nvc0)
694 {
695 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
696 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
697 struct pipe_rasterizer_state *rast = &nvc0->rast->pipe;
698
699 if (!rast)
700 return;
701
702 if (rast->offset_units_unscaled) {
703 BEGIN_NVC0(push, NVC0_3D(POLYGON_OFFSET_UNITS), 1);
704 if (fb->zsbuf && fb->zsbuf->format == PIPE_FORMAT_Z16_UNORM)
705 PUSH_DATAf(push, rast->offset_units * (1 << 16));
706 else
707 PUSH_DATAf(push, rast->offset_units * (1 << 24));
708 }
709 }
710
711
712 static void
713 nvc0_validate_tess_state(struct nvc0_context *nvc0)
714 {
715 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
716
717 BEGIN_NVC0(push, NVC0_3D(TESS_LEVEL_OUTER(0)), 6);
718 PUSH_DATAp(push, nvc0->default_tess_outer, 4);
719 PUSH_DATAp(push, nvc0->default_tess_inner, 2);
720 }
721
722 static void
723 nvc0_switch_pipe_context(struct nvc0_context *ctx_to)
724 {
725 struct nvc0_context *ctx_from = ctx_to->screen->cur_ctx;
726 unsigned s;
727
728 if (ctx_from)
729 ctx_to->state = ctx_from->state;
730 else
731 ctx_to->state = ctx_to->screen->save_state;
732
733 ctx_to->dirty_3d = ~0;
734 ctx_to->dirty_cp = ~0;
735 ctx_to->viewports_dirty = ~0;
736 ctx_to->scissors_dirty = ~0;
737
738 for (s = 0; s < 6; ++s) {
739 ctx_to->samplers_dirty[s] = ~0;
740 ctx_to->textures_dirty[s] = ~0;
741 ctx_to->constbuf_dirty[s] = (1 << NVC0_MAX_PIPE_CONSTBUFS) - 1;
742 ctx_to->buffers_dirty[s] = ~0;
743 ctx_to->images_dirty[s] = ~0;
744 }
745
746 /* Reset tfb as the shader that owns it may have been deleted. */
747 ctx_to->state.tfb = NULL;
748
749 if (!ctx_to->vertex)
750 ctx_to->dirty_3d &= ~(NVC0_NEW_3D_VERTEX | NVC0_NEW_3D_ARRAYS);
751 if (!ctx_to->idxbuf.buffer)
752 ctx_to->dirty_3d &= ~NVC0_NEW_3D_IDXBUF;
753
754 if (!ctx_to->vertprog)
755 ctx_to->dirty_3d &= ~NVC0_NEW_3D_VERTPROG;
756 if (!ctx_to->fragprog)
757 ctx_to->dirty_3d &= ~NVC0_NEW_3D_FRAGPROG;
758
759 if (!ctx_to->blend)
760 ctx_to->dirty_3d &= ~NVC0_NEW_3D_BLEND;
761 if (!ctx_to->rast)
762 ctx_to->dirty_3d &= ~(NVC0_NEW_3D_RASTERIZER | NVC0_NEW_3D_SCISSOR);
763 if (!ctx_to->zsa)
764 ctx_to->dirty_3d &= ~NVC0_NEW_3D_ZSA;
765
766 ctx_to->screen->cur_ctx = ctx_to;
767 }
768
769 static struct nvc0_state_validate
770 validate_list_3d[] = {
771 { nvc0_validate_fb, NVC0_NEW_3D_FRAMEBUFFER },
772 { nvc0_validate_blend, NVC0_NEW_3D_BLEND },
773 { nvc0_validate_zsa, NVC0_NEW_3D_ZSA },
774 { nvc0_validate_sample_mask, NVC0_NEW_3D_SAMPLE_MASK },
775 { nvc0_validate_rasterizer, NVC0_NEW_3D_RASTERIZER },
776 { nvc0_validate_blend_colour, NVC0_NEW_3D_BLEND_COLOUR },
777 { nvc0_validate_stencil_ref, NVC0_NEW_3D_STENCIL_REF },
778 { nvc0_validate_stipple, NVC0_NEW_3D_STIPPLE },
779 { nvc0_validate_scissor, NVC0_NEW_3D_SCISSOR | NVC0_NEW_3D_RASTERIZER },
780 { nvc0_validate_viewport, NVC0_NEW_3D_VIEWPORT },
781 { nvc0_validate_window_rects, NVC0_NEW_3D_WINDOW_RECTS },
782 { nvc0_vertprog_validate, NVC0_NEW_3D_VERTPROG },
783 { nvc0_tctlprog_validate, NVC0_NEW_3D_TCTLPROG },
784 { nvc0_tevlprog_validate, NVC0_NEW_3D_TEVLPROG },
785 { nvc0_validate_tess_state, NVC0_NEW_3D_TESSFACTOR },
786 { nvc0_gmtyprog_validate, NVC0_NEW_3D_GMTYPROG },
787 { nvc0_validate_min_samples, NVC0_NEW_3D_MIN_SAMPLES |
788 NVC0_NEW_3D_FRAGPROG |
789 NVC0_NEW_3D_FRAMEBUFFER },
790 { nvc0_fragprog_validate, NVC0_NEW_3D_FRAGPROG | NVC0_NEW_3D_RASTERIZER },
791 { nvc0_validate_fp_zsa_rast, NVC0_NEW_3D_FRAGPROG | NVC0_NEW_3D_ZSA |
792 NVC0_NEW_3D_RASTERIZER },
793 { nvc0_validate_zsa_fb, NVC0_NEW_3D_ZSA | NVC0_NEW_3D_FRAMEBUFFER },
794 { nvc0_validate_blend_fb, NVC0_NEW_3D_BLEND | NVC0_NEW_3D_FRAMEBUFFER },
795 { nvc0_validate_rast_fb, NVC0_NEW_3D_RASTERIZER | NVC0_NEW_3D_FRAMEBUFFER },
796 { nvc0_validate_clip, NVC0_NEW_3D_CLIP | NVC0_NEW_3D_RASTERIZER |
797 NVC0_NEW_3D_VERTPROG |
798 NVC0_NEW_3D_TEVLPROG |
799 NVC0_NEW_3D_GMTYPROG },
800 { nvc0_constbufs_validate, NVC0_NEW_3D_CONSTBUF },
801 { nvc0_validate_textures, NVC0_NEW_3D_TEXTURES },
802 { nvc0_validate_samplers, NVC0_NEW_3D_SAMPLERS },
803 { nve4_set_tex_handles, NVC0_NEW_3D_TEXTURES | NVC0_NEW_3D_SAMPLERS },
804 { nvc0_vertex_arrays_validate, NVC0_NEW_3D_VERTEX | NVC0_NEW_3D_ARRAYS },
805 { nvc0_validate_surfaces, NVC0_NEW_3D_SURFACES },
806 { nvc0_validate_buffers, NVC0_NEW_3D_BUFFERS },
807 { nvc0_idxbuf_validate, NVC0_NEW_3D_IDXBUF },
808 { nvc0_tfb_validate, NVC0_NEW_3D_TFB_TARGETS | NVC0_NEW_3D_GMTYPROG },
809 { nvc0_validate_driverconst, NVC0_NEW_3D_DRIVERCONST },
810 };
811
812 bool
813 nvc0_state_validate(struct nvc0_context *nvc0, uint32_t mask,
814 struct nvc0_state_validate *validate_list, int size,
815 uint32_t *dirty, struct nouveau_bufctx *bufctx)
816 {
817 uint32_t state_mask;
818 int ret;
819 unsigned i;
820
821 if (nvc0->screen->cur_ctx != nvc0)
822 nvc0_switch_pipe_context(nvc0);
823
824 state_mask = *dirty & mask;
825
826 if (state_mask) {
827 for (i = 0; i < size; ++i) {
828 struct nvc0_state_validate *validate = &validate_list[i];
829
830 if (state_mask & validate->states)
831 validate->func(nvc0);
832 }
833 *dirty &= ~state_mask;
834
835 nvc0_bufctx_fence(nvc0, bufctx, false);
836 }
837
838 nouveau_pushbuf_bufctx(nvc0->base.pushbuf, bufctx);
839 ret = nouveau_pushbuf_validate(nvc0->base.pushbuf);
840
841 return !ret;
842 }
843
844 bool
845 nvc0_state_validate_3d(struct nvc0_context *nvc0, uint32_t mask)
846 {
847 bool ret;
848
849 ret = nvc0_state_validate(nvc0, mask, validate_list_3d,
850 ARRAY_SIZE(validate_list_3d), &nvc0->dirty_3d,
851 nvc0->bufctx_3d);
852
853 if (unlikely(nvc0->state.flushed)) {
854 nvc0->state.flushed = false;
855 nvc0_bufctx_fence(nvc0, nvc0->bufctx_3d, true);
856 }
857 return ret;
858 }