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Merge remote-tracking branch 'origin/master' into vulkan
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_state_validate.c
1
2 #include "util/u_format.h"
3 #include "util/u_math.h"
4
5 #include "nvc0/nvc0_context.h"
6
7 #if 0
8 static void
9 nvc0_validate_zcull(struct nvc0_context *nvc0)
10 {
11 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
12 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
13 struct nv50_surface *sf = nv50_surface(fb->zsbuf);
14 struct nv50_miptree *mt = nv50_miptree(sf->base.texture);
15 struct nouveau_bo *bo = mt->base.bo;
16 uint32_t size;
17 uint32_t offset = align(mt->total_size, 1 << 17);
18 unsigned width, height;
19
20 assert(mt->base.base.depth0 == 1 && mt->base.base.array_size < 2);
21
22 size = mt->total_size * 2;
23
24 height = align(fb->height, 32);
25 width = fb->width % 224;
26 if (width)
27 width = fb->width + (224 - width);
28 else
29 width = fb->width;
30
31 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1);
32 PUSH_DATA (push, 0);
33 BEGIN_NVC0(push, NVC0_3D(ZCULL_ADDRESS_HIGH), 2);
34 PUSH_DATAh(push, bo->offset + offset);
35 PUSH_DATA (push, bo->offset + offset);
36 offset += 1 << 17;
37 BEGIN_NVC0(push, NVC0_3D(ZCULL_LIMIT_HIGH), 2);
38 PUSH_DATAh(push, bo->offset + offset);
39 PUSH_DATA (push, bo->offset + offset);
40 BEGIN_NVC0(push, SUBC_3D(0x07e0), 2);
41 PUSH_DATA (push, size);
42 PUSH_DATA (push, size >> 16);
43 BEGIN_NVC0(push, SUBC_3D(0x15c8), 1); /* bits 0x3 */
44 PUSH_DATA (push, 2);
45 BEGIN_NVC0(push, NVC0_3D(ZCULL_WIDTH), 4);
46 PUSH_DATA (push, width);
47 PUSH_DATA (push, height);
48 PUSH_DATA (push, 1);
49 PUSH_DATA (push, 0);
50 BEGIN_NVC0(push, NVC0_3D(ZCULL_WINDOW_OFFSET_X), 2);
51 PUSH_DATA (push, 0);
52 PUSH_DATA (push, 0);
53 BEGIN_NVC0(push, NVC0_3D(ZCULL_INVALIDATE), 1);
54 PUSH_DATA (push, 0);
55 }
56 #endif
57
58 static inline void
59 nvc0_fb_set_null_rt(struct nouveau_pushbuf *push, unsigned i)
60 {
61 BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(i)), 6);
62 PUSH_DATA (push, 0);
63 PUSH_DATA (push, 0);
64 PUSH_DATA (push, 64);
65 PUSH_DATA (push, 0);
66 PUSH_DATA (push, 0);
67 PUSH_DATA (push, 0);
68 }
69
70 static void
71 nvc0_validate_fb(struct nvc0_context *nvc0)
72 {
73 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
74 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
75 unsigned i, ms;
76 unsigned ms_mode = NVC0_3D_MULTISAMPLE_MODE_MS1;
77 bool serialize = false;
78
79 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_FB);
80
81 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
82 PUSH_DATA (push, (076543210 << 4) | fb->nr_cbufs);
83 BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
84 PUSH_DATA (push, fb->width << 16);
85 PUSH_DATA (push, fb->height << 16);
86
87 for (i = 0; i < fb->nr_cbufs; ++i) {
88 struct nv50_surface *sf;
89 struct nv04_resource *res;
90 struct nouveau_bo *bo;
91
92 if (!fb->cbufs[i]) {
93 nvc0_fb_set_null_rt(push, i);
94 continue;
95 }
96
97 sf = nv50_surface(fb->cbufs[i]);
98 res = nv04_resource(sf->base.texture);
99 bo = res->bo;
100
101 BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(i)), 9);
102 PUSH_DATAh(push, res->address + sf->offset);
103 PUSH_DATA (push, res->address + sf->offset);
104 if (likely(nouveau_bo_memtype(bo))) {
105 struct nv50_miptree *mt = nv50_miptree(sf->base.texture);
106
107 assert(sf->base.texture->target != PIPE_BUFFER);
108
109 PUSH_DATA(push, sf->width);
110 PUSH_DATA(push, sf->height);
111 PUSH_DATA(push, nvc0_format_table[sf->base.format].rt);
112 PUSH_DATA(push, (mt->layout_3d << 16) |
113 mt->level[sf->base.u.tex.level].tile_mode);
114 PUSH_DATA(push, sf->base.u.tex.first_layer + sf->depth);
115 PUSH_DATA(push, mt->layer_stride >> 2);
116 PUSH_DATA(push, sf->base.u.tex.first_layer);
117
118 ms_mode = mt->ms_mode;
119 } else {
120 if (res->base.target == PIPE_BUFFER) {
121 PUSH_DATA(push, 262144);
122 PUSH_DATA(push, 1);
123 } else {
124 PUSH_DATA(push, nv50_miptree(sf->base.texture)->level[0].pitch);
125 PUSH_DATA(push, sf->height);
126 }
127 PUSH_DATA(push, nvc0_format_table[sf->base.format].rt);
128 PUSH_DATA(push, 1 << 12);
129 PUSH_DATA(push, 1);
130 PUSH_DATA(push, 0);
131 PUSH_DATA(push, 0);
132
133 nvc0_resource_fence(res, NOUVEAU_BO_WR);
134
135 assert(!fb->zsbuf);
136 }
137
138 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_READING)
139 serialize = true;
140 res->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
141 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING;
142
143 /* only register for writing, otherwise we'd always serialize here */
144 BCTX_REFN(nvc0->bufctx_3d, 3D_FB, res, WR);
145 }
146
147 if (fb->zsbuf) {
148 struct nv50_miptree *mt = nv50_miptree(fb->zsbuf->texture);
149 struct nv50_surface *sf = nv50_surface(fb->zsbuf);
150 int unk = mt->base.base.target == PIPE_TEXTURE_2D;
151
152 BEGIN_NVC0(push, NVC0_3D(ZETA_ADDRESS_HIGH), 5);
153 PUSH_DATAh(push, mt->base.address + sf->offset);
154 PUSH_DATA (push, mt->base.address + sf->offset);
155 PUSH_DATA (push, nvc0_format_table[fb->zsbuf->format].rt);
156 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
157 PUSH_DATA (push, mt->layer_stride >> 2);
158 BEGIN_NVC0(push, NVC0_3D(ZETA_ENABLE), 1);
159 PUSH_DATA (push, 1);
160 BEGIN_NVC0(push, NVC0_3D(ZETA_HORIZ), 3);
161 PUSH_DATA (push, sf->width);
162 PUSH_DATA (push, sf->height);
163 PUSH_DATA (push, (unk << 16) |
164 (sf->base.u.tex.first_layer + sf->depth));
165 BEGIN_NVC0(push, NVC0_3D(ZETA_BASE_LAYER), 1);
166 PUSH_DATA (push, sf->base.u.tex.first_layer);
167
168 ms_mode = mt->ms_mode;
169
170 if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING)
171 serialize = true;
172 mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
173 mt->base.status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING;
174
175 BCTX_REFN(nvc0->bufctx_3d, 3D_FB, &mt->base, WR);
176 } else {
177 BEGIN_NVC0(push, NVC0_3D(ZETA_ENABLE), 1);
178 PUSH_DATA (push, 0);
179 }
180
181 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), ms_mode);
182
183 ms = 1 << ms_mode;
184 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
185 PUSH_DATA (push, 1024);
186 PUSH_DATAh(push, nvc0->screen->uniform_bo->offset + (6 << 16) + (4 << 10));
187 PUSH_DATA (push, nvc0->screen->uniform_bo->offset + (6 << 16) + (4 << 10));
188 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * ms);
189 PUSH_DATA (push, 256 + 128);
190 for (i = 0; i < ms; i++) {
191 float xy[2];
192 nvc0->base.pipe.get_sample_position(&nvc0->base.pipe, ms, i, xy);
193 PUSH_DATAf(push, xy[0]);
194 PUSH_DATAf(push, xy[1]);
195 }
196
197 if (serialize)
198 IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
199
200 NOUVEAU_DRV_STAT(&nvc0->screen->base, gpu_serialize_count, serialize);
201 }
202
203 static void
204 nvc0_validate_blend_colour(struct nvc0_context *nvc0)
205 {
206 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
207
208 BEGIN_NVC0(push, NVC0_3D(BLEND_COLOR(0)), 4);
209 PUSH_DATAf(push, nvc0->blend_colour.color[0]);
210 PUSH_DATAf(push, nvc0->blend_colour.color[1]);
211 PUSH_DATAf(push, nvc0->blend_colour.color[2]);
212 PUSH_DATAf(push, nvc0->blend_colour.color[3]);
213 }
214
215 static void
216 nvc0_validate_stencil_ref(struct nvc0_context *nvc0)
217 {
218 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
219 const ubyte *ref = &nvc0->stencil_ref.ref_value[0];
220
221 IMMED_NVC0(push, NVC0_3D(STENCIL_FRONT_FUNC_REF), ref[0]);
222 IMMED_NVC0(push, NVC0_3D(STENCIL_BACK_FUNC_REF), ref[1]);
223 }
224
225 static void
226 nvc0_validate_stipple(struct nvc0_context *nvc0)
227 {
228 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
229 unsigned i;
230
231 BEGIN_NVC0(push, NVC0_3D(POLYGON_STIPPLE_PATTERN(0)), 32);
232 for (i = 0; i < 32; ++i)
233 PUSH_DATA(push, util_bswap32(nvc0->stipple.stipple[i]));
234 }
235
236 static void
237 nvc0_validate_scissor(struct nvc0_context *nvc0)
238 {
239 int i;
240 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
241
242 if (!(nvc0->dirty_3d & NVC0_NEW_3D_SCISSOR) &&
243 nvc0->rast->pipe.scissor == nvc0->state.scissor)
244 return;
245
246 if (nvc0->state.scissor != nvc0->rast->pipe.scissor)
247 nvc0->scissors_dirty = (1 << NVC0_MAX_VIEWPORTS) - 1;
248
249 nvc0->state.scissor = nvc0->rast->pipe.scissor;
250
251 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
252 struct pipe_scissor_state *s = &nvc0->scissors[i];
253 if (!(nvc0->scissors_dirty & (1 << i)))
254 continue;
255
256 BEGIN_NVC0(push, NVC0_3D(SCISSOR_HORIZ(i)), 2);
257 if (nvc0->rast->pipe.scissor) {
258 PUSH_DATA(push, (s->maxx << 16) | s->minx);
259 PUSH_DATA(push, (s->maxy << 16) | s->miny);
260 } else {
261 PUSH_DATA(push, (0xffff << 16) | 0);
262 PUSH_DATA(push, (0xffff << 16) | 0);
263 }
264 }
265 nvc0->scissors_dirty = 0;
266 }
267
268 static void
269 nvc0_validate_viewport(struct nvc0_context *nvc0)
270 {
271 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
272 int x, y, w, h, i;
273 float zmin, zmax;
274
275 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
276 struct pipe_viewport_state *vp = &nvc0->viewports[i];
277
278 if (!(nvc0->viewports_dirty & (1 << i)))
279 continue;
280
281 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSLATE_X(i)), 3);
282 PUSH_DATAf(push, vp->translate[0]);
283 PUSH_DATAf(push, vp->translate[1]);
284 PUSH_DATAf(push, vp->translate[2]);
285
286 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_SCALE_X(i)), 3);
287 PUSH_DATAf(push, vp->scale[0]);
288 PUSH_DATAf(push, vp->scale[1]);
289 PUSH_DATAf(push, vp->scale[2]);
290
291 /* now set the viewport rectangle to viewport dimensions for clipping */
292
293 x = util_iround(MAX2(0.0f, vp->translate[0] - fabsf(vp->scale[0])));
294 y = util_iround(MAX2(0.0f, vp->translate[1] - fabsf(vp->scale[1])));
295 w = util_iround(vp->translate[0] + fabsf(vp->scale[0])) - x;
296 h = util_iround(vp->translate[1] + fabsf(vp->scale[1])) - y;
297
298 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_HORIZ(i)), 2);
299 PUSH_DATA (push, (w << 16) | x);
300 PUSH_DATA (push, (h << 16) | y);
301
302 zmin = vp->translate[2] - fabsf(vp->scale[2]);
303 zmax = vp->translate[2] + fabsf(vp->scale[2]);
304
305 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
306 PUSH_DATAf(push, zmin);
307 PUSH_DATAf(push, zmax);
308 }
309 nvc0->viewports_dirty = 0;
310 }
311
312 static inline void
313 nvc0_upload_uclip_planes(struct nvc0_context *nvc0, unsigned s)
314 {
315 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
316 struct nouveau_bo *bo = nvc0->screen->uniform_bo;
317
318 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
319 PUSH_DATA (push, 1024);
320 PUSH_DATAh(push, bo->offset + (6 << 16) + (s << 10));
321 PUSH_DATA (push, bo->offset + (6 << 16) + (s << 10));
322 BEGIN_1IC0(push, NVC0_3D(CB_POS), PIPE_MAX_CLIP_PLANES * 4 + 1);
323 PUSH_DATA (push, 256);
324 PUSH_DATAp(push, &nvc0->clip.ucp[0][0], PIPE_MAX_CLIP_PLANES * 4);
325 }
326
327 static inline void
328 nvc0_check_program_ucps(struct nvc0_context *nvc0,
329 struct nvc0_program *vp, uint8_t mask)
330 {
331 const unsigned n = util_logbase2(mask) + 1;
332
333 if (vp->vp.num_ucps >= n)
334 return;
335 nvc0_program_destroy(nvc0, vp);
336
337 vp->vp.num_ucps = n;
338 if (likely(vp == nvc0->vertprog))
339 nvc0_vertprog_validate(nvc0);
340 else
341 if (likely(vp == nvc0->gmtyprog))
342 nvc0_gmtyprog_validate(nvc0);
343 else
344 nvc0_tevlprog_validate(nvc0);
345 }
346
347 static void
348 nvc0_validate_clip(struct nvc0_context *nvc0)
349 {
350 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
351 struct nvc0_program *vp;
352 unsigned stage;
353 uint8_t clip_enable = nvc0->rast->pipe.clip_plane_enable;
354
355 if (nvc0->gmtyprog) {
356 stage = 3;
357 vp = nvc0->gmtyprog;
358 } else
359 if (nvc0->tevlprog) {
360 stage = 2;
361 vp = nvc0->tevlprog;
362 } else {
363 stage = 0;
364 vp = nvc0->vertprog;
365 }
366
367 if (clip_enable && vp->vp.num_ucps < PIPE_MAX_CLIP_PLANES)
368 nvc0_check_program_ucps(nvc0, vp, clip_enable);
369
370 if (nvc0->dirty_3d & (NVC0_NEW_3D_CLIP | (NVC0_NEW_3D_VERTPROG << stage)))
371 if (vp->vp.num_ucps > 0 && vp->vp.num_ucps <= PIPE_MAX_CLIP_PLANES)
372 nvc0_upload_uclip_planes(nvc0, stage);
373
374 clip_enable &= vp->vp.clip_enable;
375
376 if (nvc0->state.clip_enable != clip_enable) {
377 nvc0->state.clip_enable = clip_enable;
378 IMMED_NVC0(push, NVC0_3D(CLIP_DISTANCE_ENABLE), clip_enable);
379 }
380 if (nvc0->state.clip_mode != vp->vp.clip_mode) {
381 nvc0->state.clip_mode = vp->vp.clip_mode;
382 BEGIN_NVC0(push, NVC0_3D(CLIP_DISTANCE_MODE), 1);
383 PUSH_DATA (push, vp->vp.clip_mode);
384 }
385 }
386
387 static void
388 nvc0_validate_blend(struct nvc0_context *nvc0)
389 {
390 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
391
392 PUSH_SPACE(push, nvc0->blend->size);
393 PUSH_DATAp(push, nvc0->blend->state, nvc0->blend->size);
394 }
395
396 static void
397 nvc0_validate_zsa(struct nvc0_context *nvc0)
398 {
399 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
400
401 PUSH_SPACE(push, nvc0->zsa->size);
402 PUSH_DATAp(push, nvc0->zsa->state, nvc0->zsa->size);
403 }
404
405 static void
406 nvc0_validate_rasterizer(struct nvc0_context *nvc0)
407 {
408 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
409
410 PUSH_SPACE(push, nvc0->rast->size);
411 PUSH_DATAp(push, nvc0->rast->state, nvc0->rast->size);
412 }
413
414 static void
415 nvc0_constbufs_validate(struct nvc0_context *nvc0)
416 {
417 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
418 unsigned s;
419
420 for (s = 0; s < 5; ++s) {
421 while (nvc0->constbuf_dirty[s]) {
422 int i = ffs(nvc0->constbuf_dirty[s]) - 1;
423 nvc0->constbuf_dirty[s] &= ~(1 << i);
424
425 if (nvc0->constbuf[s][i].user) {
426 struct nouveau_bo *bo = nvc0->screen->uniform_bo;
427 const unsigned base = s << 16;
428 const unsigned size = nvc0->constbuf[s][0].size;
429 assert(i == 0); /* we really only want OpenGL uniforms here */
430 assert(nvc0->constbuf[s][0].u.data);
431
432 if (nvc0->state.uniform_buffer_bound[s] < size) {
433 nvc0->state.uniform_buffer_bound[s] = align(size, 0x100);
434
435 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
436 PUSH_DATA (push, nvc0->state.uniform_buffer_bound[s]);
437 PUSH_DATAh(push, bo->offset + base);
438 PUSH_DATA (push, bo->offset + base);
439 BEGIN_NVC0(push, NVC0_3D(CB_BIND(s)), 1);
440 PUSH_DATA (push, (0 << 4) | 1);
441 }
442 nvc0_cb_bo_push(&nvc0->base, bo, NV_VRAM_DOMAIN(&nvc0->screen->base),
443 base, nvc0->state.uniform_buffer_bound[s],
444 0, (size + 3) / 4,
445 nvc0->constbuf[s][0].u.data);
446 } else {
447 struct nv04_resource *res =
448 nv04_resource(nvc0->constbuf[s][i].u.buf);
449 if (res) {
450 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
451 PUSH_DATA (push, nvc0->constbuf[s][i].size);
452 PUSH_DATAh(push, res->address + nvc0->constbuf[s][i].offset);
453 PUSH_DATA (push, res->address + nvc0->constbuf[s][i].offset);
454 BEGIN_NVC0(push, NVC0_3D(CB_BIND(s)), 1);
455 PUSH_DATA (push, (i << 4) | 1);
456
457 BCTX_REFN(nvc0->bufctx_3d, 3D_CB(s, i), res, RD);
458
459 nvc0->cb_dirty = 1; /* Force cache flush for UBO. */
460 res->cb_bindings[s] |= 1 << i;
461 } else {
462 BEGIN_NVC0(push, NVC0_3D(CB_BIND(s)), 1);
463 PUSH_DATA (push, (i << 4) | 0);
464 }
465 if (i == 0)
466 nvc0->state.uniform_buffer_bound[s] = 0;
467 }
468 }
469 }
470
471 /* Invalidate all COMPUTE constbufs because they are aliased with 3D. */
472 nvc0->dirty_cp |= NVC0_NEW_CP_CONSTBUF;
473 nvc0->constbuf_dirty[5] |= nvc0->constbuf_valid[5];
474 nvc0->state.uniform_buffer_bound[5] = 0;
475 }
476
477 static void
478 nvc0_validate_buffers(struct nvc0_context *nvc0)
479 {
480 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
481 int i, s;
482
483 for (s = 0; s < 5; s++) {
484 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
485 PUSH_DATA (push, 1024);
486 PUSH_DATAh(push, nvc0->screen->uniform_bo->offset + (6 << 16) + (s << 10));
487 PUSH_DATA (push, nvc0->screen->uniform_bo->offset + (6 << 16) + (s << 10));
488 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 4 * NVC0_MAX_BUFFERS);
489 PUSH_DATA (push, 512);
490 for (i = 0; i < NVC0_MAX_BUFFERS; i++) {
491 if (nvc0->buffers[s][i].buffer) {
492 struct nv04_resource *res =
493 nv04_resource(nvc0->buffers[s][i].buffer);
494 PUSH_DATA (push, res->address + nvc0->buffers[s][i].buffer_offset);
495 PUSH_DATAh(push, res->address + nvc0->buffers[s][i].buffer_offset);
496 PUSH_DATA (push, nvc0->buffers[s][i].buffer_size);
497 PUSH_DATA (push, 0);
498 BCTX_REFN(nvc0->bufctx_3d, 3D_BUF, res, RDWR);
499 } else {
500 PUSH_DATA (push, 0);
501 PUSH_DATA (push, 0);
502 PUSH_DATA (push, 0);
503 PUSH_DATA (push, 0);
504 }
505 }
506 }
507
508 }
509
510 static void
511 nvc0_validate_sample_mask(struct nvc0_context *nvc0)
512 {
513 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
514
515 unsigned mask[4] =
516 {
517 nvc0->sample_mask & 0xffff,
518 nvc0->sample_mask & 0xffff,
519 nvc0->sample_mask & 0xffff,
520 nvc0->sample_mask & 0xffff
521 };
522
523 BEGIN_NVC0(push, NVC0_3D(MSAA_MASK(0)), 4);
524 PUSH_DATA (push, mask[0]);
525 PUSH_DATA (push, mask[1]);
526 PUSH_DATA (push, mask[2]);
527 PUSH_DATA (push, mask[3]);
528 }
529
530 static void
531 nvc0_validate_min_samples(struct nvc0_context *nvc0)
532 {
533 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
534 int samples;
535
536 samples = util_next_power_of_two(nvc0->min_samples);
537 if (samples > 1)
538 samples |= NVC0_3D_SAMPLE_SHADING_ENABLE;
539
540 IMMED_NVC0(push, NVC0_3D(SAMPLE_SHADING), samples);
541 }
542
543 static void
544 nvc0_validate_driverconst(struct nvc0_context *nvc0)
545 {
546 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
547 struct nvc0_screen *screen = nvc0->screen;
548 int i;
549
550 for (i = 0; i < 5; ++i) {
551 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
552 PUSH_DATA (push, 1024);
553 PUSH_DATAh(push, screen->uniform_bo->offset + (6 << 16) + (i << 10));
554 PUSH_DATA (push, screen->uniform_bo->offset + (6 << 16) + (i << 10));
555 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
556 PUSH_DATA (push, (15 << 4) | 1);
557 }
558
559 nvc0->dirty_cp |= NVC0_NEW_CP_DRIVERCONST;
560 }
561
562 void
563 nvc0_validate_global_residents(struct nvc0_context *nvc0,
564 struct nouveau_bufctx *bctx, int bin)
565 {
566 unsigned i;
567
568 for (i = 0; i < nvc0->global_residents.size / sizeof(struct pipe_resource *);
569 ++i) {
570 struct pipe_resource *res = *util_dynarray_element(
571 &nvc0->global_residents, struct pipe_resource *, i);
572 if (res)
573 nvc0_add_resident(bctx, bin, nv04_resource(res), NOUVEAU_BO_RDWR);
574 }
575 }
576
577 static void
578 nvc0_validate_derived_1(struct nvc0_context *nvc0)
579 {
580 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
581 bool rasterizer_discard;
582
583 if (nvc0->rast && nvc0->rast->pipe.rasterizer_discard) {
584 rasterizer_discard = true;
585 } else {
586 bool zs = nvc0->zsa &&
587 (nvc0->zsa->pipe.depth.enabled || nvc0->zsa->pipe.stencil[0].enabled);
588 rasterizer_discard = !zs &&
589 (!nvc0->fragprog || !nvc0->fragprog->hdr[18]);
590 }
591
592 if (rasterizer_discard != nvc0->state.rasterizer_discard) {
593 nvc0->state.rasterizer_discard = rasterizer_discard;
594 IMMED_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), !rasterizer_discard);
595 }
596 }
597
598 /* alpha test is disabled if there are no color RTs, so make sure we have at
599 * least one if alpha test is enabled. Note that this must run after
600 * nvc0_validate_fb, otherwise that will override the RT count setting.
601 */
602 static void
603 nvc0_validate_derived_2(struct nvc0_context *nvc0)
604 {
605 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
606
607 if (nvc0->zsa && nvc0->zsa->pipe.alpha.enabled &&
608 nvc0->framebuffer.nr_cbufs == 0) {
609 nvc0_fb_set_null_rt(push, 0);
610 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
611 PUSH_DATA (push, (076543210 << 4) | 1);
612 }
613 }
614
615 static void
616 nvc0_validate_derived_3(struct nvc0_context *nvc0)
617 {
618 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
619 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
620 uint32_t ms = 0;
621
622 if ((!fb->nr_cbufs || !fb->cbufs[0] ||
623 !util_format_is_pure_integer(fb->cbufs[0]->format)) && nvc0->blend) {
624 if (nvc0->blend->pipe.alpha_to_coverage)
625 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE;
626 if (nvc0->blend->pipe.alpha_to_one)
627 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE;
628 }
629
630 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
631 PUSH_DATA (push, ms);
632 }
633
634 static void
635 nvc0_validate_tess_state(struct nvc0_context *nvc0)
636 {
637 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
638
639 BEGIN_NVC0(push, NVC0_3D(TESS_LEVEL_OUTER(0)), 6);
640 PUSH_DATAp(push, nvc0->default_tess_outer, 4);
641 PUSH_DATAp(push, nvc0->default_tess_inner, 2);
642 }
643
644 static void
645 nvc0_switch_pipe_context(struct nvc0_context *ctx_to)
646 {
647 struct nvc0_context *ctx_from = ctx_to->screen->cur_ctx;
648 unsigned s;
649
650 if (ctx_from)
651 ctx_to->state = ctx_from->state;
652 else
653 ctx_to->state = ctx_to->screen->save_state;
654
655 ctx_to->dirty_3d = ~0;
656 ctx_to->dirty_cp = ~0;
657 ctx_to->viewports_dirty = ~0;
658 ctx_to->scissors_dirty = ~0;
659
660 for (s = 0; s < 6; ++s) {
661 ctx_to->samplers_dirty[s] = ~0;
662 ctx_to->textures_dirty[s] = ~0;
663 ctx_to->constbuf_dirty[s] = (1 << NVC0_MAX_PIPE_CONSTBUFS) - 1;
664 ctx_to->buffers_dirty[s] = ~0;
665 }
666
667 /* Reset tfb as the shader that owns it may have been deleted. */
668 ctx_to->state.tfb = NULL;
669
670 if (!ctx_to->vertex)
671 ctx_to->dirty_3d &= ~(NVC0_NEW_3D_VERTEX | NVC0_NEW_3D_ARRAYS);
672 if (!ctx_to->idxbuf.buffer)
673 ctx_to->dirty_3d &= ~NVC0_NEW_3D_IDXBUF;
674
675 if (!ctx_to->vertprog)
676 ctx_to->dirty_3d &= ~NVC0_NEW_3D_VERTPROG;
677 if (!ctx_to->fragprog)
678 ctx_to->dirty_3d &= ~NVC0_NEW_3D_FRAGPROG;
679
680 if (!ctx_to->blend)
681 ctx_to->dirty_3d &= ~NVC0_NEW_3D_BLEND;
682 if (!ctx_to->rast)
683 ctx_to->dirty_3d &= ~(NVC0_NEW_3D_RASTERIZER | NVC0_NEW_3D_SCISSOR);
684 if (!ctx_to->zsa)
685 ctx_to->dirty_3d &= ~NVC0_NEW_3D_ZSA;
686
687 ctx_to->screen->cur_ctx = ctx_to;
688 }
689
690 static struct state_validate {
691 void (*func)(struct nvc0_context *);
692 uint32_t states;
693 } validate_list[] = {
694 { nvc0_validate_fb, NVC0_NEW_3D_FRAMEBUFFER },
695 { nvc0_validate_blend, NVC0_NEW_3D_BLEND },
696 { nvc0_validate_zsa, NVC0_NEW_3D_ZSA },
697 { nvc0_validate_sample_mask, NVC0_NEW_3D_SAMPLE_MASK },
698 { nvc0_validate_rasterizer, NVC0_NEW_3D_RASTERIZER },
699 { nvc0_validate_blend_colour, NVC0_NEW_3D_BLEND_COLOUR },
700 { nvc0_validate_stencil_ref, NVC0_NEW_3D_STENCIL_REF },
701 { nvc0_validate_stipple, NVC0_NEW_3D_STIPPLE },
702 { nvc0_validate_scissor, NVC0_NEW_3D_SCISSOR | NVC0_NEW_3D_RASTERIZER },
703 { nvc0_validate_viewport, NVC0_NEW_3D_VIEWPORT },
704 { nvc0_vertprog_validate, NVC0_NEW_3D_VERTPROG },
705 { nvc0_tctlprog_validate, NVC0_NEW_3D_TCTLPROG },
706 { nvc0_tevlprog_validate, NVC0_NEW_3D_TEVLPROG },
707 { nvc0_validate_tess_state, NVC0_NEW_3D_TESSFACTOR },
708 { nvc0_gmtyprog_validate, NVC0_NEW_3D_GMTYPROG },
709 { nvc0_fragprog_validate, NVC0_NEW_3D_FRAGPROG | NVC0_NEW_3D_RASTERIZER },
710 { nvc0_validate_derived_1, NVC0_NEW_3D_FRAGPROG | NVC0_NEW_3D_ZSA |
711 NVC0_NEW_3D_RASTERIZER },
712 { nvc0_validate_derived_2, NVC0_NEW_3D_ZSA | NVC0_NEW_3D_FRAMEBUFFER },
713 { nvc0_validate_derived_3, NVC0_NEW_3D_BLEND | NVC0_NEW_3D_FRAMEBUFFER },
714 { nvc0_validate_clip, NVC0_NEW_3D_CLIP | NVC0_NEW_3D_RASTERIZER |
715 NVC0_NEW_3D_VERTPROG |
716 NVC0_NEW_3D_TEVLPROG |
717 NVC0_NEW_3D_GMTYPROG },
718 { nvc0_constbufs_validate, NVC0_NEW_3D_CONSTBUF },
719 { nvc0_validate_textures, NVC0_NEW_3D_TEXTURES },
720 { nvc0_validate_samplers, NVC0_NEW_3D_SAMPLERS },
721 { nve4_set_tex_handles, NVC0_NEW_3D_TEXTURES | NVC0_NEW_3D_SAMPLERS },
722 { nvc0_vertex_arrays_validate, NVC0_NEW_3D_VERTEX | NVC0_NEW_3D_ARRAYS },
723 { nvc0_validate_surfaces, NVC0_NEW_3D_SURFACES },
724 { nvc0_validate_buffers, NVC0_NEW_3D_BUFFERS },
725 { nvc0_idxbuf_validate, NVC0_NEW_3D_IDXBUF },
726 { nvc0_tfb_validate, NVC0_NEW_3D_TFB_TARGETS | NVC0_NEW_3D_GMTYPROG },
727 { nvc0_validate_min_samples, NVC0_NEW_3D_MIN_SAMPLES },
728 { nvc0_validate_driverconst, NVC0_NEW_3D_DRIVERCONST },
729 };
730
731 bool
732 nvc0_state_validate(struct nvc0_context *nvc0, uint32_t mask)
733 {
734 uint32_t state_mask;
735 int ret;
736 unsigned i;
737
738 if (nvc0->screen->cur_ctx != nvc0)
739 nvc0_switch_pipe_context(nvc0);
740
741 state_mask = nvc0->dirty_3d & mask;
742
743 if (state_mask) {
744 for (i = 0; i < ARRAY_SIZE(validate_list); ++i) {
745 struct state_validate *validate = &validate_list[i];
746
747 if (state_mask & validate->states)
748 validate->func(nvc0);
749 }
750 nvc0->dirty_3d &= ~state_mask;
751
752 nvc0_bufctx_fence(nvc0, nvc0->bufctx_3d, false);
753 }
754
755 nouveau_pushbuf_bufctx(nvc0->base.pushbuf, nvc0->bufctx_3d);
756 ret = nouveau_pushbuf_validate(nvc0->base.pushbuf);
757
758 if (unlikely(nvc0->state.flushed)) {
759 nvc0->state.flushed = false;
760 nvc0_bufctx_fence(nvc0, nvc0->bufctx_3d, true);
761 }
762 return !ret;
763 }