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nvc0: add support for PIPE_CAP_SAMPLE_SHADING
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_state_validate.c
1
2 #include "util/u_math.h"
3
4 #include "nvc0/nvc0_context.h"
5 #include "nv50/nv50_defs.xml.h"
6
7 #if 0
8 static void
9 nvc0_validate_zcull(struct nvc0_context *nvc0)
10 {
11 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
12 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
13 struct nv50_surface *sf = nv50_surface(fb->zsbuf);
14 struct nv50_miptree *mt = nv50_miptree(sf->base.texture);
15 struct nouveau_bo *bo = mt->base.bo;
16 uint32_t size;
17 uint32_t offset = align(mt->total_size, 1 << 17);
18 unsigned width, height;
19
20 assert(mt->base.base.depth0 == 1 && mt->base.base.array_size < 2);
21
22 size = mt->total_size * 2;
23
24 height = align(fb->height, 32);
25 width = fb->width % 224;
26 if (width)
27 width = fb->width + (224 - width);
28 else
29 width = fb->width;
30
31 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1);
32 PUSH_DATA (push, 0);
33 BEGIN_NVC0(push, NVC0_3D(ZCULL_ADDRESS_HIGH), 2);
34 PUSH_DATAh(push, bo->offset + offset);
35 PUSH_DATA (push, bo->offset + offset);
36 offset += 1 << 17;
37 BEGIN_NVC0(push, NVC0_3D(ZCULL_LIMIT_HIGH), 2);
38 PUSH_DATAh(push, bo->offset + offset);
39 PUSH_DATA (push, bo->offset + offset);
40 BEGIN_NVC0(push, SUBC_3D(0x07e0), 2);
41 PUSH_DATA (push, size);
42 PUSH_DATA (push, size >> 16);
43 BEGIN_NVC0(push, SUBC_3D(0x15c8), 1); /* bits 0x3 */
44 PUSH_DATA (push, 2);
45 BEGIN_NVC0(push, NVC0_3D(ZCULL_WIDTH), 4);
46 PUSH_DATA (push, width);
47 PUSH_DATA (push, height);
48 PUSH_DATA (push, 1);
49 PUSH_DATA (push, 0);
50 BEGIN_NVC0(push, NVC0_3D(ZCULL_WINDOW_OFFSET_X), 2);
51 PUSH_DATA (push, 0);
52 PUSH_DATA (push, 0);
53 BEGIN_NVC0(push, NVC0_3D(ZCULL_INVALIDATE), 1);
54 PUSH_DATA (push, 0);
55 }
56 #endif
57
58 static INLINE void
59 nvc0_fb_set_null_rt(struct nouveau_pushbuf *push, unsigned i)
60 {
61 BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(i)), 6);
62 PUSH_DATA (push, 0);
63 PUSH_DATA (push, 0);
64 PUSH_DATA (push, 64);
65 PUSH_DATA (push, 0);
66 PUSH_DATA (push, NV50_SURFACE_FORMAT_NONE);
67 PUSH_DATA (push, 0);
68 }
69
70 static void
71 nvc0_validate_fb(struct nvc0_context *nvc0)
72 {
73 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
74 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
75 unsigned i, ms;
76 unsigned ms_mode = NVC0_3D_MULTISAMPLE_MODE_MS1;
77 boolean serialize = FALSE;
78
79 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_FB);
80
81 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
82 PUSH_DATA (push, (076543210 << 4) | fb->nr_cbufs);
83 BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
84 PUSH_DATA (push, fb->width << 16);
85 PUSH_DATA (push, fb->height << 16);
86
87 for (i = 0; i < fb->nr_cbufs; ++i) {
88 struct nv50_surface *sf;
89 struct nv04_resource *res;
90 struct nouveau_bo *bo;
91
92 if (!fb->cbufs[i]) {
93 nvc0_fb_set_null_rt(push, i);
94 continue;
95 }
96
97 sf = nv50_surface(fb->cbufs[i]);
98 res = nv04_resource(sf->base.texture);
99 bo = res->bo;
100
101 BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(i)), 9);
102 PUSH_DATAh(push, res->address + sf->offset);
103 PUSH_DATA (push, res->address + sf->offset);
104 if (likely(nouveau_bo_memtype(bo))) {
105 struct nv50_miptree *mt = nv50_miptree(sf->base.texture);
106
107 assert(sf->base.texture->target != PIPE_BUFFER);
108
109 PUSH_DATA(push, sf->width);
110 PUSH_DATA(push, sf->height);
111 PUSH_DATA(push, nvc0_format_table[sf->base.format].rt);
112 PUSH_DATA(push, (mt->layout_3d << 16) |
113 mt->level[sf->base.u.tex.level].tile_mode);
114 PUSH_DATA(push, sf->base.u.tex.first_layer + sf->depth);
115 PUSH_DATA(push, mt->layer_stride >> 2);
116 PUSH_DATA(push, sf->base.u.tex.first_layer);
117
118 ms_mode = mt->ms_mode;
119 } else {
120 if (res->base.target == PIPE_BUFFER) {
121 PUSH_DATA(push, 262144);
122 PUSH_DATA(push, 1);
123 } else {
124 PUSH_DATA(push, nv50_miptree(sf->base.texture)->level[0].pitch);
125 PUSH_DATA(push, sf->height);
126 }
127 PUSH_DATA(push, nvc0_format_table[sf->base.format].rt);
128 PUSH_DATA(push, 1 << 12);
129 PUSH_DATA(push, 1);
130 PUSH_DATA(push, 0);
131 PUSH_DATA(push, 0);
132
133 nvc0_resource_fence(res, NOUVEAU_BO_WR);
134
135 assert(!fb->zsbuf);
136 }
137
138 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_READING)
139 serialize = TRUE;
140 res->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
141 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING;
142
143 /* only register for writing, otherwise we'd always serialize here */
144 BCTX_REFN(nvc0->bufctx_3d, FB, res, WR);
145 }
146
147 if (fb->zsbuf) {
148 struct nv50_miptree *mt = nv50_miptree(fb->zsbuf->texture);
149 struct nv50_surface *sf = nv50_surface(fb->zsbuf);
150 int unk = mt->base.base.target == PIPE_TEXTURE_2D;
151
152 BEGIN_NVC0(push, NVC0_3D(ZETA_ADDRESS_HIGH), 5);
153 PUSH_DATAh(push, mt->base.address + sf->offset);
154 PUSH_DATA (push, mt->base.address + sf->offset);
155 PUSH_DATA (push, nvc0_format_table[fb->zsbuf->format].rt);
156 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
157 PUSH_DATA (push, mt->layer_stride >> 2);
158 BEGIN_NVC0(push, NVC0_3D(ZETA_ENABLE), 1);
159 PUSH_DATA (push, 1);
160 BEGIN_NVC0(push, NVC0_3D(ZETA_HORIZ), 3);
161 PUSH_DATA (push, sf->width);
162 PUSH_DATA (push, sf->height);
163 PUSH_DATA (push, (unk << 16) |
164 (sf->base.u.tex.first_layer + sf->depth));
165 BEGIN_NVC0(push, NVC0_3D(ZETA_BASE_LAYER), 1);
166 PUSH_DATA (push, sf->base.u.tex.first_layer);
167
168 ms_mode = mt->ms_mode;
169
170 if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING)
171 serialize = TRUE;
172 mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
173 mt->base.status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING;
174
175 BCTX_REFN(nvc0->bufctx_3d, FB, &mt->base, WR);
176 } else {
177 BEGIN_NVC0(push, NVC0_3D(ZETA_ENABLE), 1);
178 PUSH_DATA (push, 0);
179 }
180
181 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), ms_mode);
182
183 ms = 1 << ms_mode;
184 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
185 PUSH_DATA (push, 512);
186 PUSH_DATAh(push, nvc0->screen->uniform_bo->offset + (5 << 16) + (4 << 9));
187 PUSH_DATA (push, nvc0->screen->uniform_bo->offset + (5 << 16) + (4 << 9));
188 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * ms);
189 PUSH_DATA (push, 256 + 128);
190 for (i = 0; i < ms; i++) {
191 float xy[2];
192 nvc0->base.pipe.get_sample_position(&nvc0->base.pipe, ms, i, xy);
193 PUSH_DATAf(push, xy[0]);
194 PUSH_DATAf(push, xy[1]);
195 }
196
197 if (serialize)
198 IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
199
200 NOUVEAU_DRV_STAT(&nvc0->screen->base, gpu_serialize_count, serialize);
201 }
202
203 static void
204 nvc0_validate_blend_colour(struct nvc0_context *nvc0)
205 {
206 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
207
208 BEGIN_NVC0(push, NVC0_3D(BLEND_COLOR(0)), 4);
209 PUSH_DATAf(push, nvc0->blend_colour.color[0]);
210 PUSH_DATAf(push, nvc0->blend_colour.color[1]);
211 PUSH_DATAf(push, nvc0->blend_colour.color[2]);
212 PUSH_DATAf(push, nvc0->blend_colour.color[3]);
213 }
214
215 static void
216 nvc0_validate_stencil_ref(struct nvc0_context *nvc0)
217 {
218 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
219 const ubyte *ref = &nvc0->stencil_ref.ref_value[0];
220
221 IMMED_NVC0(push, NVC0_3D(STENCIL_FRONT_FUNC_REF), ref[0]);
222 IMMED_NVC0(push, NVC0_3D(STENCIL_BACK_FUNC_REF), ref[1]);
223 }
224
225 static void
226 nvc0_validate_stipple(struct nvc0_context *nvc0)
227 {
228 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
229 unsigned i;
230
231 BEGIN_NVC0(push, NVC0_3D(POLYGON_STIPPLE_PATTERN(0)), 32);
232 for (i = 0; i < 32; ++i)
233 PUSH_DATA(push, util_bswap32(nvc0->stipple.stipple[i]));
234 }
235
236 static void
237 nvc0_validate_scissor(struct nvc0_context *nvc0)
238 {
239 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
240 struct pipe_scissor_state *s = &nvc0->scissor;
241
242 if (!(nvc0->dirty & NVC0_NEW_SCISSOR) &&
243 nvc0->rast->pipe.scissor == nvc0->state.scissor)
244 return;
245 nvc0->state.scissor = nvc0->rast->pipe.scissor;
246
247 BEGIN_NVC0(push, NVC0_3D(SCISSOR_HORIZ(0)), 2);
248 if (nvc0->rast->pipe.scissor) {
249 PUSH_DATA(push, (s->maxx << 16) | s->minx);
250 PUSH_DATA(push, (s->maxy << 16) | s->miny);
251 } else {
252 PUSH_DATA(push, (0xffff << 16) | 0);
253 PUSH_DATA(push, (0xffff << 16) | 0);
254 }
255 }
256
257 static void
258 nvc0_validate_viewport(struct nvc0_context *nvc0)
259 {
260 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
261 struct pipe_viewport_state *vp = &nvc0->viewport;
262 int x, y, w, h;
263 float zmin, zmax;
264
265 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSLATE_X(0)), 3);
266 PUSH_DATAf(push, vp->translate[0]);
267 PUSH_DATAf(push, vp->translate[1]);
268 PUSH_DATAf(push, vp->translate[2]);
269 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_SCALE_X(0)), 3);
270 PUSH_DATAf(push, vp->scale[0]);
271 PUSH_DATAf(push, vp->scale[1]);
272 PUSH_DATAf(push, vp->scale[2]);
273
274 /* now set the viewport rectangle to viewport dimensions for clipping */
275
276 x = util_iround(MAX2(0.0f, vp->translate[0] - fabsf(vp->scale[0])));
277 y = util_iround(MAX2(0.0f, vp->translate[1] - fabsf(vp->scale[1])));
278 w = util_iround(vp->translate[0] + fabsf(vp->scale[0])) - x;
279 h = util_iround(vp->translate[1] + fabsf(vp->scale[1])) - y;
280
281 zmin = vp->translate[2] - fabsf(vp->scale[2]);
282 zmax = vp->translate[2] + fabsf(vp->scale[2]);
283
284 nvc0->vport_int[0] = (w << 16) | x;
285 nvc0->vport_int[1] = (h << 16) | y;
286 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_HORIZ(0)), 2);
287 PUSH_DATA (push, nvc0->vport_int[0]);
288 PUSH_DATA (push, nvc0->vport_int[1]);
289 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2);
290 PUSH_DATAf(push, zmin);
291 PUSH_DATAf(push, zmax);
292 }
293
294 static INLINE void
295 nvc0_upload_uclip_planes(struct nvc0_context *nvc0, unsigned s)
296 {
297 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
298 struct nouveau_bo *bo = nvc0->screen->uniform_bo;
299
300 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
301 PUSH_DATA (push, 512);
302 PUSH_DATAh(push, bo->offset + (5 << 16) + (s << 9));
303 PUSH_DATA (push, bo->offset + (5 << 16) + (s << 9));
304 BEGIN_1IC0(push, NVC0_3D(CB_POS), PIPE_MAX_CLIP_PLANES * 4 + 1);
305 PUSH_DATA (push, 256);
306 PUSH_DATAp(push, &nvc0->clip.ucp[0][0], PIPE_MAX_CLIP_PLANES * 4);
307 }
308
309 static INLINE void
310 nvc0_check_program_ucps(struct nvc0_context *nvc0,
311 struct nvc0_program *vp, uint8_t mask)
312 {
313 const unsigned n = util_logbase2(mask) + 1;
314
315 if (vp->vp.num_ucps >= n)
316 return;
317 nvc0_program_destroy(nvc0, vp);
318
319 vp->vp.num_ucps = n;
320 if (likely(vp == nvc0->vertprog))
321 nvc0_vertprog_validate(nvc0);
322 else
323 if (likely(vp == nvc0->gmtyprog))
324 nvc0_vertprog_validate(nvc0);
325 else
326 nvc0_tevlprog_validate(nvc0);
327 }
328
329 static void
330 nvc0_validate_clip(struct nvc0_context *nvc0)
331 {
332 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
333 struct nvc0_program *vp;
334 unsigned stage;
335 uint8_t clip_enable = nvc0->rast->pipe.clip_plane_enable;
336
337 if (nvc0->gmtyprog) {
338 stage = 3;
339 vp = nvc0->gmtyprog;
340 } else
341 if (nvc0->tevlprog) {
342 stage = 2;
343 vp = nvc0->tevlprog;
344 } else {
345 stage = 0;
346 vp = nvc0->vertprog;
347 }
348
349 if (clip_enable && vp->vp.num_ucps < PIPE_MAX_CLIP_PLANES)
350 nvc0_check_program_ucps(nvc0, vp, clip_enable);
351
352 if (nvc0->dirty & (NVC0_NEW_CLIP | (NVC0_NEW_VERTPROG << stage)))
353 if (vp->vp.num_ucps > 0 && vp->vp.num_ucps <= PIPE_MAX_CLIP_PLANES)
354 nvc0_upload_uclip_planes(nvc0, stage);
355
356 clip_enable &= vp->vp.clip_enable;
357
358 if (nvc0->state.clip_enable != clip_enable) {
359 nvc0->state.clip_enable = clip_enable;
360 IMMED_NVC0(push, NVC0_3D(CLIP_DISTANCE_ENABLE), clip_enable);
361 }
362 if (nvc0->state.clip_mode != vp->vp.clip_mode) {
363 nvc0->state.clip_mode = vp->vp.clip_mode;
364 BEGIN_NVC0(push, NVC0_3D(CLIP_DISTANCE_MODE), 1);
365 PUSH_DATA (push, vp->vp.clip_mode);
366 }
367 }
368
369 static void
370 nvc0_validate_blend(struct nvc0_context *nvc0)
371 {
372 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
373
374 PUSH_SPACE(push, nvc0->blend->size);
375 PUSH_DATAp(push, nvc0->blend->state, nvc0->blend->size);
376 }
377
378 static void
379 nvc0_validate_zsa(struct nvc0_context *nvc0)
380 {
381 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
382
383 PUSH_SPACE(push, nvc0->zsa->size);
384 PUSH_DATAp(push, nvc0->zsa->state, nvc0->zsa->size);
385 }
386
387 static void
388 nvc0_validate_rasterizer(struct nvc0_context *nvc0)
389 {
390 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
391
392 PUSH_SPACE(push, nvc0->rast->size);
393 PUSH_DATAp(push, nvc0->rast->state, nvc0->rast->size);
394 }
395
396 static void
397 nvc0_constbufs_validate(struct nvc0_context *nvc0)
398 {
399 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
400 unsigned s;
401
402 for (s = 0; s < 5; ++s) {
403 while (nvc0->constbuf_dirty[s]) {
404 int i = ffs(nvc0->constbuf_dirty[s]) - 1;
405 nvc0->constbuf_dirty[s] &= ~(1 << i);
406
407 if (nvc0->constbuf[s][i].user) {
408 struct nouveau_bo *bo = nvc0->screen->uniform_bo;
409 const unsigned base = s << 16;
410 const unsigned size = nvc0->constbuf[s][0].size;
411 assert(i == 0); /* we really only want OpenGL uniforms here */
412 assert(nvc0->constbuf[s][0].u.data);
413
414 if (nvc0->state.uniform_buffer_bound[s] < size) {
415 nvc0->state.uniform_buffer_bound[s] = align(size, 0x100);
416
417 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
418 PUSH_DATA (push, nvc0->state.uniform_buffer_bound[s]);
419 PUSH_DATAh(push, bo->offset + base);
420 PUSH_DATA (push, bo->offset + base);
421 BEGIN_NVC0(push, NVC0_3D(CB_BIND(s)), 1);
422 PUSH_DATA (push, (0 << 4) | 1);
423 }
424 nvc0_cb_push(&nvc0->base, bo, NOUVEAU_BO_VRAM,
425 base, nvc0->state.uniform_buffer_bound[s],
426 0, (size + 3) / 4,
427 nvc0->constbuf[s][0].u.data);
428 } else {
429 struct nv04_resource *res =
430 nv04_resource(nvc0->constbuf[s][i].u.buf);
431 if (res) {
432 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
433 PUSH_DATA (push, nvc0->constbuf[s][i].size);
434 PUSH_DATAh(push, res->address + nvc0->constbuf[s][i].offset);
435 PUSH_DATA (push, res->address + nvc0->constbuf[s][i].offset);
436 BEGIN_NVC0(push, NVC0_3D(CB_BIND(s)), 1);
437 PUSH_DATA (push, (i << 4) | 1);
438
439 BCTX_REFN(nvc0->bufctx_3d, CB(s, i), res, RD);
440 } else {
441 BEGIN_NVC0(push, NVC0_3D(CB_BIND(s)), 1);
442 PUSH_DATA (push, (i << 4) | 0);
443 }
444 if (i == 0)
445 nvc0->state.uniform_buffer_bound[s] = 0;
446 }
447 }
448 }
449 }
450
451 static void
452 nvc0_validate_sample_mask(struct nvc0_context *nvc0)
453 {
454 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
455
456 unsigned mask[4] =
457 {
458 nvc0->sample_mask & 0xffff,
459 nvc0->sample_mask & 0xffff,
460 nvc0->sample_mask & 0xffff,
461 nvc0->sample_mask & 0xffff
462 };
463
464 BEGIN_NVC0(push, NVC0_3D(MSAA_MASK(0)), 4);
465 PUSH_DATA (push, mask[0]);
466 PUSH_DATA (push, mask[1]);
467 PUSH_DATA (push, mask[2]);
468 PUSH_DATA (push, mask[3]);
469 }
470
471 static void
472 nvc0_validate_min_samples(struct nvc0_context *nvc0)
473 {
474 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
475 int samples;
476
477 samples = util_next_power_of_two(nvc0->min_samples);
478 if (samples > 1)
479 samples |= NVC0_3D_SAMPLE_SHADING_ENABLE;
480
481 IMMED_NVC0(push, NVC0_3D(SAMPLE_SHADING), samples);
482 }
483
484 void
485 nvc0_validate_global_residents(struct nvc0_context *nvc0,
486 struct nouveau_bufctx *bctx, int bin)
487 {
488 unsigned i;
489
490 for (i = 0; i < nvc0->global_residents.size / sizeof(struct pipe_resource *);
491 ++i) {
492 struct pipe_resource *res = *util_dynarray_element(
493 &nvc0->global_residents, struct pipe_resource *, i);
494 if (res)
495 nvc0_add_resident(bctx, bin, nv04_resource(res), NOUVEAU_BO_RDWR);
496 }
497 }
498
499 static void
500 nvc0_validate_derived_1(struct nvc0_context *nvc0)
501 {
502 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
503 boolean rasterizer_discard;
504
505 if (nvc0->rast && nvc0->rast->pipe.rasterizer_discard) {
506 rasterizer_discard = TRUE;
507 } else {
508 boolean zs = nvc0->zsa &&
509 (nvc0->zsa->pipe.depth.enabled || nvc0->zsa->pipe.stencil[0].enabled);
510 rasterizer_discard = !zs &&
511 (!nvc0->fragprog || !nvc0->fragprog->hdr[18]);
512 }
513
514 if (rasterizer_discard != nvc0->state.rasterizer_discard) {
515 nvc0->state.rasterizer_discard = rasterizer_discard;
516 IMMED_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), !rasterizer_discard);
517 }
518 }
519
520 static void
521 nvc0_switch_pipe_context(struct nvc0_context *ctx_to)
522 {
523 struct nvc0_context *ctx_from = ctx_to->screen->cur_ctx;
524 unsigned s;
525
526 if (ctx_from)
527 ctx_to->state = ctx_from->state;
528
529 ctx_to->dirty = ~0;
530
531 for (s = 0; s < 5; ++s) {
532 ctx_to->samplers_dirty[s] = ~0;
533 ctx_to->textures_dirty[s] = ~0;
534 }
535
536 if (!ctx_to->vertex)
537 ctx_to->dirty &= ~(NVC0_NEW_VERTEX | NVC0_NEW_ARRAYS);
538 if (!ctx_to->idxbuf.buffer)
539 ctx_to->dirty &= ~NVC0_NEW_IDXBUF;
540
541 if (!ctx_to->vertprog)
542 ctx_to->dirty &= ~NVC0_NEW_VERTPROG;
543 if (!ctx_to->fragprog)
544 ctx_to->dirty &= ~NVC0_NEW_FRAGPROG;
545
546 if (!ctx_to->blend)
547 ctx_to->dirty &= ~NVC0_NEW_BLEND;
548 if (!ctx_to->rast)
549 ctx_to->dirty &= ~(NVC0_NEW_RASTERIZER | NVC0_NEW_SCISSOR);
550 if (!ctx_to->zsa)
551 ctx_to->dirty &= ~NVC0_NEW_ZSA;
552
553 ctx_to->screen->cur_ctx = ctx_to;
554 }
555
556 static struct state_validate {
557 void (*func)(struct nvc0_context *);
558 uint32_t states;
559 } validate_list[] = {
560 { nvc0_validate_fb, NVC0_NEW_FRAMEBUFFER },
561 { nvc0_validate_blend, NVC0_NEW_BLEND },
562 { nvc0_validate_zsa, NVC0_NEW_ZSA },
563 { nvc0_validate_sample_mask, NVC0_NEW_SAMPLE_MASK },
564 { nvc0_validate_rasterizer, NVC0_NEW_RASTERIZER },
565 { nvc0_validate_blend_colour, NVC0_NEW_BLEND_COLOUR },
566 { nvc0_validate_stencil_ref, NVC0_NEW_STENCIL_REF },
567 { nvc0_validate_stipple, NVC0_NEW_STIPPLE },
568 { nvc0_validate_scissor, NVC0_NEW_SCISSOR | NVC0_NEW_RASTERIZER },
569 { nvc0_validate_viewport, NVC0_NEW_VIEWPORT },
570 { nvc0_vertprog_validate, NVC0_NEW_VERTPROG },
571 { nvc0_tctlprog_validate, NVC0_NEW_TCTLPROG },
572 { nvc0_tevlprog_validate, NVC0_NEW_TEVLPROG },
573 { nvc0_gmtyprog_validate, NVC0_NEW_GMTYPROG },
574 { nvc0_fragprog_validate, NVC0_NEW_FRAGPROG },
575 { nvc0_validate_derived_1, NVC0_NEW_FRAGPROG | NVC0_NEW_ZSA |
576 NVC0_NEW_RASTERIZER },
577 { nvc0_validate_clip, NVC0_NEW_CLIP | NVC0_NEW_RASTERIZER |
578 NVC0_NEW_VERTPROG |
579 NVC0_NEW_TEVLPROG |
580 NVC0_NEW_GMTYPROG },
581 { nvc0_constbufs_validate, NVC0_NEW_CONSTBUF },
582 { nvc0_validate_textures, NVC0_NEW_TEXTURES },
583 { nvc0_validate_samplers, NVC0_NEW_SAMPLERS },
584 { nve4_set_tex_handles, NVC0_NEW_TEXTURES | NVC0_NEW_SAMPLERS },
585 { nvc0_vertex_arrays_validate, NVC0_NEW_VERTEX | NVC0_NEW_ARRAYS },
586 { nvc0_validate_surfaces, NVC0_NEW_SURFACES },
587 { nvc0_idxbuf_validate, NVC0_NEW_IDXBUF },
588 { nvc0_tfb_validate, NVC0_NEW_TFB_TARGETS | NVC0_NEW_GMTYPROG },
589 { nvc0_validate_min_samples, NVC0_NEW_MIN_SAMPLES },
590 };
591 #define validate_list_len (sizeof(validate_list) / sizeof(validate_list[0]))
592
593 boolean
594 nvc0_state_validate(struct nvc0_context *nvc0, uint32_t mask, unsigned words)
595 {
596 uint32_t state_mask;
597 int ret;
598 unsigned i;
599
600 if (nvc0->screen->cur_ctx != nvc0)
601 nvc0_switch_pipe_context(nvc0);
602
603 state_mask = nvc0->dirty & mask;
604
605 if (state_mask) {
606 for (i = 0; i < validate_list_len; ++i) {
607 struct state_validate *validate = &validate_list[i];
608
609 if (state_mask & validate->states)
610 validate->func(nvc0);
611 }
612 nvc0->dirty &= ~state_mask;
613
614 nvc0_bufctx_fence(nvc0, nvc0->bufctx_3d, FALSE);
615 }
616
617 nouveau_pushbuf_bufctx(nvc0->base.pushbuf, nvc0->bufctx_3d);
618 ret = nouveau_pushbuf_validate(nvc0->base.pushbuf);
619
620 if (unlikely(nvc0->state.flushed)) {
621 nvc0->state.flushed = FALSE;
622 nvc0_bufctx_fence(nvc0, nvc0->bufctx_3d, TRUE);
623 }
624 return !ret;
625 }