2 #include "util/u_format.h"
3 #include "util/u_framebuffer.h"
4 #include "util/u_math.h"
6 #include "nvc0/nvc0_context.h"
10 nvc0_validate_zcull(struct nvc0_context
*nvc0
)
12 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
13 struct pipe_framebuffer_state
*fb
= &nvc0
->framebuffer
;
14 struct nv50_surface
*sf
= nv50_surface(fb
->zsbuf
);
15 struct nv50_miptree
*mt
= nv50_miptree(sf
->base
.texture
);
16 struct nouveau_bo
*bo
= mt
->base
.bo
;
18 uint32_t offset
= align(mt
->total_size
, 1 << 17);
19 unsigned width
, height
;
21 assert(mt
->base
.base
.depth0
== 1 && mt
->base
.base
.array_size
< 2);
23 size
= mt
->total_size
* 2;
25 height
= align(fb
->height
, 32);
26 width
= fb
->width
% 224;
28 width
= fb
->width
+ (224 - width
);
32 BEGIN_NVC0(push
, NVC0_3D(ZCULL_REGION
), 1);
34 BEGIN_NVC0(push
, NVC0_3D(ZCULL_ADDRESS_HIGH
), 2);
35 PUSH_DATAh(push
, bo
->offset
+ offset
);
36 PUSH_DATA (push
, bo
->offset
+ offset
);
38 BEGIN_NVC0(push
, NVC0_3D(ZCULL_LIMIT_HIGH
), 2);
39 PUSH_DATAh(push
, bo
->offset
+ offset
);
40 PUSH_DATA (push
, bo
->offset
+ offset
);
41 BEGIN_NVC0(push
, SUBC_3D(0x07e0), 2);
42 PUSH_DATA (push
, size
);
43 PUSH_DATA (push
, size
>> 16);
44 BEGIN_NVC0(push
, SUBC_3D(0x15c8), 1); /* bits 0x3 */
46 BEGIN_NVC0(push
, NVC0_3D(ZCULL_WIDTH
), 4);
47 PUSH_DATA (push
, width
);
48 PUSH_DATA (push
, height
);
51 BEGIN_NVC0(push
, NVC0_3D(ZCULL_WINDOW_OFFSET_X
), 2);
54 BEGIN_NVC0(push
, NVC0_3D(ZCULL_INVALIDATE
), 1);
60 nvc0_fb_set_null_rt(struct nouveau_pushbuf
*push
, unsigned i
, unsigned layers
)
62 BEGIN_NVC0(push
, NVC0_3D(RT_ADDRESS_HIGH(i
)), 9);
65 PUSH_DATA (push
, 64); // width
66 PUSH_DATA (push
, 0); // height
67 PUSH_DATA (push
, 0); // format
68 PUSH_DATA (push
, 0); // tile mode
69 PUSH_DATA (push
, layers
); // layers
70 PUSH_DATA (push
, 0); // layer stride
71 PUSH_DATA (push
, 0); // base layer
75 nvc0_validate_fb(struct nvc0_context
*nvc0
)
77 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
78 struct pipe_framebuffer_state
*fb
= &nvc0
->framebuffer
;
79 struct nvc0_screen
*screen
= nvc0
->screen
;
81 unsigned ms_mode
= NVC0_3D_MULTISAMPLE_MODE_MS1
;
82 unsigned nr_cbufs
= fb
->nr_cbufs
;
83 bool serialize
= false;
85 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_3D_FB
);
87 BEGIN_NVC0(push
, NVC0_3D(SCREEN_SCISSOR_HORIZ
), 2);
88 PUSH_DATA (push
, fb
->width
<< 16);
89 PUSH_DATA (push
, fb
->height
<< 16);
91 for (i
= 0; i
< fb
->nr_cbufs
; ++i
) {
92 struct nv50_surface
*sf
;
93 struct nv04_resource
*res
;
94 struct nouveau_bo
*bo
;
97 nvc0_fb_set_null_rt(push
, i
, 0);
101 sf
= nv50_surface(fb
->cbufs
[i
]);
102 res
= nv04_resource(sf
->base
.texture
);
105 BEGIN_NVC0(push
, NVC0_3D(RT_ADDRESS_HIGH(i
)), 9);
106 PUSH_DATAh(push
, res
->address
+ sf
->offset
);
107 PUSH_DATA (push
, res
->address
+ sf
->offset
);
108 if (likely(nouveau_bo_memtype(bo
))) {
109 struct nv50_miptree
*mt
= nv50_miptree(sf
->base
.texture
);
111 assert(sf
->base
.texture
->target
!= PIPE_BUFFER
);
113 PUSH_DATA(push
, sf
->width
);
114 PUSH_DATA(push
, sf
->height
);
115 PUSH_DATA(push
, nvc0_format_table
[sf
->base
.format
].rt
);
116 PUSH_DATA(push
, (mt
->layout_3d
<< 16) |
117 mt
->level
[sf
->base
.u
.tex
.level
].tile_mode
);
118 PUSH_DATA(push
, sf
->base
.u
.tex
.first_layer
+ sf
->depth
);
119 PUSH_DATA(push
, mt
->layer_stride
>> 2);
120 PUSH_DATA(push
, sf
->base
.u
.tex
.first_layer
);
122 ms_mode
= mt
->ms_mode
;
124 if (res
->base
.target
== PIPE_BUFFER
) {
125 PUSH_DATA(push
, 262144);
128 PUSH_DATA(push
, nv50_miptree(sf
->base
.texture
)->level
[0].pitch
);
129 PUSH_DATA(push
, sf
->height
);
131 PUSH_DATA(push
, nvc0_format_table
[sf
->base
.format
].rt
);
132 PUSH_DATA(push
, 1 << 12);
137 nvc0_resource_fence(res
, NOUVEAU_BO_WR
);
142 if (res
->status
& NOUVEAU_BUFFER_STATUS_GPU_READING
)
144 res
->status
|= NOUVEAU_BUFFER_STATUS_GPU_WRITING
;
145 res
->status
&= ~NOUVEAU_BUFFER_STATUS_GPU_READING
;
147 /* only register for writing, otherwise we'd always serialize here */
148 BCTX_REFN(nvc0
->bufctx_3d
, 3D_FB
, res
, WR
);
152 struct nv50_miptree
*mt
= nv50_miptree(fb
->zsbuf
->texture
);
153 struct nv50_surface
*sf
= nv50_surface(fb
->zsbuf
);
154 int unk
= mt
->base
.base
.target
== PIPE_TEXTURE_2D
;
156 BEGIN_NVC0(push
, NVC0_3D(ZETA_ADDRESS_HIGH
), 5);
157 PUSH_DATAh(push
, mt
->base
.address
+ sf
->offset
);
158 PUSH_DATA (push
, mt
->base
.address
+ sf
->offset
);
159 PUSH_DATA (push
, nvc0_format_table
[fb
->zsbuf
->format
].rt
);
160 PUSH_DATA (push
, mt
->level
[sf
->base
.u
.tex
.level
].tile_mode
);
161 PUSH_DATA (push
, mt
->layer_stride
>> 2);
162 BEGIN_NVC0(push
, NVC0_3D(ZETA_ENABLE
), 1);
164 BEGIN_NVC0(push
, NVC0_3D(ZETA_HORIZ
), 3);
165 PUSH_DATA (push
, sf
->width
);
166 PUSH_DATA (push
, sf
->height
);
167 PUSH_DATA (push
, (unk
<< 16) |
168 (sf
->base
.u
.tex
.first_layer
+ sf
->depth
));
169 BEGIN_NVC0(push
, NVC0_3D(ZETA_BASE_LAYER
), 1);
170 PUSH_DATA (push
, sf
->base
.u
.tex
.first_layer
);
172 ms_mode
= mt
->ms_mode
;
174 if (mt
->base
.status
& NOUVEAU_BUFFER_STATUS_GPU_READING
)
176 mt
->base
.status
|= NOUVEAU_BUFFER_STATUS_GPU_WRITING
;
177 mt
->base
.status
&= ~NOUVEAU_BUFFER_STATUS_GPU_READING
;
179 BCTX_REFN(nvc0
->bufctx_3d
, 3D_FB
, &mt
->base
, WR
);
181 BEGIN_NVC0(push
, NVC0_3D(ZETA_ENABLE
), 1);
185 if (nr_cbufs
== 0 && !fb
->zsbuf
) {
186 assert(util_is_power_of_two(fb
->samples
));
187 assert(fb
->samples
<= 8);
189 nvc0_fb_set_null_rt(push
, 0, fb
->layers
);
192 ms_mode
= ffs(fb
->samples
) - 1;
196 BEGIN_NVC0(push
, NVC0_3D(RT_CONTROL
), 1);
197 PUSH_DATA (push
, (076543210 << 4) | nr_cbufs
);
198 IMMED_NVC0(push
, NVC0_3D(MULTISAMPLE_MODE
), ms_mode
);
201 BEGIN_NVC0(push
, NVC0_3D(CB_SIZE
), 3);
202 PUSH_DATA (push
, 2048);
203 PUSH_DATAh(push
, screen
->uniform_bo
->offset
+ NVC0_CB_AUX_INFO(4));
204 PUSH_DATA (push
, screen
->uniform_bo
->offset
+ NVC0_CB_AUX_INFO(4));
205 BEGIN_1IC0(push
, NVC0_3D(CB_POS
), 1 + 2 * ms
);
206 PUSH_DATA (push
, NVC0_CB_AUX_SAMPLE_INFO
);
207 for (i
= 0; i
< ms
; i
++) {
209 nvc0
->base
.pipe
.get_sample_position(&nvc0
->base
.pipe
, ms
, i
, xy
);
210 PUSH_DATAf(push
, xy
[0]);
211 PUSH_DATAf(push
, xy
[1]);
215 IMMED_NVC0(push
, NVC0_3D(SERIALIZE
), 0);
217 NOUVEAU_DRV_STAT(&nvc0
->screen
->base
, gpu_serialize_count
, serialize
);
221 nvc0_validate_blend_colour(struct nvc0_context
*nvc0
)
223 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
225 BEGIN_NVC0(push
, NVC0_3D(BLEND_COLOR(0)), 4);
226 PUSH_DATAf(push
, nvc0
->blend_colour
.color
[0]);
227 PUSH_DATAf(push
, nvc0
->blend_colour
.color
[1]);
228 PUSH_DATAf(push
, nvc0
->blend_colour
.color
[2]);
229 PUSH_DATAf(push
, nvc0
->blend_colour
.color
[3]);
233 nvc0_validate_stencil_ref(struct nvc0_context
*nvc0
)
235 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
236 const ubyte
*ref
= &nvc0
->stencil_ref
.ref_value
[0];
238 IMMED_NVC0(push
, NVC0_3D(STENCIL_FRONT_FUNC_REF
), ref
[0]);
239 IMMED_NVC0(push
, NVC0_3D(STENCIL_BACK_FUNC_REF
), ref
[1]);
243 nvc0_validate_stipple(struct nvc0_context
*nvc0
)
245 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
248 BEGIN_NVC0(push
, NVC0_3D(POLYGON_STIPPLE_PATTERN(0)), 32);
249 for (i
= 0; i
< 32; ++i
)
250 PUSH_DATA(push
, util_bswap32(nvc0
->stipple
.stipple
[i
]));
254 nvc0_validate_scissor(struct nvc0_context
*nvc0
)
257 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
259 if (!(nvc0
->dirty_3d
& NVC0_NEW_3D_SCISSOR
) &&
260 nvc0
->rast
->pipe
.scissor
== nvc0
->state
.scissor
)
263 if (nvc0
->state
.scissor
!= nvc0
->rast
->pipe
.scissor
)
264 nvc0
->scissors_dirty
= (1 << NVC0_MAX_VIEWPORTS
) - 1;
266 nvc0
->state
.scissor
= nvc0
->rast
->pipe
.scissor
;
268 for (i
= 0; i
< NVC0_MAX_VIEWPORTS
; i
++) {
269 struct pipe_scissor_state
*s
= &nvc0
->scissors
[i
];
270 if (!(nvc0
->scissors_dirty
& (1 << i
)))
273 BEGIN_NVC0(push
, NVC0_3D(SCISSOR_HORIZ(i
)), 2);
274 if (nvc0
->rast
->pipe
.scissor
) {
275 PUSH_DATA(push
, (s
->maxx
<< 16) | s
->minx
);
276 PUSH_DATA(push
, (s
->maxy
<< 16) | s
->miny
);
278 PUSH_DATA(push
, (0xffff << 16) | 0);
279 PUSH_DATA(push
, (0xffff << 16) | 0);
282 nvc0
->scissors_dirty
= 0;
286 nvc0_validate_viewport(struct nvc0_context
*nvc0
)
288 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
292 for (i
= 0; i
< NVC0_MAX_VIEWPORTS
; i
++) {
293 struct pipe_viewport_state
*vp
= &nvc0
->viewports
[i
];
295 if (!(nvc0
->viewports_dirty
& (1 << i
)))
298 BEGIN_NVC0(push
, NVC0_3D(VIEWPORT_TRANSLATE_X(i
)), 3);
299 PUSH_DATAf(push
, vp
->translate
[0]);
300 PUSH_DATAf(push
, vp
->translate
[1]);
301 PUSH_DATAf(push
, vp
->translate
[2]);
303 BEGIN_NVC0(push
, NVC0_3D(VIEWPORT_SCALE_X(i
)), 3);
304 PUSH_DATAf(push
, vp
->scale
[0]);
305 PUSH_DATAf(push
, vp
->scale
[1]);
306 PUSH_DATAf(push
, vp
->scale
[2]);
308 /* now set the viewport rectangle to viewport dimensions for clipping */
310 x
= util_iround(MAX2(0.0f
, vp
->translate
[0] - fabsf(vp
->scale
[0])));
311 y
= util_iround(MAX2(0.0f
, vp
->translate
[1] - fabsf(vp
->scale
[1])));
312 w
= util_iround(vp
->translate
[0] + fabsf(vp
->scale
[0])) - x
;
313 h
= util_iround(vp
->translate
[1] + fabsf(vp
->scale
[1])) - y
;
315 BEGIN_NVC0(push
, NVC0_3D(VIEWPORT_HORIZ(i
)), 2);
316 PUSH_DATA (push
, (w
<< 16) | x
);
317 PUSH_DATA (push
, (h
<< 16) | y
);
319 zmin
= vp
->translate
[2] - fabsf(vp
->scale
[2]);
320 zmax
= vp
->translate
[2] + fabsf(vp
->scale
[2]);
322 BEGIN_NVC0(push
, NVC0_3D(DEPTH_RANGE_NEAR(i
)), 2);
323 PUSH_DATAf(push
, zmin
);
324 PUSH_DATAf(push
, zmax
);
326 nvc0
->viewports_dirty
= 0;
330 nvc0_upload_uclip_planes(struct nvc0_context
*nvc0
, unsigned s
)
332 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
333 struct nvc0_screen
*screen
= nvc0
->screen
;
335 BEGIN_NVC0(push
, NVC0_3D(CB_SIZE
), 3);
336 PUSH_DATA (push
, 2048);
337 PUSH_DATAh(push
, screen
->uniform_bo
->offset
+ NVC0_CB_AUX_INFO(s
));
338 PUSH_DATA (push
, screen
->uniform_bo
->offset
+ NVC0_CB_AUX_INFO(s
));
339 BEGIN_1IC0(push
, NVC0_3D(CB_POS
), PIPE_MAX_CLIP_PLANES
* 4 + 1);
340 PUSH_DATA (push
, NVC0_CB_AUX_UCP_INFO
);
341 PUSH_DATAp(push
, &nvc0
->clip
.ucp
[0][0], PIPE_MAX_CLIP_PLANES
* 4);
345 nvc0_check_program_ucps(struct nvc0_context
*nvc0
,
346 struct nvc0_program
*vp
, uint8_t mask
)
348 const unsigned n
= util_logbase2(mask
) + 1;
350 if (vp
->vp
.num_ucps
>= n
)
352 nvc0_program_destroy(nvc0
, vp
);
355 if (likely(vp
== nvc0
->vertprog
))
356 nvc0_vertprog_validate(nvc0
);
358 if (likely(vp
== nvc0
->gmtyprog
))
359 nvc0_gmtyprog_validate(nvc0
);
361 nvc0_tevlprog_validate(nvc0
);
365 nvc0_validate_clip(struct nvc0_context
*nvc0
)
367 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
368 struct nvc0_program
*vp
;
370 uint8_t clip_enable
= nvc0
->rast
->pipe
.clip_plane_enable
;
372 if (nvc0
->gmtyprog
) {
376 if (nvc0
->tevlprog
) {
384 if (clip_enable
&& vp
->vp
.num_ucps
< PIPE_MAX_CLIP_PLANES
)
385 nvc0_check_program_ucps(nvc0
, vp
, clip_enable
);
387 if (nvc0
->dirty_3d
& (NVC0_NEW_3D_CLIP
| (NVC0_NEW_3D_VERTPROG
<< stage
)))
388 if (vp
->vp
.num_ucps
> 0 && vp
->vp
.num_ucps
<= PIPE_MAX_CLIP_PLANES
)
389 nvc0_upload_uclip_planes(nvc0
, stage
);
391 clip_enable
&= vp
->vp
.clip_enable
;
393 if (nvc0
->state
.clip_enable
!= clip_enable
) {
394 nvc0
->state
.clip_enable
= clip_enable
;
395 IMMED_NVC0(push
, NVC0_3D(CLIP_DISTANCE_ENABLE
), clip_enable
);
397 if (nvc0
->state
.clip_mode
!= vp
->vp
.clip_mode
) {
398 nvc0
->state
.clip_mode
= vp
->vp
.clip_mode
;
399 BEGIN_NVC0(push
, NVC0_3D(CLIP_DISTANCE_MODE
), 1);
400 PUSH_DATA (push
, vp
->vp
.clip_mode
);
405 nvc0_validate_blend(struct nvc0_context
*nvc0
)
407 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
409 PUSH_SPACE(push
, nvc0
->blend
->size
);
410 PUSH_DATAp(push
, nvc0
->blend
->state
, nvc0
->blend
->size
);
414 nvc0_validate_zsa(struct nvc0_context
*nvc0
)
416 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
418 PUSH_SPACE(push
, nvc0
->zsa
->size
);
419 PUSH_DATAp(push
, nvc0
->zsa
->state
, nvc0
->zsa
->size
);
423 nvc0_validate_rasterizer(struct nvc0_context
*nvc0
)
425 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
427 PUSH_SPACE(push
, nvc0
->rast
->size
);
428 PUSH_DATAp(push
, nvc0
->rast
->state
, nvc0
->rast
->size
);
432 nvc0_constbufs_validate(struct nvc0_context
*nvc0
)
434 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
437 for (s
= 0; s
< 5; ++s
) {
438 while (nvc0
->constbuf_dirty
[s
]) {
439 int i
= ffs(nvc0
->constbuf_dirty
[s
]) - 1;
440 nvc0
->constbuf_dirty
[s
] &= ~(1 << i
);
442 if (nvc0
->constbuf
[s
][i
].user
) {
443 struct nouveau_bo
*bo
= nvc0
->screen
->uniform_bo
;
444 const unsigned base
= NVC0_CB_USR_INFO(s
);
445 const unsigned size
= nvc0
->constbuf
[s
][0].size
;
446 assert(i
== 0); /* we really only want OpenGL uniforms here */
447 assert(nvc0
->constbuf
[s
][0].u
.data
);
449 if (nvc0
->state
.uniform_buffer_bound
[s
] < size
) {
450 nvc0
->state
.uniform_buffer_bound
[s
] = align(size
, 0x100);
452 BEGIN_NVC0(push
, NVC0_3D(CB_SIZE
), 3);
453 PUSH_DATA (push
, nvc0
->state
.uniform_buffer_bound
[s
]);
454 PUSH_DATAh(push
, bo
->offset
+ base
);
455 PUSH_DATA (push
, bo
->offset
+ base
);
456 BEGIN_NVC0(push
, NVC0_3D(CB_BIND(s
)), 1);
457 PUSH_DATA (push
, (0 << 4) | 1);
459 nvc0_cb_bo_push(&nvc0
->base
, bo
, NV_VRAM_DOMAIN(&nvc0
->screen
->base
),
460 base
, nvc0
->state
.uniform_buffer_bound
[s
],
462 nvc0
->constbuf
[s
][0].u
.data
);
464 struct nv04_resource
*res
=
465 nv04_resource(nvc0
->constbuf
[s
][i
].u
.buf
);
467 BEGIN_NVC0(push
, NVC0_3D(CB_SIZE
), 3);
468 PUSH_DATA (push
, nvc0
->constbuf
[s
][i
].size
);
469 PUSH_DATAh(push
, res
->address
+ nvc0
->constbuf
[s
][i
].offset
);
470 PUSH_DATA (push
, res
->address
+ nvc0
->constbuf
[s
][i
].offset
);
471 BEGIN_NVC0(push
, NVC0_3D(CB_BIND(s
)), 1);
472 PUSH_DATA (push
, (i
<< 4) | 1);
474 BCTX_REFN(nvc0
->bufctx_3d
, 3D_CB(s
, i
), res
, RD
);
476 nvc0
->cb_dirty
= 1; /* Force cache flush for UBO. */
477 res
->cb_bindings
[s
] |= 1 << i
;
479 BEGIN_NVC0(push
, NVC0_3D(CB_BIND(s
)), 1);
480 PUSH_DATA (push
, (i
<< 4) | 0);
483 nvc0
->state
.uniform_buffer_bound
[s
] = 0;
488 /* Invalidate all COMPUTE constbufs because they are aliased with 3D. */
489 nvc0
->dirty_cp
|= NVC0_NEW_CP_CONSTBUF
;
490 nvc0
->constbuf_dirty
[5] |= nvc0
->constbuf_valid
[5];
491 nvc0
->state
.uniform_buffer_bound
[5] = 0;
495 nvc0_validate_buffers(struct nvc0_context
*nvc0
)
497 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
498 struct nvc0_screen
*screen
= nvc0
->screen
;
501 for (s
= 0; s
< 5; s
++) {
502 BEGIN_NVC0(push
, NVC0_3D(CB_SIZE
), 3);
503 PUSH_DATA (push
, 2048);
504 PUSH_DATAh(push
, screen
->uniform_bo
->offset
+ NVC0_CB_AUX_INFO(s
));
505 PUSH_DATA (push
, screen
->uniform_bo
->offset
+ NVC0_CB_AUX_INFO(s
));
506 BEGIN_1IC0(push
, NVC0_3D(CB_POS
), 1 + 4 * NVC0_MAX_BUFFERS
);
507 PUSH_DATA (push
, NVC0_CB_AUX_BUF_INFO(0));
508 for (i
= 0; i
< NVC0_MAX_BUFFERS
; i
++) {
509 if (nvc0
->buffers
[s
][i
].buffer
) {
510 struct nv04_resource
*res
=
511 nv04_resource(nvc0
->buffers
[s
][i
].buffer
);
512 PUSH_DATA (push
, res
->address
+ nvc0
->buffers
[s
][i
].buffer_offset
);
513 PUSH_DATAh(push
, res
->address
+ nvc0
->buffers
[s
][i
].buffer_offset
);
514 PUSH_DATA (push
, nvc0
->buffers
[s
][i
].buffer_size
);
516 BCTX_REFN(nvc0
->bufctx_3d
, 3D_BUF
, res
, RDWR
);
529 nvc0_validate_sample_mask(struct nvc0_context
*nvc0
)
531 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
535 nvc0
->sample_mask
& 0xffff,
536 nvc0
->sample_mask
& 0xffff,
537 nvc0
->sample_mask
& 0xffff,
538 nvc0
->sample_mask
& 0xffff
541 BEGIN_NVC0(push
, NVC0_3D(MSAA_MASK(0)), 4);
542 PUSH_DATA (push
, mask
[0]);
543 PUSH_DATA (push
, mask
[1]);
544 PUSH_DATA (push
, mask
[2]);
545 PUSH_DATA (push
, mask
[3]);
549 nvc0_validate_min_samples(struct nvc0_context
*nvc0
)
551 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
554 samples
= util_next_power_of_two(nvc0
->min_samples
);
556 // If we're using the incoming sample mask and doing sample shading, we
557 // have to do sample shading "to the max", otherwise there's no way to
558 // tell which sets of samples are covered by the current invocation.
559 if (nvc0
->fragprog
->fp
.sample_mask_in
)
560 samples
= util_framebuffer_get_num_samples(&nvc0
->framebuffer
);
561 samples
|= NVC0_3D_SAMPLE_SHADING_ENABLE
;
564 IMMED_NVC0(push
, NVC0_3D(SAMPLE_SHADING
), samples
);
568 nvc0_validate_driverconst(struct nvc0_context
*nvc0
)
570 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
571 struct nvc0_screen
*screen
= nvc0
->screen
;
574 for (i
= 0; i
< 5; ++i
) {
575 BEGIN_NVC0(push
, NVC0_3D(CB_SIZE
), 3);
576 PUSH_DATA (push
, 2048);
577 PUSH_DATAh(push
, screen
->uniform_bo
->offset
+ NVC0_CB_AUX_INFO(i
));
578 PUSH_DATA (push
, screen
->uniform_bo
->offset
+ NVC0_CB_AUX_INFO(i
));
579 BEGIN_NVC0(push
, NVC0_3D(CB_BIND(i
)), 1);
580 PUSH_DATA (push
, (15 << 4) | 1);
583 nvc0
->dirty_cp
|= NVC0_NEW_CP_DRIVERCONST
;
587 nvc0_validate_derived_1(struct nvc0_context
*nvc0
)
589 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
590 bool rasterizer_discard
;
592 if (nvc0
->rast
&& nvc0
->rast
->pipe
.rasterizer_discard
) {
593 rasterizer_discard
= true;
595 bool zs
= nvc0
->zsa
&&
596 (nvc0
->zsa
->pipe
.depth
.enabled
|| nvc0
->zsa
->pipe
.stencil
[0].enabled
);
597 rasterizer_discard
= !zs
&&
598 (!nvc0
->fragprog
|| !nvc0
->fragprog
->hdr
[18]);
601 if (rasterizer_discard
!= nvc0
->state
.rasterizer_discard
) {
602 nvc0
->state
.rasterizer_discard
= rasterizer_discard
;
603 IMMED_NVC0(push
, NVC0_3D(RASTERIZE_ENABLE
), !rasterizer_discard
);
607 /* alpha test is disabled if there are no color RTs, so make sure we have at
608 * least one if alpha test is enabled. Note that this must run after
609 * nvc0_validate_fb, otherwise that will override the RT count setting.
612 nvc0_validate_derived_2(struct nvc0_context
*nvc0
)
614 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
616 if (nvc0
->zsa
&& nvc0
->zsa
->pipe
.alpha
.enabled
&&
617 nvc0
->framebuffer
.zsbuf
&&
618 nvc0
->framebuffer
.nr_cbufs
== 0) {
619 nvc0_fb_set_null_rt(push
, 0, 0);
620 BEGIN_NVC0(push
, NVC0_3D(RT_CONTROL
), 1);
621 PUSH_DATA (push
, (076543210 << 4) | 1);
626 nvc0_validate_derived_3(struct nvc0_context
*nvc0
)
628 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
629 struct pipe_framebuffer_state
*fb
= &nvc0
->framebuffer
;
632 if ((!fb
->nr_cbufs
|| !fb
->cbufs
[0] ||
633 !util_format_is_pure_integer(fb
->cbufs
[0]->format
)) && nvc0
->blend
) {
634 if (nvc0
->blend
->pipe
.alpha_to_coverage
)
635 ms
|= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE
;
636 if (nvc0
->blend
->pipe
.alpha_to_one
)
637 ms
|= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE
;
640 BEGIN_NVC0(push
, NVC0_3D(MULTISAMPLE_CTRL
), 1);
641 PUSH_DATA (push
, ms
);
645 nvc0_validate_tess_state(struct nvc0_context
*nvc0
)
647 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
649 BEGIN_NVC0(push
, NVC0_3D(TESS_LEVEL_OUTER(0)), 6);
650 PUSH_DATAp(push
, nvc0
->default_tess_outer
, 4);
651 PUSH_DATAp(push
, nvc0
->default_tess_inner
, 2);
655 nvc0_switch_pipe_context(struct nvc0_context
*ctx_to
)
657 struct nvc0_context
*ctx_from
= ctx_to
->screen
->cur_ctx
;
661 ctx_to
->state
= ctx_from
->state
;
663 ctx_to
->state
= ctx_to
->screen
->save_state
;
665 ctx_to
->dirty_3d
= ~0;
666 ctx_to
->dirty_cp
= ~0;
667 ctx_to
->viewports_dirty
= ~0;
668 ctx_to
->scissors_dirty
= ~0;
670 for (s
= 0; s
< 6; ++s
) {
671 ctx_to
->samplers_dirty
[s
] = ~0;
672 ctx_to
->textures_dirty
[s
] = ~0;
673 ctx_to
->constbuf_dirty
[s
] = (1 << NVC0_MAX_PIPE_CONSTBUFS
) - 1;
674 ctx_to
->buffers_dirty
[s
] = ~0;
675 ctx_to
->images_dirty
[s
] = ~0;
678 /* Reset tfb as the shader that owns it may have been deleted. */
679 ctx_to
->state
.tfb
= NULL
;
682 ctx_to
->dirty_3d
&= ~(NVC0_NEW_3D_VERTEX
| NVC0_NEW_3D_ARRAYS
);
683 if (!ctx_to
->idxbuf
.buffer
)
684 ctx_to
->dirty_3d
&= ~NVC0_NEW_3D_IDXBUF
;
686 if (!ctx_to
->vertprog
)
687 ctx_to
->dirty_3d
&= ~NVC0_NEW_3D_VERTPROG
;
688 if (!ctx_to
->fragprog
)
689 ctx_to
->dirty_3d
&= ~NVC0_NEW_3D_FRAGPROG
;
692 ctx_to
->dirty_3d
&= ~NVC0_NEW_3D_BLEND
;
694 ctx_to
->dirty_3d
&= ~(NVC0_NEW_3D_RASTERIZER
| NVC0_NEW_3D_SCISSOR
);
696 ctx_to
->dirty_3d
&= ~NVC0_NEW_3D_ZSA
;
698 ctx_to
->screen
->cur_ctx
= ctx_to
;
701 static struct nvc0_state_validate
702 validate_list_3d
[] = {
703 { nvc0_validate_fb
, NVC0_NEW_3D_FRAMEBUFFER
},
704 { nvc0_validate_blend
, NVC0_NEW_3D_BLEND
},
705 { nvc0_validate_zsa
, NVC0_NEW_3D_ZSA
},
706 { nvc0_validate_sample_mask
, NVC0_NEW_3D_SAMPLE_MASK
},
707 { nvc0_validate_rasterizer
, NVC0_NEW_3D_RASTERIZER
},
708 { nvc0_validate_blend_colour
, NVC0_NEW_3D_BLEND_COLOUR
},
709 { nvc0_validate_stencil_ref
, NVC0_NEW_3D_STENCIL_REF
},
710 { nvc0_validate_stipple
, NVC0_NEW_3D_STIPPLE
},
711 { nvc0_validate_scissor
, NVC0_NEW_3D_SCISSOR
| NVC0_NEW_3D_RASTERIZER
},
712 { nvc0_validate_viewport
, NVC0_NEW_3D_VIEWPORT
},
713 { nvc0_vertprog_validate
, NVC0_NEW_3D_VERTPROG
},
714 { nvc0_tctlprog_validate
, NVC0_NEW_3D_TCTLPROG
},
715 { nvc0_tevlprog_validate
, NVC0_NEW_3D_TEVLPROG
},
716 { nvc0_validate_tess_state
, NVC0_NEW_3D_TESSFACTOR
},
717 { nvc0_gmtyprog_validate
, NVC0_NEW_3D_GMTYPROG
},
718 { nvc0_validate_min_samples
, NVC0_NEW_3D_MIN_SAMPLES
|
719 NVC0_NEW_3D_FRAGPROG
|
720 NVC0_NEW_3D_FRAMEBUFFER
},
721 { nvc0_fragprog_validate
, NVC0_NEW_3D_FRAGPROG
| NVC0_NEW_3D_RASTERIZER
},
722 { nvc0_validate_derived_1
, NVC0_NEW_3D_FRAGPROG
| NVC0_NEW_3D_ZSA
|
723 NVC0_NEW_3D_RASTERIZER
},
724 { nvc0_validate_derived_2
, NVC0_NEW_3D_ZSA
| NVC0_NEW_3D_FRAMEBUFFER
},
725 { nvc0_validate_derived_3
, NVC0_NEW_3D_BLEND
| NVC0_NEW_3D_FRAMEBUFFER
},
726 { nvc0_validate_clip
, NVC0_NEW_3D_CLIP
| NVC0_NEW_3D_RASTERIZER
|
727 NVC0_NEW_3D_VERTPROG
|
728 NVC0_NEW_3D_TEVLPROG
|
729 NVC0_NEW_3D_GMTYPROG
},
730 { nvc0_constbufs_validate
, NVC0_NEW_3D_CONSTBUF
},
731 { nvc0_validate_textures
, NVC0_NEW_3D_TEXTURES
},
732 { nvc0_validate_samplers
, NVC0_NEW_3D_SAMPLERS
},
733 { nve4_set_tex_handles
, NVC0_NEW_3D_TEXTURES
| NVC0_NEW_3D_SAMPLERS
},
734 { nvc0_vertex_arrays_validate
, NVC0_NEW_3D_VERTEX
| NVC0_NEW_3D_ARRAYS
},
735 { nvc0_validate_surfaces
, NVC0_NEW_3D_SURFACES
},
736 { nvc0_validate_buffers
, NVC0_NEW_3D_BUFFERS
},
737 { nvc0_idxbuf_validate
, NVC0_NEW_3D_IDXBUF
},
738 { nvc0_tfb_validate
, NVC0_NEW_3D_TFB_TARGETS
| NVC0_NEW_3D_GMTYPROG
},
739 { nvc0_validate_driverconst
, NVC0_NEW_3D_DRIVERCONST
},
743 nvc0_state_validate(struct nvc0_context
*nvc0
, uint32_t mask
,
744 struct nvc0_state_validate
*validate_list
, int size
,
745 uint32_t *dirty
, struct nouveau_bufctx
*bufctx
)
751 if (nvc0
->screen
->cur_ctx
!= nvc0
)
752 nvc0_switch_pipe_context(nvc0
);
754 state_mask
= *dirty
& mask
;
757 for (i
= 0; i
< size
; ++i
) {
758 struct nvc0_state_validate
*validate
= &validate_list
[i
];
760 if (state_mask
& validate
->states
)
761 validate
->func(nvc0
);
763 *dirty
&= ~state_mask
;
765 nvc0_bufctx_fence(nvc0
, bufctx
, false);
768 nouveau_pushbuf_bufctx(nvc0
->base
.pushbuf
, bufctx
);
769 ret
= nouveau_pushbuf_validate(nvc0
->base
.pushbuf
);
775 nvc0_state_validate_3d(struct nvc0_context
*nvc0
, uint32_t mask
)
779 ret
= nvc0_state_validate(nvc0
, mask
, validate_list_3d
,
780 ARRAY_SIZE(validate_list_3d
), &nvc0
->dirty_3d
,
783 if (unlikely(nvc0
->state
.flushed
)) {
784 nvc0
->state
.flushed
= false;
785 nvc0_bufctx_fence(nvc0
, nvc0
->bufctx_3d
, true);