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nvc0/cl: hande 64 bit pointers in nvc0_set_global_handle
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_surface.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <stdint.h>
24
25 #include "pipe/p_defines.h"
26
27 #include "util/u_inlines.h"
28 #include "util/u_pack_color.h"
29 #include "util/format/u_format.h"
30 #include "util/u_surface.h"
31
32 #include "tgsi/tgsi_ureg.h"
33
34 #include "os/os_thread.h"
35
36 #include "nvc0/nvc0_context.h"
37 #include "nvc0/nvc0_resource.h"
38
39 #include "nv50/g80_defs.xml.h"
40 #include "nv50/g80_texture.xml.h"
41
42 /* these are used in nv50_blit.h */
43 #define NV50_ENG2D_SUPPORTED_FORMATS 0xff9ccfe1cce3ccc9ULL
44 #define NV50_ENG2D_NOCONVERT_FORMATS 0x009cc02000000000ULL
45 #define NV50_ENG2D_LUMINANCE_FORMATS 0x001cc02000000000ULL
46 #define NV50_ENG2D_INTENSITY_FORMATS 0x0080000000000000ULL
47 #define NV50_ENG2D_OPERATION_FORMATS 0x060001c000638000ULL
48
49 #define NOUVEAU_DRIVER 0xc0
50 #include "nv50/nv50_blit.h"
51
52 static inline uint8_t
53 nvc0_2d_format(enum pipe_format format, bool dst, bool dst_src_equal)
54 {
55 uint8_t id = nvc0_format_table[format].rt;
56
57 /* A8_UNORM is treated as I8_UNORM as far as the 2D engine is concerned. */
58 if (!dst && unlikely(format == PIPE_FORMAT_I8_UNORM) && !dst_src_equal)
59 return G80_SURFACE_FORMAT_A8_UNORM;
60
61 /* Hardware values for color formats range from 0xc0 to 0xff,
62 * but the 2D engine doesn't support all of them.
63 */
64 if (nv50_2d_format_supported(format))
65 return id;
66 assert(dst_src_equal);
67
68 switch (util_format_get_blocksize(format)) {
69 case 1:
70 return G80_SURFACE_FORMAT_R8_UNORM;
71 case 2:
72 return G80_SURFACE_FORMAT_RG8_UNORM;
73 case 4:
74 return G80_SURFACE_FORMAT_BGRA8_UNORM;
75 case 8:
76 return G80_SURFACE_FORMAT_RGBA16_UNORM;
77 case 16:
78 return G80_SURFACE_FORMAT_RGBA32_FLOAT;
79 default:
80 assert(0);
81 return 0;
82 }
83 }
84
85 static int
86 nvc0_2d_texture_set(struct nouveau_pushbuf *push, bool dst,
87 struct nv50_miptree *mt, unsigned level, unsigned layer,
88 enum pipe_format pformat, bool dst_src_pformat_equal)
89 {
90 struct nouveau_bo *bo = mt->base.bo;
91 uint32_t width, height, depth;
92 uint32_t format;
93 uint32_t mthd = dst ? NV50_2D_DST_FORMAT : NV50_2D_SRC_FORMAT;
94 uint32_t offset = mt->level[level].offset;
95
96 format = nvc0_2d_format(pformat, dst, dst_src_pformat_equal);
97 if (!format) {
98 NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
99 util_format_name(pformat));
100 return 1;
101 }
102
103 width = u_minify(mt->base.base.width0, level) << mt->ms_x;
104 height = u_minify(mt->base.base.height0, level) << mt->ms_y;
105 depth = u_minify(mt->base.base.depth0, level);
106
107 /* layer has to be < depth, and depth > tile depth / 2 */
108
109 if (!mt->layout_3d) {
110 offset += mt->layer_stride * layer;
111 layer = 0;
112 depth = 1;
113 } else
114 if (!dst) {
115 offset += nvc0_mt_zslice_offset(mt, level, layer);
116 layer = 0;
117 }
118
119 if (!nouveau_bo_memtype(bo)) {
120 BEGIN_NVC0(push, SUBC_2D(mthd), 2);
121 PUSH_DATA (push, format);
122 PUSH_DATA (push, 1);
123 BEGIN_NVC0(push, SUBC_2D(mthd + 0x14), 5);
124 PUSH_DATA (push, mt->level[level].pitch);
125 PUSH_DATA (push, width);
126 PUSH_DATA (push, height);
127 PUSH_DATAh(push, bo->offset + offset);
128 PUSH_DATA (push, bo->offset + offset);
129 } else {
130 BEGIN_NVC0(push, SUBC_2D(mthd), 5);
131 PUSH_DATA (push, format);
132 PUSH_DATA (push, 0);
133 PUSH_DATA (push, mt->level[level].tile_mode);
134 PUSH_DATA (push, depth);
135 PUSH_DATA (push, layer);
136 BEGIN_NVC0(push, SUBC_2D(mthd + 0x18), 4);
137 PUSH_DATA (push, width);
138 PUSH_DATA (push, height);
139 PUSH_DATAh(push, bo->offset + offset);
140 PUSH_DATA (push, bo->offset + offset);
141 }
142
143 if (dst) {
144 IMMED_NVC0(push, SUBC_2D(NVC0_2D_SET_DST_COLOR_RENDER_TO_ZETA_SURFACE),
145 util_format_is_depth_or_stencil(pformat));
146 }
147
148 #if 0
149 if (dst) {
150 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_CLIP_X), 4);
151 PUSH_DATA (push, 0);
152 PUSH_DATA (push, 0);
153 PUSH_DATA (push, width);
154 PUSH_DATA (push, height);
155 }
156 #endif
157 return 0;
158 }
159
160 static int
161 nvc0_2d_texture_do_copy(struct nouveau_pushbuf *push,
162 struct nv50_miptree *dst, unsigned dst_level,
163 unsigned dx, unsigned dy, unsigned dz,
164 struct nv50_miptree *src, unsigned src_level,
165 unsigned sx, unsigned sy, unsigned sz,
166 unsigned w, unsigned h)
167 {
168 const enum pipe_format dfmt = dst->base.base.format;
169 const enum pipe_format sfmt = src->base.base.format;
170 int ret;
171 bool eqfmt = dfmt == sfmt;
172
173 if (!PUSH_SPACE(push, 2 * 16 + 32))
174 return PIPE_ERROR;
175
176 ret = nvc0_2d_texture_set(push, true, dst, dst_level, dz, dfmt, eqfmt);
177 if (ret)
178 return ret;
179
180 ret = nvc0_2d_texture_set(push, false, src, src_level, sz, sfmt, eqfmt);
181 if (ret)
182 return ret;
183
184 IMMED_NVC0(push, NVC0_2D(BLIT_CONTROL), 0x00);
185 BEGIN_NVC0(push, NVC0_2D(BLIT_DST_X), 4);
186 PUSH_DATA (push, dx << dst->ms_x);
187 PUSH_DATA (push, dy << dst->ms_y);
188 PUSH_DATA (push, w << dst->ms_x);
189 PUSH_DATA (push, h << dst->ms_y);
190 BEGIN_NVC0(push, NVC0_2D(BLIT_DU_DX_FRACT), 4);
191 PUSH_DATA (push, 0);
192 PUSH_DATA (push, 1);
193 PUSH_DATA (push, 0);
194 PUSH_DATA (push, 1);
195 BEGIN_NVC0(push, NVC0_2D(BLIT_SRC_X_FRACT), 4);
196 PUSH_DATA (push, 0);
197 PUSH_DATA (push, sx << src->ms_x);
198 PUSH_DATA (push, 0);
199 PUSH_DATA (push, sy << src->ms_y);
200
201 return 0;
202 }
203
204 static void
205 nvc0_resource_copy_region(struct pipe_context *pipe,
206 struct pipe_resource *dst, unsigned dst_level,
207 unsigned dstx, unsigned dsty, unsigned dstz,
208 struct pipe_resource *src, unsigned src_level,
209 const struct pipe_box *src_box)
210 {
211 struct nvc0_context *nvc0 = nvc0_context(pipe);
212 int ret;
213 bool m2mf;
214 unsigned dst_layer = dstz, src_layer = src_box->z;
215
216 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
217 nouveau_copy_buffer(&nvc0->base,
218 nv04_resource(dst), dstx,
219 nv04_resource(src), src_box->x, src_box->width);
220 NOUVEAU_DRV_STAT(&nvc0->screen->base, buf_copy_bytes, src_box->width);
221 return;
222 }
223 NOUVEAU_DRV_STAT(&nvc0->screen->base, tex_copy_count, 1);
224
225 /* 0 and 1 are equal, only supporting 0/1, 2, 4 and 8 */
226 assert((src->nr_samples | 1) == (dst->nr_samples | 1));
227
228 m2mf = (src->format == dst->format) ||
229 (util_format_get_blocksizebits(src->format) ==
230 util_format_get_blocksizebits(dst->format));
231
232 nv04_resource(dst)->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
233
234 if (m2mf) {
235 struct nv50_miptree *src_mt = nv50_miptree(src);
236 struct nv50_miptree *dst_mt = nv50_miptree(dst);
237 struct nv50_m2mf_rect drect, srect;
238 unsigned i;
239 unsigned nx = util_format_get_nblocksx(src->format, src_box->width)
240 << src_mt->ms_x;
241 unsigned ny = util_format_get_nblocksy(src->format, src_box->height)
242 << src_mt->ms_y;
243
244 nv50_m2mf_rect_setup(&drect, dst, dst_level, dstx, dsty, dstz);
245 nv50_m2mf_rect_setup(&srect, src, src_level,
246 src_box->x, src_box->y, src_box->z);
247
248 for (i = 0; i < src_box->depth; ++i) {
249 nvc0->m2mf_copy_rect(nvc0, &drect, &srect, nx, ny);
250
251 if (dst_mt->layout_3d)
252 drect.z++;
253 else
254 drect.base += dst_mt->layer_stride;
255
256 if (src_mt->layout_3d)
257 srect.z++;
258 else
259 srect.base += src_mt->layer_stride;
260 }
261 return;
262 }
263
264 assert(nv50_2d_dst_format_faithful(dst->format));
265 assert(nv50_2d_src_format_faithful(src->format));
266
267 BCTX_REFN(nvc0->bufctx, 2D, nv04_resource(src), RD);
268 BCTX_REFN(nvc0->bufctx, 2D, nv04_resource(dst), WR);
269 nouveau_pushbuf_bufctx(nvc0->base.pushbuf, nvc0->bufctx);
270 nouveau_pushbuf_validate(nvc0->base.pushbuf);
271
272 for (; dst_layer < dstz + src_box->depth; ++dst_layer, ++src_layer) {
273 ret = nvc0_2d_texture_do_copy(nvc0->base.pushbuf,
274 nv50_miptree(dst), dst_level,
275 dstx, dsty, dst_layer,
276 nv50_miptree(src), src_level,
277 src_box->x, src_box->y, src_layer,
278 src_box->width, src_box->height);
279 if (ret)
280 break;
281 }
282 nouveau_bufctx_reset(nvc0->bufctx, 0);
283 }
284
285 static void
286 nvc0_clear_render_target(struct pipe_context *pipe,
287 struct pipe_surface *dst,
288 const union pipe_color_union *color,
289 unsigned dstx, unsigned dsty,
290 unsigned width, unsigned height,
291 bool render_condition_enabled)
292 {
293 struct nvc0_context *nvc0 = nvc0_context(pipe);
294 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
295 struct nv50_surface *sf = nv50_surface(dst);
296 struct nv04_resource *res = nv04_resource(sf->base.texture);
297 unsigned z;
298
299 assert(dst->texture->target != PIPE_BUFFER);
300
301 if (!PUSH_SPACE(push, 32 + sf->depth))
302 return;
303
304 PUSH_REFN (push, res->bo, res->domain | NOUVEAU_BO_WR);
305
306 BEGIN_NVC0(push, NVC0_3D(CLEAR_COLOR(0)), 4);
307 PUSH_DATAf(push, color->f[0]);
308 PUSH_DATAf(push, color->f[1]);
309 PUSH_DATAf(push, color->f[2]);
310 PUSH_DATAf(push, color->f[3]);
311
312 BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
313 PUSH_DATA (push, ( width << 16) | dstx);
314 PUSH_DATA (push, (height << 16) | dsty);
315
316 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
317 PUSH_DATA (push, 1);
318 BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(0)), 9);
319 PUSH_DATAh(push, res->address + sf->offset);
320 PUSH_DATA (push, res->address + sf->offset);
321 if (likely(nouveau_bo_memtype(res->bo))) {
322 struct nv50_miptree *mt = nv50_miptree(dst->texture);
323
324 PUSH_DATA(push, sf->width);
325 PUSH_DATA(push, sf->height);
326 PUSH_DATA(push, nvc0_format_table[dst->format].rt);
327 PUSH_DATA(push, (mt->layout_3d << 16) |
328 mt->level[sf->base.u.tex.level].tile_mode);
329 PUSH_DATA(push, dst->u.tex.first_layer + sf->depth);
330 PUSH_DATA(push, mt->layer_stride >> 2);
331 PUSH_DATA(push, dst->u.tex.first_layer);
332 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), mt->ms_mode);
333 } else {
334 if (res->base.target == PIPE_BUFFER) {
335 PUSH_DATA(push, 262144);
336 PUSH_DATA(push, 1);
337 } else {
338 PUSH_DATA(push, nv50_miptree(&res->base)->level[0].pitch);
339 PUSH_DATA(push, sf->height);
340 }
341 PUSH_DATA(push, nvc0_format_table[sf->base.format].rt);
342 PUSH_DATA(push, 1 << 12);
343 PUSH_DATA(push, 1);
344 PUSH_DATA(push, 0);
345 PUSH_DATA(push, 0);
346
347 IMMED_NVC0(push, NVC0_3D(ZETA_ENABLE), 0);
348 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 0);
349
350 /* tiled textures don't have to be fenced, they're not mapped directly */
351 nvc0_resource_fence(res, NOUVEAU_BO_WR);
352 }
353
354 if (!render_condition_enabled)
355 IMMED_NVC0(push, NVC0_3D(COND_MODE), NVC0_3D_COND_MODE_ALWAYS);
356
357 BEGIN_NIC0(push, NVC0_3D(CLEAR_BUFFERS), sf->depth);
358 for (z = 0; z < sf->depth; ++z) {
359 PUSH_DATA (push, 0x3c |
360 (z << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
361 }
362
363 if (!render_condition_enabled)
364 IMMED_NVC0(push, NVC0_3D(COND_MODE), nvc0->cond_condmode);
365
366 nvc0->dirty_3d |= NVC0_NEW_3D_FRAMEBUFFER;
367 }
368
369 static void
370 nvc0_clear_buffer_push_nvc0(struct pipe_context *pipe,
371 struct pipe_resource *res,
372 unsigned offset, unsigned size,
373 const void *data, int data_size)
374 {
375 struct nvc0_context *nvc0 = nvc0_context(pipe);
376 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
377 struct nv04_resource *buf = nv04_resource(res);
378 unsigned i;
379
380 nouveau_bufctx_refn(nvc0->bufctx, 0, buf->bo, buf->domain | NOUVEAU_BO_WR);
381 nouveau_pushbuf_bufctx(push, nvc0->bufctx);
382 nouveau_pushbuf_validate(push);
383
384 unsigned count = (size + 3) / 4;
385 unsigned data_words = data_size / 4;
386
387 while (count) {
388 unsigned nr_data = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN) / data_words;
389 unsigned nr = nr_data * data_words;
390
391 if (!PUSH_SPACE(push, nr + 9))
392 break;
393
394 BEGIN_NVC0(push, NVC0_M2MF(OFFSET_OUT_HIGH), 2);
395 PUSH_DATAh(push, buf->address + offset);
396 PUSH_DATA (push, buf->address + offset);
397 BEGIN_NVC0(push, NVC0_M2MF(LINE_LENGTH_IN), 2);
398 PUSH_DATA (push, MIN2(size, nr * 4));
399 PUSH_DATA (push, 1);
400 BEGIN_NVC0(push, NVC0_M2MF(EXEC), 1);
401 PUSH_DATA (push, 0x100111);
402
403 /* must not be interrupted (trap on QUERY fence, 0x50 works however) */
404 BEGIN_NIC0(push, NVC0_M2MF(DATA), nr);
405 for (i = 0; i < nr_data; i++)
406 PUSH_DATAp(push, data, data_words);
407
408 count -= nr;
409 offset += nr * 4;
410 size -= nr * 4;
411 }
412
413 nvc0_resource_validate(buf, NOUVEAU_BO_WR);
414
415 nouveau_bufctx_reset(nvc0->bufctx, 0);
416 }
417
418 static void
419 nvc0_clear_buffer_push_nve4(struct pipe_context *pipe,
420 struct pipe_resource *res,
421 unsigned offset, unsigned size,
422 const void *data, int data_size)
423 {
424 struct nvc0_context *nvc0 = nvc0_context(pipe);
425 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
426 struct nv04_resource *buf = nv04_resource(res);
427 unsigned i;
428
429 nouveau_bufctx_refn(nvc0->bufctx, 0, buf->bo, buf->domain | NOUVEAU_BO_WR);
430 nouveau_pushbuf_bufctx(push, nvc0->bufctx);
431 nouveau_pushbuf_validate(push);
432
433 unsigned count = (size + 3) / 4;
434 unsigned data_words = data_size / 4;
435
436 while (count) {
437 unsigned nr_data = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN) / data_words;
438 unsigned nr = nr_data * data_words;
439
440 if (!PUSH_SPACE(push, nr + 10))
441 break;
442
443 BEGIN_NVC0(push, NVE4_P2MF(UPLOAD_DST_ADDRESS_HIGH), 2);
444 PUSH_DATAh(push, buf->address + offset);
445 PUSH_DATA (push, buf->address + offset);
446 BEGIN_NVC0(push, NVE4_P2MF(UPLOAD_LINE_LENGTH_IN), 2);
447 PUSH_DATA (push, MIN2(size, nr * 4));
448 PUSH_DATA (push, 1);
449 /* must not be interrupted (trap on QUERY fence, 0x50 works however) */
450 BEGIN_1IC0(push, NVE4_P2MF(UPLOAD_EXEC), nr + 1);
451 PUSH_DATA (push, 0x1001);
452 for (i = 0; i < nr_data; i++)
453 PUSH_DATAp(push, data, data_words);
454
455 count -= nr;
456 offset += nr * 4;
457 size -= nr * 4;
458 }
459
460 nvc0_resource_validate(buf, NOUVEAU_BO_WR);
461
462 nouveau_bufctx_reset(nvc0->bufctx, 0);
463 }
464
465 static void
466 nvc0_clear_buffer_push(struct pipe_context *pipe,
467 struct pipe_resource *res,
468 unsigned offset, unsigned size,
469 const void *data, int data_size)
470 {
471 struct nvc0_context *nvc0 = nvc0_context(pipe);
472 unsigned tmp;
473
474 if (data_size == 1) {
475 tmp = *(unsigned char *)data;
476 tmp = (tmp << 24) | (tmp << 16) | (tmp << 8) | tmp;
477 data = &tmp;
478 data_size = 4;
479 } else if (data_size == 2) {
480 tmp = *(unsigned short *)data;
481 tmp = (tmp << 16) | tmp;
482 data = &tmp;
483 data_size = 4;
484 }
485
486 if (nvc0->screen->base.class_3d < NVE4_3D_CLASS)
487 nvc0_clear_buffer_push_nvc0(pipe, res, offset, size, data, data_size);
488 else
489 nvc0_clear_buffer_push_nve4(pipe, res, offset, size, data, data_size);
490 }
491
492 static void
493 nvc0_clear_buffer(struct pipe_context *pipe,
494 struct pipe_resource *res,
495 unsigned offset, unsigned size,
496 const void *data, int data_size)
497 {
498 struct nvc0_context *nvc0 = nvc0_context(pipe);
499 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
500 struct nv04_resource *buf = nv04_resource(res);
501 union pipe_color_union color;
502 enum pipe_format dst_fmt;
503 unsigned width, height, elements;
504
505 assert(res->target == PIPE_BUFFER);
506 assert(nouveau_bo_memtype(buf->bo) == 0);
507
508 switch (data_size) {
509 case 16:
510 dst_fmt = PIPE_FORMAT_R32G32B32A32_UINT;
511 memcpy(&color.ui, data, 16);
512 break;
513 case 12:
514 /* RGB32 is not a valid RT format. This will be handled by the pushbuf
515 * uploader.
516 */
517 dst_fmt = PIPE_FORMAT_NONE; /* Init dst_fmt to silence gcc warning */
518 break;
519 case 8:
520 dst_fmt = PIPE_FORMAT_R32G32_UINT;
521 memcpy(&color.ui, data, 8);
522 memset(&color.ui[2], 0, 8);
523 break;
524 case 4:
525 dst_fmt = PIPE_FORMAT_R32_UINT;
526 memcpy(&color.ui, data, 4);
527 memset(&color.ui[1], 0, 12);
528 break;
529 case 2:
530 dst_fmt = PIPE_FORMAT_R16_UINT;
531 color.ui[0] = util_cpu_to_le32(
532 util_le16_to_cpu(*(unsigned short *)data));
533 memset(&color.ui[1], 0, 12);
534 break;
535 case 1:
536 dst_fmt = PIPE_FORMAT_R8_UINT;
537 color.ui[0] = util_cpu_to_le32(*(unsigned char *)data);
538 memset(&color.ui[1], 0, 12);
539 break;
540 default:
541 assert(!"Unsupported element size");
542 return;
543 }
544
545 util_range_add(&buf->base, &buf->valid_buffer_range, offset, offset + size);
546
547 assert(size % data_size == 0);
548
549 if (data_size == 12) {
550 nvc0_clear_buffer_push(pipe, res, offset, size, data, data_size);
551 return;
552 }
553
554 if (offset & 0xff) {
555 unsigned fixup_size = MIN2(size, align(offset, 0x100) - offset);
556 assert(fixup_size % data_size == 0);
557 nvc0_clear_buffer_push(pipe, res, offset, fixup_size, data, data_size);
558 offset += fixup_size;
559 size -= fixup_size;
560 if (!size)
561 return;
562 }
563
564 elements = size / data_size;
565 height = (elements + 16383) / 16384;
566 width = elements / height;
567 if (height > 1)
568 width &= ~0xff;
569 assert(width > 0);
570
571 if (!PUSH_SPACE(push, 40))
572 return;
573
574 PUSH_REFN (push, buf->bo, buf->domain | NOUVEAU_BO_WR);
575
576 BEGIN_NVC0(push, NVC0_3D(CLEAR_COLOR(0)), 4);
577 PUSH_DATA (push, color.ui[0]);
578 PUSH_DATA (push, color.ui[1]);
579 PUSH_DATA (push, color.ui[2]);
580 PUSH_DATA (push, color.ui[3]);
581 BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
582 PUSH_DATA (push, width << 16);
583 PUSH_DATA (push, height << 16);
584
585 IMMED_NVC0(push, NVC0_3D(RT_CONTROL), 1);
586
587 BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(0)), 9);
588 PUSH_DATAh(push, buf->address + offset);
589 PUSH_DATA (push, buf->address + offset);
590 PUSH_DATA (push, align(width * data_size, 0x100));
591 PUSH_DATA (push, height);
592 PUSH_DATA (push, nvc0_format_table[dst_fmt].rt);
593 PUSH_DATA (push, NVC0_3D_RT_TILE_MODE_LINEAR);
594 PUSH_DATA (push, 1);
595 PUSH_DATA (push, 0);
596 PUSH_DATA (push, 0);
597
598 IMMED_NVC0(push, NVC0_3D(ZETA_ENABLE), 0);
599 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 0);
600
601 IMMED_NVC0(push, NVC0_3D(COND_MODE), NVC0_3D_COND_MODE_ALWAYS);
602
603 IMMED_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 0x3c);
604
605 IMMED_NVC0(push, NVC0_3D(COND_MODE), nvc0->cond_condmode);
606
607 nvc0_resource_validate(buf, NOUVEAU_BO_WR);
608
609 if (width * height != elements) {
610 offset += width * height * data_size;
611 width = elements - width * height;
612 nvc0_clear_buffer_push(pipe, res, offset, width * data_size,
613 data, data_size);
614 }
615
616 nvc0->dirty_3d |= NVC0_NEW_3D_FRAMEBUFFER;
617 }
618
619 static void
620 nvc0_clear_depth_stencil(struct pipe_context *pipe,
621 struct pipe_surface *dst,
622 unsigned clear_flags,
623 double depth,
624 unsigned stencil,
625 unsigned dstx, unsigned dsty,
626 unsigned width, unsigned height,
627 bool render_condition_enabled)
628 {
629 struct nvc0_context *nvc0 = nvc0_context(pipe);
630 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
631 struct nv50_miptree *mt = nv50_miptree(dst->texture);
632 struct nv50_surface *sf = nv50_surface(dst);
633 uint32_t mode = 0;
634 int unk = mt->base.base.target == PIPE_TEXTURE_2D;
635 unsigned z;
636
637 assert(dst->texture->target != PIPE_BUFFER);
638
639 if (!PUSH_SPACE(push, 32 + sf->depth))
640 return;
641
642 PUSH_REFN (push, mt->base.bo, mt->base.domain | NOUVEAU_BO_WR);
643
644 if (clear_flags & PIPE_CLEAR_DEPTH) {
645 BEGIN_NVC0(push, NVC0_3D(CLEAR_DEPTH), 1);
646 PUSH_DATAf(push, depth);
647 mode |= NVC0_3D_CLEAR_BUFFERS_Z;
648 }
649
650 if (clear_flags & PIPE_CLEAR_STENCIL) {
651 BEGIN_NVC0(push, NVC0_3D(CLEAR_STENCIL), 1);
652 PUSH_DATA (push, stencil & 0xff);
653 mode |= NVC0_3D_CLEAR_BUFFERS_S;
654 }
655
656 BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
657 PUSH_DATA (push, ( width << 16) | dstx);
658 PUSH_DATA (push, (height << 16) | dsty);
659
660 BEGIN_NVC0(push, NVC0_3D(ZETA_ADDRESS_HIGH), 5);
661 PUSH_DATAh(push, mt->base.address + sf->offset);
662 PUSH_DATA (push, mt->base.address + sf->offset);
663 PUSH_DATA (push, nvc0_format_table[dst->format].rt);
664 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
665 PUSH_DATA (push, mt->layer_stride >> 2);
666 BEGIN_NVC0(push, NVC0_3D(ZETA_ENABLE), 1);
667 PUSH_DATA (push, 1);
668 BEGIN_NVC0(push, NVC0_3D(ZETA_HORIZ), 3);
669 PUSH_DATA (push, sf->width);
670 PUSH_DATA (push, sf->height);
671 PUSH_DATA (push, (unk << 16) | (dst->u.tex.first_layer + sf->depth));
672 BEGIN_NVC0(push, NVC0_3D(ZETA_BASE_LAYER), 1);
673 PUSH_DATA (push, dst->u.tex.first_layer);
674 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), mt->ms_mode);
675
676 if (!render_condition_enabled)
677 IMMED_NVC0(push, NVC0_3D(COND_MODE), NVC0_3D_COND_MODE_ALWAYS);
678
679 BEGIN_NIC0(push, NVC0_3D(CLEAR_BUFFERS), sf->depth);
680 for (z = 0; z < sf->depth; ++z) {
681 PUSH_DATA (push, mode |
682 (z << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
683 }
684
685 if (!render_condition_enabled)
686 IMMED_NVC0(push, NVC0_3D(COND_MODE), nvc0->cond_condmode);
687
688 nvc0->dirty_3d |= NVC0_NEW_3D_FRAMEBUFFER;
689 }
690
691 void
692 nvc0_clear(struct pipe_context *pipe, unsigned buffers,
693 const struct pipe_scissor_state *scissor_state,
694 const union pipe_color_union *color,
695 double depth, unsigned stencil)
696 {
697 struct nvc0_context *nvc0 = nvc0_context(pipe);
698 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
699 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
700 unsigned i, j, k;
701 uint32_t mode = 0;
702
703 /* don't need NEW_BLEND, COLOR_MASK doesn't affect CLEAR_BUFFERS */
704 if (!nvc0_state_validate_3d(nvc0, NVC0_NEW_3D_FRAMEBUFFER))
705 return;
706
707 if (buffers & PIPE_CLEAR_COLOR && fb->nr_cbufs) {
708 BEGIN_NVC0(push, NVC0_3D(CLEAR_COLOR(0)), 4);
709 PUSH_DATAf(push, color->f[0]);
710 PUSH_DATAf(push, color->f[1]);
711 PUSH_DATAf(push, color->f[2]);
712 PUSH_DATAf(push, color->f[3]);
713 if (buffers & PIPE_CLEAR_COLOR0)
714 mode =
715 NVC0_3D_CLEAR_BUFFERS_R | NVC0_3D_CLEAR_BUFFERS_G |
716 NVC0_3D_CLEAR_BUFFERS_B | NVC0_3D_CLEAR_BUFFERS_A;
717 }
718
719 if (buffers & PIPE_CLEAR_DEPTH) {
720 BEGIN_NVC0(push, NVC0_3D(CLEAR_DEPTH), 1);
721 PUSH_DATA (push, fui(depth));
722 mode |= NVC0_3D_CLEAR_BUFFERS_Z;
723 }
724
725 if (buffers & PIPE_CLEAR_STENCIL) {
726 BEGIN_NVC0(push, NVC0_3D(CLEAR_STENCIL), 1);
727 PUSH_DATA (push, stencil & 0xff);
728 mode |= NVC0_3D_CLEAR_BUFFERS_S;
729 }
730
731 if (mode) {
732 int zs_layers = 0, color0_layers = 0;
733 if (fb->cbufs[0] && (mode & 0x3c))
734 color0_layers = fb->cbufs[0]->u.tex.last_layer -
735 fb->cbufs[0]->u.tex.first_layer + 1;
736 if (fb->zsbuf && (mode & ~0x3c))
737 zs_layers = fb->zsbuf->u.tex.last_layer -
738 fb->zsbuf->u.tex.first_layer + 1;
739
740 for (j = 0; j < MIN2(zs_layers, color0_layers); j++) {
741 BEGIN_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 1);
742 PUSH_DATA(push, mode | (j << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
743 }
744 for (k = j; k < zs_layers; k++) {
745 BEGIN_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 1);
746 PUSH_DATA(push, (mode & ~0x3c) | (k << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
747 }
748 for (k = j; k < color0_layers; k++) {
749 BEGIN_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 1);
750 PUSH_DATA(push, (mode & 0x3c) | (k << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
751 }
752 }
753
754 for (i = 1; i < fb->nr_cbufs; i++) {
755 struct pipe_surface *sf = fb->cbufs[i];
756 if (!sf || !(buffers & (PIPE_CLEAR_COLOR0 << i)))
757 continue;
758 for (j = 0; j <= sf->u.tex.last_layer - sf->u.tex.first_layer; j++) {
759 BEGIN_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 1);
760 PUSH_DATA (push, (i << 6) | 0x3c |
761 (j << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
762 }
763 }
764 }
765
766 static void
767 gm200_evaluate_depth_buffer(struct pipe_context *pipe)
768 {
769 struct nvc0_context *nvc0 = nvc0_context(pipe);
770 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
771
772 nvc0_state_validate_3d(nvc0, NVC0_NEW_3D_FRAMEBUFFER);
773 IMMED_NVC0(push, SUBC_3D(0x11fc), 1);
774 }
775
776
777 /* =============================== BLIT CODE ===================================
778 */
779
780 struct nvc0_blitter
781 {
782 struct nvc0_program *fp[NV50_BLIT_MAX_TEXTURE_TYPES][NV50_BLIT_MODES];
783 struct nvc0_program *vp;
784
785 struct nv50_tsc_entry sampler[2]; /* nearest, bilinear */
786
787 mtx_t mutex;
788
789 struct nvc0_screen *screen;
790 };
791
792 struct nvc0_blitctx
793 {
794 struct nvc0_context *nvc0;
795 struct nvc0_program *fp;
796 struct nvc0_program *vp;
797 uint8_t mode;
798 uint16_t color_mask;
799 uint8_t filter;
800 uint8_t render_condition_enable;
801 enum pipe_texture_target target;
802 struct {
803 struct pipe_framebuffer_state fb;
804 struct nvc0_window_rect_stateobj window_rect;
805 struct nvc0_rasterizer_stateobj *rast;
806 struct nvc0_program *vp;
807 struct nvc0_program *tcp;
808 struct nvc0_program *tep;
809 struct nvc0_program *gp;
810 struct nvc0_program *fp;
811 unsigned num_textures[5];
812 unsigned num_samplers[5];
813 struct pipe_sampler_view *texture[2];
814 struct nv50_tsc_entry *sampler[2];
815 unsigned min_samples;
816 uint32_t dirty_3d;
817 } saved;
818 struct nvc0_rasterizer_stateobj rast;
819 };
820
821 static void *
822 nvc0_blitter_make_vp(struct pipe_context *pipe)
823 {
824 struct ureg_program *ureg;
825 struct ureg_src ipos, itex;
826 struct ureg_dst opos, otex;
827
828 ureg = ureg_create(PIPE_SHADER_VERTEX);
829 if (!ureg)
830 return NULL;
831
832 opos = ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0);
833 ipos = ureg_DECL_vs_input(ureg, 0);
834 otex = ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, 0);
835 itex = ureg_DECL_vs_input(ureg, 1);
836
837 ureg_MOV(ureg, ureg_writemask(opos, TGSI_WRITEMASK_XY ), ipos);
838 ureg_MOV(ureg, ureg_writemask(otex, TGSI_WRITEMASK_XYZ), itex);
839 ureg_END(ureg);
840
841 return ureg_create_shader_and_destroy(ureg, pipe);
842 }
843
844 static void
845 nvc0_blitter_make_sampler(struct nvc0_blitter *blit)
846 {
847 /* clamp to edge, min/max lod = 0, nearest filtering */
848
849 blit->sampler[0].id = -1;
850
851 blit->sampler[0].tsc[0] = G80_TSC_0_SRGB_CONVERSION |
852 (G80_TSC_WRAP_CLAMP_TO_EDGE << G80_TSC_0_ADDRESS_U__SHIFT) |
853 (G80_TSC_WRAP_CLAMP_TO_EDGE << G80_TSC_0_ADDRESS_V__SHIFT) |
854 (G80_TSC_WRAP_CLAMP_TO_EDGE << G80_TSC_0_ADDRESS_P__SHIFT);
855 blit->sampler[0].tsc[1] =
856 G80_TSC_1_MAG_FILTER_NEAREST |
857 G80_TSC_1_MIN_FILTER_NEAREST |
858 G80_TSC_1_MIP_FILTER_NONE;
859
860 /* clamp to edge, min/max lod = 0, bilinear filtering */
861
862 blit->sampler[1].id = -1;
863
864 blit->sampler[1].tsc[0] = blit->sampler[0].tsc[0];
865 blit->sampler[1].tsc[1] =
866 G80_TSC_1_MAG_FILTER_LINEAR |
867 G80_TSC_1_MIN_FILTER_LINEAR |
868 G80_TSC_1_MIP_FILTER_NONE;
869 }
870
871 static void
872 nvc0_blit_select_vp(struct nvc0_blitctx *ctx)
873 {
874 struct nvc0_blitter *blitter = ctx->nvc0->screen->blitter;
875
876 if (!blitter->vp) {
877 mtx_lock(&blitter->mutex);
878 if (!blitter->vp)
879 blitter->vp = nvc0_blitter_make_vp(&ctx->nvc0->base.pipe);
880 mtx_unlock(&blitter->mutex);
881 }
882 ctx->vp = blitter->vp;
883 }
884
885 static void
886 nvc0_blit_select_fp(struct nvc0_blitctx *ctx, const struct pipe_blit_info *info)
887 {
888 struct nvc0_blitter *blitter = ctx->nvc0->screen->blitter;
889
890 const enum pipe_texture_target ptarg =
891 nv50_blit_reinterpret_pipe_texture_target(info->src.resource->target);
892
893 const unsigned targ = nv50_blit_texture_type(ptarg);
894 const unsigned mode = ctx->mode;
895
896 if (!blitter->fp[targ][mode]) {
897 mtx_lock(&blitter->mutex);
898 if (!blitter->fp[targ][mode])
899 blitter->fp[targ][mode] =
900 nv50_blitter_make_fp(&ctx->nvc0->base.pipe, mode, ptarg);
901 mtx_unlock(&blitter->mutex);
902 }
903 ctx->fp = blitter->fp[targ][mode];
904 }
905
906 static void
907 nvc0_blit_set_dst(struct nvc0_blitctx *ctx,
908 struct pipe_resource *res, unsigned level, unsigned layer,
909 enum pipe_format format)
910 {
911 struct nvc0_context *nvc0 = ctx->nvc0;
912 struct pipe_context *pipe = &nvc0->base.pipe;
913 struct pipe_surface templ;
914
915 if (util_format_is_depth_or_stencil(format))
916 templ.format = nv50_blit_zeta_to_colour_format(format);
917 else
918 templ.format = format;
919
920 templ.u.tex.level = level;
921 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
922
923 if (layer == -1) {
924 templ.u.tex.first_layer = 0;
925 templ.u.tex.last_layer =
926 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
927 }
928
929 nvc0->framebuffer.cbufs[0] = nvc0_miptree_surface_new(pipe, res, &templ);
930 nvc0->framebuffer.nr_cbufs = 1;
931 nvc0->framebuffer.zsbuf = NULL;
932 nvc0->framebuffer.width = nvc0->framebuffer.cbufs[0]->width;
933 nvc0->framebuffer.height = nvc0->framebuffer.cbufs[0]->height;
934 }
935
936 static void
937 nvc0_blit_set_src(struct nvc0_blitctx *ctx,
938 struct pipe_resource *res, unsigned level, unsigned layer,
939 enum pipe_format format, const uint8_t filter)
940 {
941 struct nvc0_context *nvc0 = ctx->nvc0;
942 struct pipe_context *pipe = &nvc0->base.pipe;
943 struct pipe_sampler_view templ;
944 uint32_t flags;
945 unsigned s;
946 enum pipe_texture_target target;
947
948 target = nv50_blit_reinterpret_pipe_texture_target(res->target);
949
950 templ.format = format;
951 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
952 templ.u.tex.first_level = templ.u.tex.last_level = level;
953 templ.swizzle_r = PIPE_SWIZZLE_X;
954 templ.swizzle_g = PIPE_SWIZZLE_Y;
955 templ.swizzle_b = PIPE_SWIZZLE_Z;
956 templ.swizzle_a = PIPE_SWIZZLE_W;
957
958 if (layer == -1) {
959 templ.u.tex.first_layer = 0;
960 templ.u.tex.last_layer =
961 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
962 }
963
964 flags = res->last_level ? 0 : NV50_TEXVIEW_SCALED_COORDS;
965 flags |= NV50_TEXVIEW_ACCESS_RESOLVE;
966 if (filter && res->nr_samples == 8)
967 flags |= NV50_TEXVIEW_FILTER_MSAA8;
968
969 nvc0->textures[4][0] = nvc0_create_texture_view(
970 pipe, res, &templ, flags, target);
971 nvc0->textures[4][1] = NULL;
972
973 for (s = 0; s <= 3; ++s)
974 nvc0->num_textures[s] = 0;
975 nvc0->num_textures[4] = 1;
976
977 templ.format = nv50_zs_to_s_format(format);
978 if (templ.format != format) {
979 nvc0->textures[4][1] = nvc0_create_texture_view(
980 pipe, res, &templ, flags, target);
981 nvc0->num_textures[4] = 2;
982 }
983 }
984
985 static void
986 nvc0_blitctx_prepare_state(struct nvc0_blitctx *blit)
987 {
988 struct nouveau_pushbuf *push = blit->nvc0->base.pushbuf;
989
990 /* TODO: maybe make this a MACRO (if we need more logic) ? */
991
992 if (blit->nvc0->cond_query && !blit->render_condition_enable)
993 IMMED_NVC0(push, NVC0_3D(COND_MODE), NVC0_3D_COND_MODE_ALWAYS);
994
995 /* blend state */
996 BEGIN_NVC0(push, NVC0_3D(COLOR_MASK(0)), 1);
997 PUSH_DATA (push, blit->color_mask);
998 IMMED_NVC0(push, NVC0_3D(BLEND_ENABLE(0)), 0);
999 IMMED_NVC0(push, NVC0_3D(LOGIC_OP_ENABLE), 0);
1000
1001 /* rasterizer state */
1002 IMMED_NVC0(push, NVC0_3D(FRAG_COLOR_CLAMP_EN), 0);
1003 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 0);
1004 BEGIN_NVC0(push, NVC0_3D(MSAA_MASK(0)), 4);
1005 PUSH_DATA (push, 0xffff);
1006 PUSH_DATA (push, 0xffff);
1007 PUSH_DATA (push, 0xffff);
1008 PUSH_DATA (push, 0xffff);
1009 BEGIN_NVC0(push, NVC0_3D(MACRO_POLYGON_MODE_FRONT), 1);
1010 PUSH_DATA (push, NVC0_3D_MACRO_POLYGON_MODE_FRONT_FILL);
1011 BEGIN_NVC0(push, NVC0_3D(MACRO_POLYGON_MODE_BACK), 1);
1012 PUSH_DATA (push, NVC0_3D_MACRO_POLYGON_MODE_BACK_FILL);
1013 IMMED_NVC0(push, NVC0_3D(POLYGON_SMOOTH_ENABLE), 0);
1014 IMMED_NVC0(push, NVC0_3D(POLYGON_OFFSET_FILL_ENABLE), 0);
1015 IMMED_NVC0(push, NVC0_3D(POLYGON_STIPPLE_ENABLE), 0);
1016 IMMED_NVC0(push, NVC0_3D(CULL_FACE_ENABLE), 0);
1017
1018 /* zsa state */
1019 IMMED_NVC0(push, NVC0_3D(DEPTH_TEST_ENABLE), 0);
1020 IMMED_NVC0(push, NVC0_3D(DEPTH_BOUNDS_EN), 0);
1021 IMMED_NVC0(push, NVC0_3D(STENCIL_ENABLE), 0);
1022 IMMED_NVC0(push, NVC0_3D(ALPHA_TEST_ENABLE), 0);
1023
1024 /* disable transform feedback */
1025 IMMED_NVC0(push, NVC0_3D(TFB_ENABLE), 0);
1026 }
1027
1028 static void
1029 nvc0_blitctx_pre_blit(struct nvc0_blitctx *ctx,
1030 const struct pipe_blit_info *info)
1031 {
1032 struct nvc0_context *nvc0 = ctx->nvc0;
1033 struct nvc0_blitter *blitter = nvc0->screen->blitter;
1034 int s;
1035
1036 ctx->saved.fb.width = nvc0->framebuffer.width;
1037 ctx->saved.fb.height = nvc0->framebuffer.height;
1038 ctx->saved.fb.samples = nvc0->framebuffer.samples;
1039 ctx->saved.fb.layers = nvc0->framebuffer.layers;
1040 ctx->saved.fb.nr_cbufs = nvc0->framebuffer.nr_cbufs;
1041 ctx->saved.fb.cbufs[0] = nvc0->framebuffer.cbufs[0];
1042 ctx->saved.fb.zsbuf = nvc0->framebuffer.zsbuf;
1043
1044 ctx->saved.rast = nvc0->rast;
1045
1046 ctx->saved.vp = nvc0->vertprog;
1047 ctx->saved.tcp = nvc0->tctlprog;
1048 ctx->saved.tep = nvc0->tevlprog;
1049 ctx->saved.gp = nvc0->gmtyprog;
1050 ctx->saved.fp = nvc0->fragprog;
1051
1052 ctx->saved.min_samples = nvc0->min_samples;
1053 ctx->saved.window_rect = nvc0->window_rect;
1054
1055 nvc0->rast = &ctx->rast;
1056
1057 nvc0->vertprog = ctx->vp;
1058 nvc0->tctlprog = NULL;
1059 nvc0->tevlprog = NULL;
1060 nvc0->gmtyprog = NULL;
1061 nvc0->fragprog = ctx->fp;
1062
1063 nvc0->window_rect.rects =
1064 MIN2(info->num_window_rectangles, NVC0_MAX_WINDOW_RECTANGLES);
1065 nvc0->window_rect.inclusive = info->window_rectangle_include;
1066 if (nvc0->window_rect.rects)
1067 memcpy(nvc0->window_rect.rect, info->window_rectangles,
1068 sizeof(struct pipe_scissor_state) * nvc0->window_rect.rects);
1069
1070 for (s = 0; s <= 4; ++s) {
1071 ctx->saved.num_textures[s] = nvc0->num_textures[s];
1072 ctx->saved.num_samplers[s] = nvc0->num_samplers[s];
1073 nvc0->textures_dirty[s] = (1 << nvc0->num_textures[s]) - 1;
1074 nvc0->samplers_dirty[s] = (1 << nvc0->num_samplers[s]) - 1;
1075 }
1076 ctx->saved.texture[0] = nvc0->textures[4][0];
1077 ctx->saved.texture[1] = nvc0->textures[4][1];
1078 ctx->saved.sampler[0] = nvc0->samplers[4][0];
1079 ctx->saved.sampler[1] = nvc0->samplers[4][1];
1080
1081 nvc0->samplers[4][0] = &blitter->sampler[ctx->filter];
1082 nvc0->samplers[4][1] = &blitter->sampler[ctx->filter];
1083
1084 for (s = 0; s <= 3; ++s)
1085 nvc0->num_samplers[s] = 0;
1086 nvc0->num_samplers[4] = 2;
1087
1088 nvc0->min_samples = 1;
1089
1090 ctx->saved.dirty_3d = nvc0->dirty_3d;
1091
1092 nvc0->textures_dirty[4] |= 3;
1093 nvc0->samplers_dirty[4] |= 3;
1094
1095 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_FB);
1096 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(4, 0));
1097 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(4, 1));
1098
1099 nvc0->dirty_3d = NVC0_NEW_3D_FRAMEBUFFER | NVC0_NEW_3D_MIN_SAMPLES |
1100 NVC0_NEW_3D_VERTPROG | NVC0_NEW_3D_FRAGPROG |
1101 NVC0_NEW_3D_TCTLPROG | NVC0_NEW_3D_TEVLPROG | NVC0_NEW_3D_GMTYPROG |
1102 NVC0_NEW_3D_TEXTURES | NVC0_NEW_3D_SAMPLERS | NVC0_NEW_3D_WINDOW_RECTS;
1103 }
1104
1105 static void
1106 nvc0_blitctx_post_blit(struct nvc0_blitctx *blit)
1107 {
1108 struct nvc0_context *nvc0 = blit->nvc0;
1109 int s;
1110
1111 pipe_surface_reference(&nvc0->framebuffer.cbufs[0], NULL);
1112
1113 nvc0->framebuffer.width = blit->saved.fb.width;
1114 nvc0->framebuffer.height = blit->saved.fb.height;
1115 nvc0->framebuffer.samples = blit->saved.fb.samples;
1116 nvc0->framebuffer.layers = blit->saved.fb.layers;
1117 nvc0->framebuffer.nr_cbufs = blit->saved.fb.nr_cbufs;
1118 nvc0->framebuffer.cbufs[0] = blit->saved.fb.cbufs[0];
1119 nvc0->framebuffer.zsbuf = blit->saved.fb.zsbuf;
1120
1121 nvc0->rast = blit->saved.rast;
1122
1123 nvc0->vertprog = blit->saved.vp;
1124 nvc0->tctlprog = blit->saved.tcp;
1125 nvc0->tevlprog = blit->saved.tep;
1126 nvc0->gmtyprog = blit->saved.gp;
1127 nvc0->fragprog = blit->saved.fp;
1128
1129 nvc0->min_samples = blit->saved.min_samples;
1130 nvc0->window_rect = blit->saved.window_rect;
1131
1132 pipe_sampler_view_reference(&nvc0->textures[4][0], NULL);
1133 pipe_sampler_view_reference(&nvc0->textures[4][1], NULL);
1134
1135 for (s = 0; s <= 4; ++s) {
1136 nvc0->num_textures[s] = blit->saved.num_textures[s];
1137 nvc0->num_samplers[s] = blit->saved.num_samplers[s];
1138 nvc0->textures_dirty[s] = (1 << nvc0->num_textures[s]) - 1;
1139 nvc0->samplers_dirty[s] = (1 << nvc0->num_samplers[s]) - 1;
1140 }
1141 nvc0->textures[4][0] = blit->saved.texture[0];
1142 nvc0->textures[4][1] = blit->saved.texture[1];
1143 nvc0->samplers[4][0] = blit->saved.sampler[0];
1144 nvc0->samplers[4][1] = blit->saved.sampler[1];
1145
1146 nvc0->textures_dirty[4] |= 3;
1147 nvc0->samplers_dirty[4] |= 3;
1148
1149 if (nvc0->cond_query && !blit->render_condition_enable)
1150 nvc0->base.pipe.render_condition(&nvc0->base.pipe, nvc0->cond_query,
1151 nvc0->cond_cond, nvc0->cond_mode);
1152
1153 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_VTX_TMP);
1154 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEXT);
1155 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_FB);
1156 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(4, 0));
1157 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(4, 1));
1158 nouveau_scratch_done(&nvc0->base);
1159
1160 nvc0->dirty_3d = blit->saved.dirty_3d |
1161 (NVC0_NEW_3D_FRAMEBUFFER | NVC0_NEW_3D_SCISSOR | NVC0_NEW_3D_SAMPLE_MASK |
1162 NVC0_NEW_3D_RASTERIZER | NVC0_NEW_3D_ZSA | NVC0_NEW_3D_BLEND |
1163 NVC0_NEW_3D_VIEWPORT | NVC0_NEW_3D_WINDOW_RECTS |
1164 NVC0_NEW_3D_TEXTURES | NVC0_NEW_3D_SAMPLERS |
1165 NVC0_NEW_3D_VERTPROG | NVC0_NEW_3D_FRAGPROG |
1166 NVC0_NEW_3D_TCTLPROG | NVC0_NEW_3D_TEVLPROG | NVC0_NEW_3D_GMTYPROG |
1167 NVC0_NEW_3D_TFB_TARGETS | NVC0_NEW_3D_VERTEX | NVC0_NEW_3D_ARRAYS);
1168 nvc0->scissors_dirty |= 1;
1169 nvc0->viewports_dirty |= 1;
1170
1171 nvc0->base.pipe.set_min_samples(&nvc0->base.pipe, blit->saved.min_samples);
1172 }
1173
1174 static void
1175 nvc0_blit_3d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
1176 {
1177 struct nvc0_screen *screen = nvc0->screen;
1178 struct nvc0_blitctx *blit = nvc0->blit;
1179 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
1180 struct pipe_resource *src = info->src.resource;
1181 struct pipe_resource *dst = info->dst.resource;
1182 struct nouveau_bo *vtxbuf_bo;
1183 uint32_t stride, length, *vbuf;
1184 uint64_t vtxbuf;
1185 int32_t minx, maxx, miny, maxy;
1186 int32_t i, n;
1187 float x0, x1, y0, y1, z;
1188 float dz;
1189 float x_range, y_range;
1190
1191 blit->mode = nv50_blit_select_mode(info);
1192 blit->color_mask = nv50_blit_derive_color_mask(info);
1193 blit->filter = nv50_blit_get_filter(info);
1194 blit->render_condition_enable = info->render_condition_enable;
1195
1196 nvc0_blit_select_vp(blit);
1197 nvc0_blit_select_fp(blit, info);
1198 nvc0_blitctx_pre_blit(blit, info);
1199
1200 nvc0_blit_set_dst(blit, dst, info->dst.level, -1, info->dst.format);
1201 nvc0_blit_set_src(blit, src, info->src.level, -1, info->src.format,
1202 blit->filter);
1203
1204 nvc0_blitctx_prepare_state(blit);
1205
1206 nvc0_state_validate_3d(nvc0, ~0);
1207
1208 x_range = (float)info->src.box.width / (float)info->dst.box.width;
1209 y_range = (float)info->src.box.height / (float)info->dst.box.height;
1210
1211 x0 = (float)info->src.box.x - x_range * (float)info->dst.box.x;
1212 y0 = (float)info->src.box.y - y_range * (float)info->dst.box.y;
1213
1214 x1 = x0 + 32768.0f * x_range;
1215 y1 = y0 + 32768.0f * y_range;
1216
1217 x0 *= (float)(1 << nv50_miptree(src)->ms_x);
1218 x1 *= (float)(1 << nv50_miptree(src)->ms_x);
1219 y0 *= (float)(1 << nv50_miptree(src)->ms_y);
1220 y1 *= (float)(1 << nv50_miptree(src)->ms_y);
1221
1222 dz = (float)info->src.box.depth / (float)info->dst.box.depth;
1223 z = (float)info->src.box.z;
1224 if (nv50_miptree(src)->layout_3d)
1225 z += 0.5f * dz;
1226
1227 if (src->last_level > 0) {
1228 /* If there are mip maps, GPU always assumes normalized coordinates. */
1229 const unsigned l = info->src.level;
1230 const float fh = u_minify(src->width0 << nv50_miptree(src)->ms_x, l);
1231 const float fv = u_minify(src->height0 << nv50_miptree(src)->ms_y, l);
1232 x0 /= fh;
1233 x1 /= fh;
1234 y0 /= fv;
1235 y1 /= fv;
1236 if (nv50_miptree(src)->layout_3d) {
1237 z /= u_minify(src->depth0, l);
1238 dz /= u_minify(src->depth0, l);
1239 }
1240 }
1241
1242 if (screen->eng3d->oclass >= TU102_3D_CLASS) {
1243 IMMED_NVC0(push, SUBC_3D(TU102_3D_SET_COLOR_RENDER_TO_ZETA_SURFACE),
1244 util_format_is_depth_or_stencil(info->dst.format));
1245 }
1246
1247 IMMED_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 0);
1248 IMMED_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 0x2 |
1249 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_RANGE_0_1);
1250 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_HORIZ(0)), 2);
1251 PUSH_DATA (push, nvc0->framebuffer.width << 16);
1252 PUSH_DATA (push, nvc0->framebuffer.height << 16);
1253
1254 /* Draw a large triangle in screen coordinates covering the whole
1255 * render target, with scissors defining the destination region.
1256 * The vertex is supplied with non-normalized texture coordinates
1257 * arranged in a way to yield the desired offset and scale.
1258 *
1259 * Note that while the source texture is presented to the sampler as
1260 * non-MSAA (even if it is), the destination texture is treated as MSAA for
1261 * rendering. This means that
1262 * - destination coordinates shouldn't be scaled
1263 * - without per-sample rendering, the target will be a solid-fill for all
1264 * of the samples
1265 *
1266 * The last point implies that this process is very bad for 1:1 blits, as
1267 * well as scaled blits between MSAA surfaces. This works fine for
1268 * upscaling and downscaling though. The 1:1 blits should ideally be
1269 * handled by the 2d engine, which can do it perfectly.
1270 */
1271
1272 minx = info->dst.box.x;
1273 maxx = info->dst.box.x + info->dst.box.width;
1274 miny = info->dst.box.y;
1275 maxy = info->dst.box.y + info->dst.box.height;
1276 if (info->scissor_enable) {
1277 minx = MAX2(minx, info->scissor.minx);
1278 maxx = MIN2(maxx, info->scissor.maxx);
1279 miny = MAX2(miny, info->scissor.miny);
1280 maxy = MIN2(maxy, info->scissor.maxy);
1281 }
1282 BEGIN_NVC0(push, NVC0_3D(SCISSOR_HORIZ(0)), 2);
1283 PUSH_DATA (push, (maxx << 16) | minx);
1284 PUSH_DATA (push, (maxy << 16) | miny);
1285
1286 stride = (3 + 2) * 4;
1287 length = stride * 3 * info->dst.box.depth;
1288
1289 vbuf = nouveau_scratch_get(&nvc0->base, length, &vtxbuf, &vtxbuf_bo);
1290 if (!vbuf) {
1291 assert(vbuf);
1292 return;
1293 }
1294
1295 BCTX_REFN_bo(nvc0->bufctx_3d, 3D_VTX_TMP,
1296 NOUVEAU_BO_GART | NOUVEAU_BO_RD, vtxbuf_bo);
1297 BCTX_REFN_bo(nvc0->bufctx_3d, 3D_TEXT,
1298 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD, screen->text);
1299 nouveau_pushbuf_validate(push);
1300
1301 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(0)), 4);
1302 PUSH_DATA (push, NVC0_3D_VERTEX_ARRAY_FETCH_ENABLE | stride <<
1303 NVC0_3D_VERTEX_ARRAY_FETCH_STRIDE__SHIFT);
1304 PUSH_DATAh(push, vtxbuf);
1305 PUSH_DATA (push, vtxbuf);
1306 PUSH_DATA (push, 0);
1307 if (screen->eng3d->oclass < TU102_3D_CLASS)
1308 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_LIMIT_HIGH(0)), 2);
1309 else
1310 BEGIN_NVC0(push, SUBC_3D(TU102_3D_VERTEX_ARRAY_LIMIT_HIGH(0)), 2);
1311 PUSH_DATAh(push, vtxbuf + length - 1);
1312 PUSH_DATA (push, vtxbuf + length - 1);
1313
1314 n = MAX2(2, nvc0->state.num_vtxelts);
1315
1316 BEGIN_NVC0(push, NVC0_3D(VERTEX_ATTRIB_FORMAT(0)), n);
1317 PUSH_DATA (push, NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT |
1318 NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32_32 | 0x00 <<
1319 NVC0_3D_VERTEX_ATTRIB_FORMAT_OFFSET__SHIFT);
1320 PUSH_DATA (push, NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT |
1321 NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32_32_32 | 0x08 <<
1322 NVC0_3D_VERTEX_ATTRIB_FORMAT_OFFSET__SHIFT);
1323 for (i = 2; i < n; i++) {
1324 PUSH_DATA(push, NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT |
1325 NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32 |
1326 NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST);
1327 }
1328 for (i = 1; i < n; ++i)
1329 IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 0);
1330 if (nvc0->state.instance_elts) {
1331 nvc0->state.instance_elts = 0;
1332 BEGIN_NVC0(push, NVC0_3D(MACRO_VERTEX_ARRAY_PER_INSTANCE), 2);
1333 PUSH_DATA (push, n);
1334 PUSH_DATA (push, 0);
1335 }
1336 nvc0->state.num_vtxelts = 2;
1337
1338 if (nvc0->state.prim_restart) {
1339 IMMED_NVC0(push, NVC0_3D(PRIM_RESTART_ENABLE), 0);
1340 nvc0->state.prim_restart = 0;
1341 }
1342
1343 if (nvc0->state.index_bias) {
1344 IMMED_NVC0(push, NVC0_3D(VB_ELEMENT_BASE), 0);
1345 IMMED_NVC0(push, NVC0_3D(VERTEX_ID_BASE), 0);
1346 nvc0->state.index_bias = 0;
1347 }
1348
1349 for (i = 0; i < info->dst.box.depth; ++i, z += dz) {
1350 if (info->dst.box.z + i) {
1351 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1352 PUSH_DATA (push, info->dst.box.z + i);
1353 }
1354
1355 *(vbuf++) = fui(0.0f);
1356 *(vbuf++) = fui(0.0f);
1357 *(vbuf++) = fui(x0);
1358 *(vbuf++) = fui(y0);
1359 *(vbuf++) = fui(z);
1360
1361 *(vbuf++) = fui(32768.0f);
1362 *(vbuf++) = fui(0.0f);
1363 *(vbuf++) = fui(x1);
1364 *(vbuf++) = fui(y0);
1365 *(vbuf++) = fui(z);
1366
1367 *(vbuf++) = fui(0.0f);
1368 *(vbuf++) = fui(32768.0f);
1369 *(vbuf++) = fui(x0);
1370 *(vbuf++) = fui(y1);
1371 *(vbuf++) = fui(z);
1372
1373 IMMED_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL),
1374 NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES);
1375 BEGIN_NVC0(push, NVC0_3D(VERTEX_BUFFER_FIRST), 2);
1376 PUSH_DATA (push, i * 3);
1377 PUSH_DATA (push, 3);
1378 IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
1379 }
1380 if (info->dst.box.z + info->dst.box.depth - 1)
1381 IMMED_NVC0(push, NVC0_3D(LAYER), 0);
1382
1383 nvc0_blitctx_post_blit(blit);
1384
1385 /* restore viewport transform */
1386 IMMED_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1387 if (screen->eng3d->oclass >= TU102_3D_CLASS)
1388 IMMED_NVC0(push, SUBC_3D(TU102_3D_SET_COLOR_RENDER_TO_ZETA_SURFACE), 0);
1389 }
1390
1391 static void
1392 nvc0_blit_eng2d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
1393 {
1394 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
1395 struct nv50_miptree *dst = nv50_miptree(info->dst.resource);
1396 struct nv50_miptree *src = nv50_miptree(info->src.resource);
1397 const int32_t srcx_adj = info->src.box.width < 0 ? -1 : 0;
1398 const int32_t srcy_adj = info->src.box.height < 0 ? -1 : 0;
1399 const int dz = info->dst.box.z;
1400 const int sz = info->src.box.z;
1401 uint32_t dstw, dsth;
1402 int32_t dstx, dsty;
1403 int64_t srcx, srcy;
1404 int64_t du_dx, dv_dy;
1405 int i;
1406 uint32_t mode;
1407 uint32_t mask = nv50_blit_eng2d_get_mask(info);
1408 bool b;
1409
1410 mode = nv50_blit_get_filter(info) ?
1411 NV50_2D_BLIT_CONTROL_FILTER_BILINEAR :
1412 NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE;
1413 mode |= (src->base.base.nr_samples > dst->base.base.nr_samples) ?
1414 NV50_2D_BLIT_CONTROL_ORIGIN_CORNER : NV50_2D_BLIT_CONTROL_ORIGIN_CENTER;
1415
1416 du_dx = ((int64_t)info->src.box.width << 32) / info->dst.box.width;
1417 dv_dy = ((int64_t)info->src.box.height << 32) / info->dst.box.height;
1418
1419 b = info->dst.format == info->src.format;
1420 nvc0_2d_texture_set(push, 1, dst, info->dst.level, dz, info->dst.format, b);
1421 nvc0_2d_texture_set(push, 0, src, info->src.level, sz, info->src.format, b);
1422
1423 if (info->scissor_enable) {
1424 BEGIN_NVC0(push, NVC0_2D(CLIP_X), 5);
1425 PUSH_DATA (push, info->scissor.minx << dst->ms_x);
1426 PUSH_DATA (push, info->scissor.miny << dst->ms_y);
1427 PUSH_DATA (push, (info->scissor.maxx - info->scissor.minx) << dst->ms_x);
1428 PUSH_DATA (push, (info->scissor.maxy - info->scissor.miny) << dst->ms_y);
1429 PUSH_DATA (push, 1); /* enable */
1430 }
1431
1432 if (nvc0->cond_query && info->render_condition_enable)
1433 IMMED_NVC0(push, NVC0_2D(COND_MODE), nvc0->cond_condmode);
1434
1435 if (mask != 0xffffffff) {
1436 IMMED_NVC0(push, NVC0_2D(ROP), 0xca); /* DPSDxax */
1437 IMMED_NVC0(push, NVC0_2D(PATTERN_COLOR_FORMAT),
1438 NV50_2D_PATTERN_COLOR_FORMAT_A8R8G8B8);
1439 BEGIN_NVC0(push, NVC0_2D(PATTERN_BITMAP_COLOR(0)), 4);
1440 PUSH_DATA (push, 0x00000000);
1441 PUSH_DATA (push, mask);
1442 PUSH_DATA (push, 0xffffffff);
1443 PUSH_DATA (push, 0xffffffff);
1444 IMMED_NVC0(push, NVC0_2D(OPERATION), NV50_2D_OPERATION_ROP);
1445 } else
1446 if (info->src.format != info->dst.format) {
1447 if (info->src.format == PIPE_FORMAT_R8_UNORM ||
1448 info->src.format == PIPE_FORMAT_R8_SNORM ||
1449 info->src.format == PIPE_FORMAT_R16_UNORM ||
1450 info->src.format == PIPE_FORMAT_R16_SNORM ||
1451 info->src.format == PIPE_FORMAT_R16_FLOAT ||
1452 info->src.format == PIPE_FORMAT_R32_FLOAT) {
1453 mask = 0xffff0000; /* also makes condition for OPERATION reset true */
1454 BEGIN_NVC0(push, NVC0_2D(BETA4), 2);
1455 PUSH_DATA (push, mask);
1456 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY_PREMULT);
1457 } else
1458 if (info->src.format == PIPE_FORMAT_A8_UNORM) {
1459 mask = 0xff000000;
1460 BEGIN_NVC0(push, NVC0_2D(BETA4), 2);
1461 PUSH_DATA (push, mask);
1462 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY_PREMULT);
1463 }
1464 }
1465
1466 if (src->ms_x > dst->ms_x || src->ms_y > dst->ms_y) {
1467 /* ms_x is always >= ms_y */
1468 du_dx <<= src->ms_x - dst->ms_x;
1469 dv_dy <<= src->ms_y - dst->ms_y;
1470 } else {
1471 du_dx >>= dst->ms_x - src->ms_x;
1472 dv_dy >>= dst->ms_y - src->ms_y;
1473 }
1474
1475 srcx = (int64_t)(info->src.box.x + srcx_adj) << (src->ms_x + 32);
1476 srcy = (int64_t)(info->src.box.y + srcy_adj) << (src->ms_y + 32);
1477
1478 if (src->base.base.nr_samples > dst->base.base.nr_samples) {
1479 /* center src coorinates for proper MS resolve filtering */
1480 srcx += (int64_t)1 << (src->ms_x + 31);
1481 srcy += (int64_t)1 << (src->ms_y + 31);
1482 }
1483
1484 dstx = info->dst.box.x << dst->ms_x;
1485 dsty = info->dst.box.y << dst->ms_y;
1486
1487 dstw = info->dst.box.width << dst->ms_x;
1488 dsth = info->dst.box.height << dst->ms_y;
1489
1490 if (dstx < 0) {
1491 dstw += dstx;
1492 srcx -= du_dx * dstx;
1493 dstx = 0;
1494 }
1495 if (dsty < 0) {
1496 dsth += dsty;
1497 srcy -= dv_dy * dsty;
1498 dsty = 0;
1499 }
1500
1501 IMMED_NVC0(push, NVC0_2D(BLIT_CONTROL), mode);
1502 BEGIN_NVC0(push, NVC0_2D(BLIT_DST_X), 4);
1503 PUSH_DATA (push, dstx);
1504 PUSH_DATA (push, dsty);
1505 PUSH_DATA (push, dstw);
1506 PUSH_DATA (push, dsth);
1507 BEGIN_NVC0(push, NVC0_2D(BLIT_DU_DX_FRACT), 4);
1508 PUSH_DATA (push, du_dx);
1509 PUSH_DATA (push, du_dx >> 32);
1510 PUSH_DATA (push, dv_dy);
1511 PUSH_DATA (push, dv_dy >> 32);
1512
1513 BCTX_REFN(nvc0->bufctx, 2D, &dst->base, WR);
1514 BCTX_REFN(nvc0->bufctx, 2D, &src->base, RD);
1515 nouveau_pushbuf_bufctx(nvc0->base.pushbuf, nvc0->bufctx);
1516 if (nouveau_pushbuf_validate(nvc0->base.pushbuf))
1517 return;
1518
1519 for (i = 0; i < info->dst.box.depth; ++i) {
1520 if (i > 0) {
1521 /* no scaling in z-direction possible for eng2d blits */
1522 if (dst->layout_3d) {
1523 BEGIN_NVC0(push, NVC0_2D(DST_LAYER), 1);
1524 PUSH_DATA (push, info->dst.box.z + i);
1525 } else {
1526 const unsigned z = info->dst.box.z + i;
1527 const uint64_t address = dst->base.address +
1528 dst->level[info->dst.level].offset +
1529 z * dst->layer_stride;
1530 BEGIN_NVC0(push, NVC0_2D(DST_ADDRESS_HIGH), 2);
1531 PUSH_DATAh(push, address);
1532 PUSH_DATA (push, address);
1533 }
1534 if (src->layout_3d) {
1535 /* not possible because of depth tiling */
1536 assert(0);
1537 } else {
1538 const unsigned z = info->src.box.z + i;
1539 const uint64_t address = src->base.address +
1540 src->level[info->src.level].offset +
1541 z * src->layer_stride;
1542 BEGIN_NVC0(push, NVC0_2D(SRC_ADDRESS_HIGH), 2);
1543 PUSH_DATAh(push, address);
1544 PUSH_DATA (push, address);
1545 }
1546 BEGIN_NVC0(push, NVC0_2D(BLIT_SRC_Y_INT), 1); /* trigger */
1547 PUSH_DATA (push, srcy >> 32);
1548 } else {
1549 BEGIN_NVC0(push, NVC0_2D(BLIT_SRC_X_FRACT), 4);
1550 PUSH_DATA (push, srcx);
1551 PUSH_DATA (push, srcx >> 32);
1552 PUSH_DATA (push, srcy);
1553 PUSH_DATA (push, srcy >> 32);
1554 }
1555 }
1556 nvc0_resource_validate(&dst->base, NOUVEAU_BO_WR);
1557 nvc0_resource_validate(&src->base, NOUVEAU_BO_RD);
1558
1559 nouveau_bufctx_reset(nvc0->bufctx, NVC0_BIND_2D);
1560
1561 if (info->scissor_enable)
1562 IMMED_NVC0(push, NVC0_2D(CLIP_ENABLE), 0);
1563 if (mask != 0xffffffff)
1564 IMMED_NVC0(push, NVC0_2D(OPERATION), NV50_2D_OPERATION_SRCCOPY);
1565 if (nvc0->cond_query && info->render_condition_enable)
1566 IMMED_NVC0(push, NVC0_2D(COND_MODE), NV50_2D_COND_MODE_ALWAYS);
1567 }
1568
1569 static void
1570 nvc0_blit(struct pipe_context *pipe, const struct pipe_blit_info *info)
1571 {
1572 struct nvc0_context *nvc0 = nvc0_context(pipe);
1573 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
1574 bool eng3d = false;
1575
1576 if (info->src.box.width == 0 || info->src.box.height == 0 ||
1577 info->dst.box.width == 0 || info->dst.box.height == 0) {
1578 pipe_debug_message(&nvc0->base.debug, ERROR,
1579 "Blit with zero-size src or dst box");
1580 return;
1581 }
1582
1583 if (util_format_is_depth_or_stencil(info->dst.resource->format)) {
1584 if (!(info->mask & PIPE_MASK_ZS))
1585 return;
1586 if (info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT ||
1587 info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
1588 eng3d = true;
1589 if (info->filter != PIPE_TEX_FILTER_NEAREST)
1590 eng3d = true;
1591 } else {
1592 if (!(info->mask & PIPE_MASK_RGBA))
1593 return;
1594 if (info->mask != PIPE_MASK_RGBA)
1595 eng3d = true;
1596 }
1597
1598 if (nv50_miptree(info->src.resource)->layout_3d) {
1599 eng3d = true;
1600 } else
1601 if (info->src.box.depth != info->dst.box.depth) {
1602 eng3d = true;
1603 debug_printf("blit: cannot filter array or cube textures in z direction");
1604 }
1605
1606 if (!eng3d && info->dst.format != info->src.format) {
1607 if (!nv50_2d_dst_format_faithful(info->dst.format)) {
1608 eng3d = true;
1609 } else
1610 if (!nv50_2d_src_format_faithful(info->src.format)) {
1611 if (!util_format_is_luminance(info->src.format)) {
1612 if (!nv50_2d_dst_format_ops_supported(info->dst.format))
1613 eng3d = true;
1614 else
1615 if (util_format_is_intensity(info->src.format))
1616 eng3d = info->src.format != PIPE_FORMAT_I8_UNORM;
1617 else
1618 if (util_format_is_alpha(info->src.format))
1619 eng3d = info->src.format != PIPE_FORMAT_A8_UNORM;
1620 else
1621 if (util_format_is_srgb(info->dst.format) &&
1622 util_format_get_nr_components(info->src.format) == 1)
1623 eng3d = true;
1624 else
1625 eng3d = !nv50_2d_format_supported(info->src.format);
1626 }
1627 } else
1628 if (util_format_is_luminance_alpha(info->src.format))
1629 eng3d = true;
1630 }
1631
1632 if (info->src.resource->nr_samples == 8 &&
1633 info->dst.resource->nr_samples <= 1)
1634 eng3d = true;
1635 #if 0
1636 /* FIXME: can't make this work with eng2d anymore, at least not on nv50 */
1637 if (info->src.resource->nr_samples > 1 ||
1638 info->dst.resource->nr_samples > 1)
1639 eng3d = true;
1640 #endif
1641 /* FIXME: find correct src coordinates adjustments */
1642 if ((info->src.box.width != info->dst.box.width &&
1643 info->src.box.width != -info->dst.box.width) ||
1644 (info->src.box.height != info->dst.box.height &&
1645 info->src.box.height != -info->dst.box.height))
1646 eng3d = true;
1647
1648 if (info->num_window_rectangles > 0 || info->window_rectangle_include)
1649 eng3d = true;
1650
1651 if (nvc0->screen->num_occlusion_queries_active)
1652 IMMED_NVC0(push, NVC0_3D(SAMPLECNT_ENABLE), 0);
1653
1654 if (!eng3d)
1655 nvc0_blit_eng2d(nvc0, info);
1656 else
1657 nvc0_blit_3d(nvc0, info);
1658
1659 if (nvc0->screen->num_occlusion_queries_active)
1660 IMMED_NVC0(push, NVC0_3D(SAMPLECNT_ENABLE), 1);
1661
1662 NOUVEAU_DRV_STAT(&nvc0->screen->base, tex_blit_count, 1);
1663 }
1664
1665 static void
1666 nvc0_flush_resource(struct pipe_context *ctx,
1667 struct pipe_resource *resource)
1668 {
1669 }
1670
1671 bool
1672 nvc0_blitter_create(struct nvc0_screen *screen)
1673 {
1674 screen->blitter = CALLOC_STRUCT(nvc0_blitter);
1675 if (!screen->blitter) {
1676 NOUVEAU_ERR("failed to allocate blitter struct\n");
1677 return false;
1678 }
1679 screen->blitter->screen = screen;
1680
1681 (void) mtx_init(&screen->blitter->mutex, mtx_plain);
1682
1683 nvc0_blitter_make_sampler(screen->blitter);
1684
1685 return true;
1686 }
1687
1688 void
1689 nvc0_blitter_destroy(struct nvc0_screen *screen)
1690 {
1691 struct nvc0_blitter *blitter = screen->blitter;
1692 unsigned i, m;
1693
1694 for (i = 0; i < NV50_BLIT_MAX_TEXTURE_TYPES; ++i) {
1695 for (m = 0; m < NV50_BLIT_MODES; ++m) {
1696 struct nvc0_program *prog = blitter->fp[i][m];
1697 if (prog) {
1698 nvc0_program_destroy(NULL, prog);
1699 FREE((void *)prog->pipe.tokens);
1700 FREE(prog);
1701 }
1702 }
1703 }
1704
1705 mtx_destroy(&blitter->mutex);
1706 FREE(blitter);
1707 }
1708
1709 bool
1710 nvc0_blitctx_create(struct nvc0_context *nvc0)
1711 {
1712 nvc0->blit = CALLOC_STRUCT(nvc0_blitctx);
1713 if (!nvc0->blit) {
1714 NOUVEAU_ERR("failed to allocate blit context\n");
1715 return false;
1716 }
1717
1718 nvc0->blit->nvc0 = nvc0;
1719
1720 nvc0->blit->rast.pipe.half_pixel_center = 1;
1721
1722 return true;
1723 }
1724
1725 void
1726 nvc0_blitctx_destroy(struct nvc0_context *nvc0)
1727 {
1728 FREE(nvc0->blit);
1729 }
1730
1731 void
1732 nvc0_init_surface_functions(struct nvc0_context *nvc0)
1733 {
1734 struct pipe_context *pipe = &nvc0->base.pipe;
1735
1736 pipe->resource_copy_region = nvc0_resource_copy_region;
1737 pipe->blit = nvc0_blit;
1738 pipe->flush_resource = nvc0_flush_resource;
1739 pipe->clear_render_target = nvc0_clear_render_target;
1740 pipe->clear_depth_stencil = nvc0_clear_depth_stencil;
1741 pipe->clear_texture = nv50_clear_texture;
1742 pipe->clear_buffer = nvc0_clear_buffer;
1743 if (nvc0->screen->base.class_3d >= GM200_3D_CLASS)
1744 pipe->evaluate_depth_buffer = gm200_evaluate_depth_buffer;
1745 }