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cdb1fc1145ff5c0de398c4a53924fefb86699215
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_surface.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <stdint.h>
24
25 #include "pipe/p_defines.h"
26
27 #include "util/u_inlines.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_format.h"
30 #include "util/u_surface.h"
31
32 #include "os/os_thread.h"
33
34 #include "nvc0/nvc0_context.h"
35 #include "nvc0/nvc0_resource.h"
36
37 #include "nv50/nv50_defs.xml.h"
38 #include "nv50/nv50_texture.xml.h"
39
40 /* these are used in nv50_blit.h */
41 #define NV50_ENG2D_SUPPORTED_FORMATS 0xff9ccfe1cce3ccc9ULL
42 #define NV50_ENG2D_NOCONVERT_FORMATS 0x009cc02000000000ULL
43 #define NV50_ENG2D_LUMINANCE_FORMATS 0x001cc02000000000ULL
44 #define NV50_ENG2D_INTENSITY_FORMATS 0x0080000000000000ULL
45 #define NV50_ENG2D_OPERATION_FORMATS 0x060001c000638000ULL
46
47 #define NOUVEAU_DRIVER 0xc0
48 #include "nv50/nv50_blit.h"
49
50 static inline uint8_t
51 nvc0_2d_format(enum pipe_format format, bool dst, bool dst_src_equal)
52 {
53 uint8_t id = nvc0_format_table[format].rt;
54
55 /* A8_UNORM is treated as I8_UNORM as far as the 2D engine is concerned. */
56 if (!dst && unlikely(format == PIPE_FORMAT_I8_UNORM) && !dst_src_equal)
57 return NV50_SURFACE_FORMAT_A8_UNORM;
58
59 /* Hardware values for color formats range from 0xc0 to 0xff,
60 * but the 2D engine doesn't support all of them.
61 */
62 if (nv50_2d_format_supported(format))
63 return id;
64 assert(dst_src_equal);
65
66 switch (util_format_get_blocksize(format)) {
67 case 1:
68 return NV50_SURFACE_FORMAT_R8_UNORM;
69 case 2:
70 return NV50_SURFACE_FORMAT_RG8_UNORM;
71 case 4:
72 return NV50_SURFACE_FORMAT_BGRA8_UNORM;
73 case 8:
74 return NV50_SURFACE_FORMAT_RGBA16_UNORM;
75 case 16:
76 return NV50_SURFACE_FORMAT_RGBA32_FLOAT;
77 default:
78 assert(0);
79 return 0;
80 }
81 }
82
83 static int
84 nvc0_2d_texture_set(struct nouveau_pushbuf *push, bool dst,
85 struct nv50_miptree *mt, unsigned level, unsigned layer,
86 enum pipe_format pformat, bool dst_src_pformat_equal)
87 {
88 struct nouveau_bo *bo = mt->base.bo;
89 uint32_t width, height, depth;
90 uint32_t format;
91 uint32_t mthd = dst ? NV50_2D_DST_FORMAT : NV50_2D_SRC_FORMAT;
92 uint32_t offset = mt->level[level].offset;
93
94 format = nvc0_2d_format(pformat, dst, dst_src_pformat_equal);
95 if (!format) {
96 NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
97 util_format_name(pformat));
98 return 1;
99 }
100
101 width = u_minify(mt->base.base.width0, level) << mt->ms_x;
102 height = u_minify(mt->base.base.height0, level) << mt->ms_y;
103 depth = u_minify(mt->base.base.depth0, level);
104
105 /* layer has to be < depth, and depth > tile depth / 2 */
106
107 if (!mt->layout_3d) {
108 offset += mt->layer_stride * layer;
109 layer = 0;
110 depth = 1;
111 } else
112 if (!dst) {
113 offset += nvc0_mt_zslice_offset(mt, level, layer);
114 layer = 0;
115 }
116
117 if (!nouveau_bo_memtype(bo)) {
118 BEGIN_NVC0(push, SUBC_2D(mthd), 2);
119 PUSH_DATA (push, format);
120 PUSH_DATA (push, 1);
121 BEGIN_NVC0(push, SUBC_2D(mthd + 0x14), 5);
122 PUSH_DATA (push, mt->level[level].pitch);
123 PUSH_DATA (push, width);
124 PUSH_DATA (push, height);
125 PUSH_DATAh(push, bo->offset + offset);
126 PUSH_DATA (push, bo->offset + offset);
127 } else {
128 BEGIN_NVC0(push, SUBC_2D(mthd), 5);
129 PUSH_DATA (push, format);
130 PUSH_DATA (push, 0);
131 PUSH_DATA (push, mt->level[level].tile_mode);
132 PUSH_DATA (push, depth);
133 PUSH_DATA (push, layer);
134 BEGIN_NVC0(push, SUBC_2D(mthd + 0x18), 4);
135 PUSH_DATA (push, width);
136 PUSH_DATA (push, height);
137 PUSH_DATAh(push, bo->offset + offset);
138 PUSH_DATA (push, bo->offset + offset);
139 }
140
141 #if 0
142 if (dst) {
143 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_CLIP_X), 4);
144 PUSH_DATA (push, 0);
145 PUSH_DATA (push, 0);
146 PUSH_DATA (push, width);
147 PUSH_DATA (push, height);
148 }
149 #endif
150 return 0;
151 }
152
153 static int
154 nvc0_2d_texture_do_copy(struct nouveau_pushbuf *push,
155 struct nv50_miptree *dst, unsigned dst_level,
156 unsigned dx, unsigned dy, unsigned dz,
157 struct nv50_miptree *src, unsigned src_level,
158 unsigned sx, unsigned sy, unsigned sz,
159 unsigned w, unsigned h)
160 {
161 const enum pipe_format dfmt = dst->base.base.format;
162 const enum pipe_format sfmt = src->base.base.format;
163 int ret;
164 bool eqfmt = dfmt == sfmt;
165
166 if (!PUSH_SPACE(push, 2 * 16 + 32))
167 return PIPE_ERROR;
168
169 ret = nvc0_2d_texture_set(push, true, dst, dst_level, dz, dfmt, eqfmt);
170 if (ret)
171 return ret;
172
173 ret = nvc0_2d_texture_set(push, false, src, src_level, sz, sfmt, eqfmt);
174 if (ret)
175 return ret;
176
177 IMMED_NVC0(push, NVC0_2D(BLIT_CONTROL), 0x00);
178 BEGIN_NVC0(push, NVC0_2D(BLIT_DST_X), 4);
179 PUSH_DATA (push, dx << dst->ms_x);
180 PUSH_DATA (push, dy << dst->ms_y);
181 PUSH_DATA (push, w << dst->ms_x);
182 PUSH_DATA (push, h << dst->ms_y);
183 BEGIN_NVC0(push, NVC0_2D(BLIT_DU_DX_FRACT), 4);
184 PUSH_DATA (push, 0);
185 PUSH_DATA (push, 1);
186 PUSH_DATA (push, 0);
187 PUSH_DATA (push, 1);
188 BEGIN_NVC0(push, NVC0_2D(BLIT_SRC_X_FRACT), 4);
189 PUSH_DATA (push, 0);
190 PUSH_DATA (push, sx << src->ms_x);
191 PUSH_DATA (push, 0);
192 PUSH_DATA (push, sy << src->ms_y);
193
194 return 0;
195 }
196
197 static void
198 nvc0_resource_copy_region(struct pipe_context *pipe,
199 struct pipe_resource *dst, unsigned dst_level,
200 unsigned dstx, unsigned dsty, unsigned dstz,
201 struct pipe_resource *src, unsigned src_level,
202 const struct pipe_box *src_box)
203 {
204 struct nvc0_context *nvc0 = nvc0_context(pipe);
205 int ret;
206 bool m2mf;
207 unsigned dst_layer = dstz, src_layer = src_box->z;
208
209 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
210 nouveau_copy_buffer(&nvc0->base,
211 nv04_resource(dst), dstx,
212 nv04_resource(src), src_box->x, src_box->width);
213 NOUVEAU_DRV_STAT(&nvc0->screen->base, buf_copy_bytes, src_box->width);
214 return;
215 }
216 NOUVEAU_DRV_STAT(&nvc0->screen->base, tex_copy_count, 1);
217
218 /* 0 and 1 are equal, only supporting 0/1, 2, 4 and 8 */
219 assert((src->nr_samples | 1) == (dst->nr_samples | 1));
220
221 m2mf = (src->format == dst->format) ||
222 (util_format_get_blocksizebits(src->format) ==
223 util_format_get_blocksizebits(dst->format));
224
225 nv04_resource(dst)->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
226
227 if (m2mf) {
228 struct nv50_miptree *src_mt = nv50_miptree(src);
229 struct nv50_miptree *dst_mt = nv50_miptree(dst);
230 struct nv50_m2mf_rect drect, srect;
231 unsigned i;
232 unsigned nx = util_format_get_nblocksx(src->format, src_box->width)
233 << src_mt->ms_x;
234 unsigned ny = util_format_get_nblocksy(src->format, src_box->height)
235 << src_mt->ms_y;
236
237 nv50_m2mf_rect_setup(&drect, dst, dst_level, dstx, dsty, dstz);
238 nv50_m2mf_rect_setup(&srect, src, src_level,
239 src_box->x, src_box->y, src_box->z);
240
241 for (i = 0; i < src_box->depth; ++i) {
242 nvc0->m2mf_copy_rect(nvc0, &drect, &srect, nx, ny);
243
244 if (dst_mt->layout_3d)
245 drect.z++;
246 else
247 drect.base += dst_mt->layer_stride;
248
249 if (src_mt->layout_3d)
250 srect.z++;
251 else
252 srect.base += src_mt->layer_stride;
253 }
254 return;
255 }
256
257 assert(nv50_2d_dst_format_faithful(dst->format));
258 assert(nv50_2d_src_format_faithful(src->format));
259
260 BCTX_REFN(nvc0->bufctx, 2D, nv04_resource(src), RD);
261 BCTX_REFN(nvc0->bufctx, 2D, nv04_resource(dst), WR);
262 nouveau_pushbuf_bufctx(nvc0->base.pushbuf, nvc0->bufctx);
263 nouveau_pushbuf_validate(nvc0->base.pushbuf);
264
265 for (; dst_layer < dstz + src_box->depth; ++dst_layer, ++src_layer) {
266 ret = nvc0_2d_texture_do_copy(nvc0->base.pushbuf,
267 nv50_miptree(dst), dst_level,
268 dstx, dsty, dst_layer,
269 nv50_miptree(src), src_level,
270 src_box->x, src_box->y, src_layer,
271 src_box->width, src_box->height);
272 if (ret)
273 break;
274 }
275 nouveau_bufctx_reset(nvc0->bufctx, 0);
276 }
277
278 static void
279 nvc0_clear_render_target(struct pipe_context *pipe,
280 struct pipe_surface *dst,
281 const union pipe_color_union *color,
282 unsigned dstx, unsigned dsty,
283 unsigned width, unsigned height)
284 {
285 struct nvc0_context *nvc0 = nvc0_context(pipe);
286 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
287 struct nv50_surface *sf = nv50_surface(dst);
288 struct nv04_resource *res = nv04_resource(sf->base.texture);
289 unsigned z;
290
291 if (!PUSH_SPACE(push, 32 + sf->depth))
292 return;
293
294 PUSH_REFN (push, res->bo, res->domain | NOUVEAU_BO_WR);
295
296 BEGIN_NVC0(push, NVC0_3D(CLEAR_COLOR(0)), 4);
297 PUSH_DATAf(push, color->f[0]);
298 PUSH_DATAf(push, color->f[1]);
299 PUSH_DATAf(push, color->f[2]);
300 PUSH_DATAf(push, color->f[3]);
301
302 BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
303 PUSH_DATA (push, ( width << 16) | dstx);
304 PUSH_DATA (push, (height << 16) | dsty);
305
306 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
307 PUSH_DATA (push, 1);
308 BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(0)), 9);
309 PUSH_DATAh(push, res->address + sf->offset);
310 PUSH_DATA (push, res->address + sf->offset);
311 if (likely(nouveau_bo_memtype(res->bo))) {
312 struct nv50_miptree *mt = nv50_miptree(dst->texture);
313
314 PUSH_DATA(push, sf->width);
315 PUSH_DATA(push, sf->height);
316 PUSH_DATA(push, nvc0_format_table[dst->format].rt);
317 PUSH_DATA(push, (mt->layout_3d << 16) |
318 mt->level[sf->base.u.tex.level].tile_mode);
319 PUSH_DATA(push, dst->u.tex.first_layer + sf->depth);
320 PUSH_DATA(push, mt->layer_stride >> 2);
321 PUSH_DATA(push, dst->u.tex.first_layer);
322 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), mt->ms_mode);
323 } else {
324 if (res->base.target == PIPE_BUFFER) {
325 PUSH_DATA(push, 262144);
326 PUSH_DATA(push, 1);
327 } else {
328 PUSH_DATA(push, nv50_miptree(&res->base)->level[0].pitch);
329 PUSH_DATA(push, sf->height);
330 }
331 PUSH_DATA(push, nvc0_format_table[sf->base.format].rt);
332 PUSH_DATA(push, 1 << 12);
333 PUSH_DATA(push, 1);
334 PUSH_DATA(push, 0);
335 PUSH_DATA(push, 0);
336
337 IMMED_NVC0(push, NVC0_3D(ZETA_ENABLE), 0);
338 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 0);
339
340 /* tiled textures don't have to be fenced, they're not mapped directly */
341 nvc0_resource_fence(res, NOUVEAU_BO_WR);
342 }
343
344 BEGIN_NIC0(push, NVC0_3D(CLEAR_BUFFERS), sf->depth);
345 for (z = 0; z < sf->depth; ++z) {
346 PUSH_DATA (push, 0x3c |
347 (z << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
348 }
349
350 nvc0->dirty |= NVC0_NEW_FRAMEBUFFER;
351 }
352
353 static void
354 nvc0_clear_buffer_cpu(struct pipe_context *pipe,
355 struct pipe_resource *res,
356 unsigned offset, unsigned size,
357 const void *data, int data_size)
358 {
359 struct nv04_resource *buf = nv04_resource(res);
360 struct pipe_transfer *pt;
361 struct pipe_box box;
362 unsigned elements, i;
363
364 elements = size / data_size;
365
366 u_box_1d(offset, size, &box);
367
368 uint8_t *map = buf->vtbl->transfer_map(pipe, res, 0, PIPE_TRANSFER_WRITE,
369 &box, &pt);
370
371 for (i = 0; i < elements; ++i)
372 memcpy(&map[i*data_size], data, data_size);
373
374 buf->vtbl->transfer_unmap(pipe, pt);
375 }
376
377 static void
378 nvc0_clear_buffer(struct pipe_context *pipe,
379 struct pipe_resource *res,
380 unsigned offset, unsigned size,
381 const void *data, int data_size)
382 {
383 struct nvc0_context *nvc0 = nvc0_context(pipe);
384 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
385 struct nv04_resource *buf = nv04_resource(res);
386 union pipe_color_union color;
387 enum pipe_format dst_fmt;
388 unsigned width, height, elements;
389
390 assert(res->target == PIPE_BUFFER);
391 assert(nouveau_bo_memtype(buf->bo) == 0);
392
393 switch (data_size) {
394 case 16:
395 dst_fmt = PIPE_FORMAT_R32G32B32A32_UINT;
396 memcpy(&color.ui, data, 16);
397 break;
398 case 12:
399 /* This doesn't work, RGB32 is not a valid RT format.
400 * dst_fmt = PIPE_FORMAT_R32G32B32_UINT;
401 * memcpy(&color.ui, data, 12);
402 * memset(&color.ui[3], 0, 4);
403 */
404 break;
405 case 8:
406 dst_fmt = PIPE_FORMAT_R32G32_UINT;
407 memcpy(&color.ui, data, 8);
408 memset(&color.ui[2], 0, 8);
409 break;
410 case 4:
411 dst_fmt = PIPE_FORMAT_R32_UINT;
412 memcpy(&color.ui, data, 4);
413 memset(&color.ui[1], 0, 12);
414 break;
415 case 2:
416 dst_fmt = PIPE_FORMAT_R16_UINT;
417 color.ui[0] = util_cpu_to_le32(
418 util_le16_to_cpu(*(unsigned short *)data));
419 memset(&color.ui[1], 0, 12);
420 break;
421 case 1:
422 dst_fmt = PIPE_FORMAT_R8_UINT;
423 color.ui[0] = util_cpu_to_le32(*(unsigned char *)data);
424 memset(&color.ui[1], 0, 12);
425 break;
426 default:
427 assert(!"Unsupported element size");
428 return;
429 }
430
431 assert(size % data_size == 0);
432
433 if (data_size == 12) {
434 /* TODO: Find a way to do this with the GPU! */
435 nvc0_clear_buffer_cpu(pipe, res, offset, size, data, data_size);
436 return;
437 }
438
439 elements = size / data_size;
440 height = (elements + 16383) / 16384;
441 width = elements / height;
442
443 if (!PUSH_SPACE(push, 40))
444 return;
445
446 PUSH_REFN (push, buf->bo, buf->domain | NOUVEAU_BO_WR);
447
448 BEGIN_NVC0(push, NVC0_3D(CLEAR_COLOR(0)), 4);
449 PUSH_DATAf(push, color.f[0]);
450 PUSH_DATAf(push, color.f[1]);
451 PUSH_DATAf(push, color.f[2]);
452 PUSH_DATAf(push, color.f[3]);
453 BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
454 PUSH_DATA (push, width << 16);
455 PUSH_DATA (push, height << 16);
456
457 IMMED_NVC0(push, NVC0_3D(RT_CONTROL), 1);
458
459 BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(0)), 9);
460 PUSH_DATAh(push, buf->address + offset);
461 PUSH_DATA (push, buf->address + offset);
462 PUSH_DATA (push, width * data_size);
463 PUSH_DATA (push, height);
464 PUSH_DATA (push, nvc0_format_table[dst_fmt].rt);
465 PUSH_DATA (push, NVC0_3D_RT_TILE_MODE_LINEAR);
466 PUSH_DATA (push, 1);
467 PUSH_DATA (push, 0);
468 PUSH_DATA (push, 0);
469
470 IMMED_NVC0(push, NVC0_3D(ZETA_ENABLE), 0);
471 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 0);
472
473 IMMED_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 0x3c);
474
475 if (width * height != elements) {
476 offset += width * height * data_size;
477 width = elements - width * height;
478 height = 1;
479
480 BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(0)), 4);
481 PUSH_DATAh(push, buf->address + offset);
482 PUSH_DATA (push, buf->address + offset);
483 PUSH_DATA (push, width * data_size);
484 PUSH_DATA (push, height);
485
486 IMMED_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 0x3c);
487 }
488
489 nouveau_fence_ref(nvc0->screen->base.fence.current, &buf->fence);
490 nouveau_fence_ref(nvc0->screen->base.fence.current, &buf->fence_wr);
491 nvc0->dirty |= NVC0_NEW_FRAMEBUFFER;
492 }
493
494 static void
495 nvc0_clear_depth_stencil(struct pipe_context *pipe,
496 struct pipe_surface *dst,
497 unsigned clear_flags,
498 double depth,
499 unsigned stencil,
500 unsigned dstx, unsigned dsty,
501 unsigned width, unsigned height)
502 {
503 struct nvc0_context *nvc0 = nvc0_context(pipe);
504 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
505 struct nv50_miptree *mt = nv50_miptree(dst->texture);
506 struct nv50_surface *sf = nv50_surface(dst);
507 uint32_t mode = 0;
508 int unk = mt->base.base.target == PIPE_TEXTURE_2D;
509 unsigned z;
510
511 if (!PUSH_SPACE(push, 32 + sf->depth))
512 return;
513
514 PUSH_REFN (push, mt->base.bo, mt->base.domain | NOUVEAU_BO_WR);
515
516 if (clear_flags & PIPE_CLEAR_DEPTH) {
517 BEGIN_NVC0(push, NVC0_3D(CLEAR_DEPTH), 1);
518 PUSH_DATAf(push, depth);
519 mode |= NVC0_3D_CLEAR_BUFFERS_Z;
520 }
521
522 if (clear_flags & PIPE_CLEAR_STENCIL) {
523 BEGIN_NVC0(push, NVC0_3D(CLEAR_STENCIL), 1);
524 PUSH_DATA (push, stencil & 0xff);
525 mode |= NVC0_3D_CLEAR_BUFFERS_S;
526 }
527
528 BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
529 PUSH_DATA (push, ( width << 16) | dstx);
530 PUSH_DATA (push, (height << 16) | dsty);
531
532 BEGIN_NVC0(push, NVC0_3D(ZETA_ADDRESS_HIGH), 5);
533 PUSH_DATAh(push, mt->base.address + sf->offset);
534 PUSH_DATA (push, mt->base.address + sf->offset);
535 PUSH_DATA (push, nvc0_format_table[dst->format].rt);
536 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
537 PUSH_DATA (push, mt->layer_stride >> 2);
538 BEGIN_NVC0(push, NVC0_3D(ZETA_ENABLE), 1);
539 PUSH_DATA (push, 1);
540 BEGIN_NVC0(push, NVC0_3D(ZETA_HORIZ), 3);
541 PUSH_DATA (push, sf->width);
542 PUSH_DATA (push, sf->height);
543 PUSH_DATA (push, (unk << 16) | (dst->u.tex.first_layer + sf->depth));
544 BEGIN_NVC0(push, NVC0_3D(ZETA_BASE_LAYER), 1);
545 PUSH_DATA (push, dst->u.tex.first_layer);
546 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), mt->ms_mode);
547
548 BEGIN_NIC0(push, NVC0_3D(CLEAR_BUFFERS), sf->depth);
549 for (z = 0; z < sf->depth; ++z) {
550 PUSH_DATA (push, mode |
551 (z << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
552 }
553
554 nvc0->dirty |= NVC0_NEW_FRAMEBUFFER;
555 }
556
557 void
558 nvc0_clear(struct pipe_context *pipe, unsigned buffers,
559 const union pipe_color_union *color,
560 double depth, unsigned stencil)
561 {
562 struct nvc0_context *nvc0 = nvc0_context(pipe);
563 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
564 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
565 unsigned i, j, k;
566 uint32_t mode = 0;
567
568 /* don't need NEW_BLEND, COLOR_MASK doesn't affect CLEAR_BUFFERS */
569 if (!nvc0_state_validate(nvc0, NVC0_NEW_FRAMEBUFFER, 9 + (fb->nr_cbufs * 2)))
570 return;
571
572 if (buffers & PIPE_CLEAR_COLOR && fb->nr_cbufs) {
573 BEGIN_NVC0(push, NVC0_3D(CLEAR_COLOR(0)), 4);
574 PUSH_DATAf(push, color->f[0]);
575 PUSH_DATAf(push, color->f[1]);
576 PUSH_DATAf(push, color->f[2]);
577 PUSH_DATAf(push, color->f[3]);
578 if (buffers & PIPE_CLEAR_COLOR0)
579 mode =
580 NVC0_3D_CLEAR_BUFFERS_R | NVC0_3D_CLEAR_BUFFERS_G |
581 NVC0_3D_CLEAR_BUFFERS_B | NVC0_3D_CLEAR_BUFFERS_A;
582 }
583
584 if (buffers & PIPE_CLEAR_DEPTH) {
585 BEGIN_NVC0(push, NVC0_3D(CLEAR_DEPTH), 1);
586 PUSH_DATA (push, fui(depth));
587 mode |= NVC0_3D_CLEAR_BUFFERS_Z;
588 }
589
590 if (buffers & PIPE_CLEAR_STENCIL) {
591 BEGIN_NVC0(push, NVC0_3D(CLEAR_STENCIL), 1);
592 PUSH_DATA (push, stencil & 0xff);
593 mode |= NVC0_3D_CLEAR_BUFFERS_S;
594 }
595
596 if (mode) {
597 int zs_layers = 0, color0_layers = 0;
598 if (fb->cbufs[0] && (mode & 0x3c))
599 color0_layers = fb->cbufs[0]->u.tex.last_layer -
600 fb->cbufs[0]->u.tex.first_layer + 1;
601 if (fb->zsbuf && (mode & ~0x3c))
602 zs_layers = fb->zsbuf->u.tex.last_layer -
603 fb->zsbuf->u.tex.first_layer + 1;
604
605 for (j = 0; j < MIN2(zs_layers, color0_layers); j++) {
606 BEGIN_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 1);
607 PUSH_DATA(push, mode | (j << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
608 }
609 for (k = j; k < zs_layers; k++) {
610 BEGIN_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 1);
611 PUSH_DATA(push, (mode & ~0x3c) | (k << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
612 }
613 for (k = j; k < color0_layers; k++) {
614 BEGIN_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 1);
615 PUSH_DATA(push, (mode & 0x3c) | (k << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
616 }
617 }
618
619 for (i = 1; i < fb->nr_cbufs; i++) {
620 struct pipe_surface *sf = fb->cbufs[i];
621 if (!sf || !(buffers & (PIPE_CLEAR_COLOR0 << i)))
622 continue;
623 for (j = 0; j <= sf->u.tex.last_layer - sf->u.tex.first_layer; j++) {
624 BEGIN_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 1);
625 PUSH_DATA (push, (i << 6) | 0x3c |
626 (j << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
627 }
628 }
629 }
630
631
632 /* =============================== BLIT CODE ===================================
633 */
634
635 struct nvc0_blitter
636 {
637 struct nvc0_program *fp[NV50_BLIT_MAX_TEXTURE_TYPES][NV50_BLIT_MODES];
638 struct nvc0_program vp;
639
640 struct nv50_tsc_entry sampler[2]; /* nearest, bilinear */
641
642 pipe_mutex mutex;
643
644 struct nvc0_screen *screen;
645 };
646
647 struct nvc0_blitctx
648 {
649 struct nvc0_context *nvc0;
650 struct nvc0_program *fp;
651 uint8_t mode;
652 uint16_t color_mask;
653 uint8_t filter;
654 uint8_t render_condition_enable;
655 enum pipe_texture_target target;
656 struct {
657 struct pipe_framebuffer_state fb;
658 struct nvc0_rasterizer_stateobj *rast;
659 struct nvc0_program *vp;
660 struct nvc0_program *tcp;
661 struct nvc0_program *tep;
662 struct nvc0_program *gp;
663 struct nvc0_program *fp;
664 unsigned num_textures[5];
665 unsigned num_samplers[5];
666 struct pipe_sampler_view *texture[2];
667 struct nv50_tsc_entry *sampler[2];
668 unsigned min_samples;
669 uint32_t dirty;
670 } saved;
671 struct nvc0_rasterizer_stateobj rast;
672 };
673
674 static void
675 nvc0_blitter_make_vp(struct nvc0_blitter *blit)
676 {
677 static const uint32_t code_nvc0[] =
678 {
679 0xfff11c26, 0x06000080, /* vfetch b64 $r4:$r5 a[0x80] */
680 0xfff01c46, 0x06000090, /* vfetch b96 $r0:$r1:$r2 a[0x90] */
681 0x13f01c26, 0x0a7e0070, /* export b64 o[0x70] $r4:$r5 */
682 0x03f01c46, 0x0a7e0080, /* export b96 o[0x80] $r0:$r1:$r2 */
683 0x00001de7, 0x80000000, /* exit */
684 };
685 static const uint32_t code_nve4[] =
686 {
687 0x00000007, 0x20000000, /* sched */
688 0xfff11c26, 0x06000080, /* vfetch b64 $r4:$r5 a[0x80] */
689 0xfff01c46, 0x06000090, /* vfetch b96 $r0:$r1:$r2 a[0x90] */
690 0x13f01c26, 0x0a7e0070, /* export b64 o[0x70] $r4:$r5 */
691 0x03f01c46, 0x0a7e0080, /* export b96 o[0x80] $r0:$r1:$r2 */
692 0x00001de7, 0x80000000, /* exit */
693 };
694 static const uint32_t code_gk110[] =
695 {
696 0x00000000, 0x08000000, /* sched */
697 0x401ffc12, 0x7ec7fc00, /* ld b64 $r4d a[0x80] 0x0 0x0 */
698 0x481ffc02, 0x7ecbfc00, /* ld b96 $r0t a[0x90] 0x0 0x0 */
699 0x381ffc12, 0x7f07fc00, /* st b64 a[0x70] $r4d 0x0 0x0 */
700 0x401ffc02, 0x7f0bfc00, /* st b96 a[0x80] $r0t 0x0 0x0 */
701 0x001c003c, 0x18000000, /* exit */
702 };
703 static const uint32_t code_gm107[] =
704 {
705 0xfc0007e0, 0x001f8000, /* sched 0x7e0 0x7e0 0x7e0 */
706 0x0807ff04, 0xefd8ff80, /* ld b64 $r4 a[0x80] 0x0 */
707 0x0907ff00, 0xefd97f80, /* ld b96 $r0 a[0x90] 0x0 */
708 0x0707ff04, 0xeff0ff80, /* st b64 a[0x70] $r4 0x0 */
709 0xfc0007e0, 0x00000000, /* sched 0x7e0 0x7e0 0x0 */
710 0x0807ff00, 0xeff17f80, /* st b96 a[0x80] $r0 0x0 */
711 0x0007000f, 0xe3000000, /* exit */
712 };
713
714 blit->vp.type = PIPE_SHADER_VERTEX;
715 blit->vp.translated = true;
716 if (blit->screen->base.class_3d >= GM107_3D_CLASS) {
717 blit->vp.code = (uint32_t *)code_gm107; /* const_cast */
718 blit->vp.code_size = sizeof(code_gm107);
719 } else
720 if (blit->screen->base.class_3d >= NVF0_3D_CLASS) {
721 blit->vp.code = (uint32_t *)code_gk110; /* const_cast */
722 blit->vp.code_size = sizeof(code_gk110);
723 } else
724 if (blit->screen->base.class_3d >= NVE4_3D_CLASS) {
725 blit->vp.code = (uint32_t *)code_nve4; /* const_cast */
726 blit->vp.code_size = sizeof(code_nve4);
727 } else {
728 blit->vp.code = (uint32_t *)code_nvc0; /* const_cast */
729 blit->vp.code_size = sizeof(code_nvc0);
730 }
731 blit->vp.num_gprs = 6;
732 blit->vp.vp.edgeflag = PIPE_MAX_ATTRIBS;
733
734 blit->vp.hdr[0] = 0x00020461; /* vertprog magic */
735 blit->vp.hdr[4] = 0x000ff000; /* no outputs read */
736 blit->vp.hdr[6] = 0x00000073; /* a[0x80].xy, a[0x90].xyz */
737 blit->vp.hdr[13] = 0x00073000; /* o[0x70].xy, o[0x80].xyz */
738 }
739
740 static void
741 nvc0_blitter_make_sampler(struct nvc0_blitter *blit)
742 {
743 /* clamp to edge, min/max lod = 0, nearest filtering */
744
745 blit->sampler[0].id = -1;
746
747 blit->sampler[0].tsc[0] = NV50_TSC_0_SRGB_CONVERSION_ALLOWED |
748 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPS__SHIFT) |
749 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPT__SHIFT) |
750 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPR__SHIFT);
751 blit->sampler[0].tsc[1] =
752 NV50_TSC_1_MAGF_NEAREST | NV50_TSC_1_MINF_NEAREST | NV50_TSC_1_MIPF_NONE;
753
754 /* clamp to edge, min/max lod = 0, bilinear filtering */
755
756 blit->sampler[1].id = -1;
757
758 blit->sampler[1].tsc[0] = blit->sampler[0].tsc[0];
759 blit->sampler[1].tsc[1] =
760 NV50_TSC_1_MAGF_LINEAR | NV50_TSC_1_MINF_LINEAR | NV50_TSC_1_MIPF_NONE;
761 }
762
763 static void
764 nvc0_blit_select_fp(struct nvc0_blitctx *ctx, const struct pipe_blit_info *info)
765 {
766 struct nvc0_blitter *blitter = ctx->nvc0->screen->blitter;
767
768 const enum pipe_texture_target ptarg =
769 nv50_blit_reinterpret_pipe_texture_target(info->src.resource->target);
770
771 const unsigned targ = nv50_blit_texture_type(ptarg);
772 const unsigned mode = ctx->mode;
773
774 if (!blitter->fp[targ][mode]) {
775 pipe_mutex_lock(blitter->mutex);
776 if (!blitter->fp[targ][mode])
777 blitter->fp[targ][mode] =
778 nv50_blitter_make_fp(&ctx->nvc0->base.pipe, mode, ptarg);
779 pipe_mutex_unlock(blitter->mutex);
780 }
781 ctx->fp = blitter->fp[targ][mode];
782 }
783
784 static void
785 nvc0_blit_set_dst(struct nvc0_blitctx *ctx,
786 struct pipe_resource *res, unsigned level, unsigned layer,
787 enum pipe_format format)
788 {
789 struct nvc0_context *nvc0 = ctx->nvc0;
790 struct pipe_context *pipe = &nvc0->base.pipe;
791 struct pipe_surface templ;
792
793 if (util_format_is_depth_or_stencil(format))
794 templ.format = nv50_blit_zeta_to_colour_format(format);
795 else
796 templ.format = format;
797
798 templ.u.tex.level = level;
799 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
800
801 if (layer == -1) {
802 templ.u.tex.first_layer = 0;
803 templ.u.tex.last_layer =
804 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
805 }
806
807 nvc0->framebuffer.cbufs[0] = nvc0_miptree_surface_new(pipe, res, &templ);
808 nvc0->framebuffer.nr_cbufs = 1;
809 nvc0->framebuffer.zsbuf = NULL;
810 nvc0->framebuffer.width = nvc0->framebuffer.cbufs[0]->width;
811 nvc0->framebuffer.height = nvc0->framebuffer.cbufs[0]->height;
812 }
813
814 static void
815 nvc0_blit_set_src(struct nvc0_blitctx *ctx,
816 struct pipe_resource *res, unsigned level, unsigned layer,
817 enum pipe_format format, const uint8_t filter)
818 {
819 struct nvc0_context *nvc0 = ctx->nvc0;
820 struct pipe_context *pipe = &nvc0->base.pipe;
821 struct pipe_sampler_view templ;
822 uint32_t flags;
823 unsigned s;
824 enum pipe_texture_target target;
825
826 target = nv50_blit_reinterpret_pipe_texture_target(res->target);
827
828 templ.format = format;
829 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
830 templ.u.tex.first_level = templ.u.tex.last_level = level;
831 templ.swizzle_r = PIPE_SWIZZLE_RED;
832 templ.swizzle_g = PIPE_SWIZZLE_GREEN;
833 templ.swizzle_b = PIPE_SWIZZLE_BLUE;
834 templ.swizzle_a = PIPE_SWIZZLE_ALPHA;
835
836 if (layer == -1) {
837 templ.u.tex.first_layer = 0;
838 templ.u.tex.last_layer =
839 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
840 }
841
842 flags = res->last_level ? 0 : NV50_TEXVIEW_SCALED_COORDS;
843 flags |= NV50_TEXVIEW_ACCESS_RESOLVE;
844 if (filter && res->nr_samples == 8)
845 flags |= NV50_TEXVIEW_FILTER_MSAA8;
846
847 nvc0->textures[4][0] = nvc0_create_texture_view(
848 pipe, res, &templ, flags, target);
849 nvc0->textures[4][1] = NULL;
850
851 for (s = 0; s <= 3; ++s)
852 nvc0->num_textures[s] = 0;
853 nvc0->num_textures[4] = 1;
854
855 templ.format = nv50_zs_to_s_format(format);
856 if (templ.format != format) {
857 nvc0->textures[4][1] = nvc0_create_texture_view(
858 pipe, res, &templ, flags, target);
859 nvc0->num_textures[4] = 2;
860 }
861 }
862
863 static void
864 nvc0_blitctx_prepare_state(struct nvc0_blitctx *blit)
865 {
866 struct nouveau_pushbuf *push = blit->nvc0->base.pushbuf;
867
868 /* TODO: maybe make this a MACRO (if we need more logic) ? */
869
870 if (blit->nvc0->cond_query && !blit->render_condition_enable)
871 IMMED_NVC0(push, NVC0_3D(COND_MODE), NVC0_3D_COND_MODE_ALWAYS);
872
873 /* blend state */
874 BEGIN_NVC0(push, NVC0_3D(COLOR_MASK(0)), 1);
875 PUSH_DATA (push, blit->color_mask);
876 IMMED_NVC0(push, NVC0_3D(BLEND_ENABLE(0)), 0);
877 IMMED_NVC0(push, NVC0_3D(LOGIC_OP_ENABLE), 0);
878
879 /* rasterizer state */
880 IMMED_NVC0(push, NVC0_3D(FRAG_COLOR_CLAMP_EN), 0);
881 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 0);
882 BEGIN_NVC0(push, NVC0_3D(MSAA_MASK(0)), 4);
883 PUSH_DATA (push, 0xffff);
884 PUSH_DATA (push, 0xffff);
885 PUSH_DATA (push, 0xffff);
886 PUSH_DATA (push, 0xffff);
887 BEGIN_NVC0(push, NVC0_3D(MACRO_POLYGON_MODE_FRONT), 1);
888 PUSH_DATA (push, NVC0_3D_MACRO_POLYGON_MODE_FRONT_FILL);
889 BEGIN_NVC0(push, NVC0_3D(MACRO_POLYGON_MODE_BACK), 1);
890 PUSH_DATA (push, NVC0_3D_MACRO_POLYGON_MODE_BACK_FILL);
891 IMMED_NVC0(push, NVC0_3D(POLYGON_SMOOTH_ENABLE), 0);
892 IMMED_NVC0(push, NVC0_3D(POLYGON_OFFSET_FILL_ENABLE), 0);
893 IMMED_NVC0(push, NVC0_3D(POLYGON_STIPPLE_ENABLE), 0);
894 IMMED_NVC0(push, NVC0_3D(CULL_FACE_ENABLE), 0);
895
896 /* zsa state */
897 IMMED_NVC0(push, NVC0_3D(DEPTH_TEST_ENABLE), 0);
898 IMMED_NVC0(push, NVC0_3D(DEPTH_BOUNDS_EN), 0);
899 IMMED_NVC0(push, NVC0_3D(STENCIL_ENABLE), 0);
900 IMMED_NVC0(push, NVC0_3D(ALPHA_TEST_ENABLE), 0);
901
902 /* disable transform feedback */
903 IMMED_NVC0(push, NVC0_3D(TFB_ENABLE), 0);
904 }
905
906 static void
907 nvc0_blitctx_pre_blit(struct nvc0_blitctx *ctx)
908 {
909 struct nvc0_context *nvc0 = ctx->nvc0;
910 struct nvc0_blitter *blitter = nvc0->screen->blitter;
911 int s;
912
913 ctx->saved.fb.width = nvc0->framebuffer.width;
914 ctx->saved.fb.height = nvc0->framebuffer.height;
915 ctx->saved.fb.nr_cbufs = nvc0->framebuffer.nr_cbufs;
916 ctx->saved.fb.cbufs[0] = nvc0->framebuffer.cbufs[0];
917 ctx->saved.fb.zsbuf = nvc0->framebuffer.zsbuf;
918
919 ctx->saved.rast = nvc0->rast;
920
921 ctx->saved.vp = nvc0->vertprog;
922 ctx->saved.tcp = nvc0->tctlprog;
923 ctx->saved.tep = nvc0->tevlprog;
924 ctx->saved.gp = nvc0->gmtyprog;
925 ctx->saved.fp = nvc0->fragprog;
926
927 ctx->saved.min_samples = nvc0->min_samples;
928
929 nvc0->rast = &ctx->rast;
930
931 nvc0->vertprog = &blitter->vp;
932 nvc0->tctlprog = NULL;
933 nvc0->tevlprog = NULL;
934 nvc0->gmtyprog = NULL;
935 nvc0->fragprog = ctx->fp;
936
937 for (s = 0; s <= 4; ++s) {
938 ctx->saved.num_textures[s] = nvc0->num_textures[s];
939 ctx->saved.num_samplers[s] = nvc0->num_samplers[s];
940 nvc0->textures_dirty[s] = (1 << nvc0->num_textures[s]) - 1;
941 nvc0->samplers_dirty[s] = (1 << nvc0->num_samplers[s]) - 1;
942 }
943 ctx->saved.texture[0] = nvc0->textures[4][0];
944 ctx->saved.texture[1] = nvc0->textures[4][1];
945 ctx->saved.sampler[0] = nvc0->samplers[4][0];
946 ctx->saved.sampler[1] = nvc0->samplers[4][1];
947
948 nvc0->samplers[4][0] = &blitter->sampler[ctx->filter];
949 nvc0->samplers[4][1] = &blitter->sampler[ctx->filter];
950
951 for (s = 0; s <= 3; ++s)
952 nvc0->num_samplers[s] = 0;
953 nvc0->num_samplers[4] = 2;
954
955 nvc0->min_samples = 1;
956
957 ctx->saved.dirty = nvc0->dirty;
958
959 nvc0->textures_dirty[4] |= 3;
960 nvc0->samplers_dirty[4] |= 3;
961
962 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_FB);
963 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(4, 0));
964 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(4, 1));
965
966 nvc0->dirty = NVC0_NEW_FRAMEBUFFER | NVC0_NEW_MIN_SAMPLES |
967 NVC0_NEW_VERTPROG | NVC0_NEW_FRAGPROG |
968 NVC0_NEW_TCTLPROG | NVC0_NEW_TEVLPROG | NVC0_NEW_GMTYPROG |
969 NVC0_NEW_TEXTURES | NVC0_NEW_SAMPLERS;
970 }
971
972 static void
973 nvc0_blitctx_post_blit(struct nvc0_blitctx *blit)
974 {
975 struct nvc0_context *nvc0 = blit->nvc0;
976 int s;
977
978 pipe_surface_reference(&nvc0->framebuffer.cbufs[0], NULL);
979
980 nvc0->framebuffer.width = blit->saved.fb.width;
981 nvc0->framebuffer.height = blit->saved.fb.height;
982 nvc0->framebuffer.nr_cbufs = blit->saved.fb.nr_cbufs;
983 nvc0->framebuffer.cbufs[0] = blit->saved.fb.cbufs[0];
984 nvc0->framebuffer.zsbuf = blit->saved.fb.zsbuf;
985
986 nvc0->rast = blit->saved.rast;
987
988 nvc0->vertprog = blit->saved.vp;
989 nvc0->tctlprog = blit->saved.tcp;
990 nvc0->tevlprog = blit->saved.tep;
991 nvc0->gmtyprog = blit->saved.gp;
992 nvc0->fragprog = blit->saved.fp;
993
994 nvc0->min_samples = blit->saved.min_samples;
995
996 pipe_sampler_view_reference(&nvc0->textures[4][0], NULL);
997 pipe_sampler_view_reference(&nvc0->textures[4][1], NULL);
998
999 for (s = 0; s <= 4; ++s) {
1000 nvc0->num_textures[s] = blit->saved.num_textures[s];
1001 nvc0->num_samplers[s] = blit->saved.num_samplers[s];
1002 nvc0->textures_dirty[s] = (1 << nvc0->num_textures[s]) - 1;
1003 nvc0->samplers_dirty[s] = (1 << nvc0->num_samplers[s]) - 1;
1004 }
1005 nvc0->textures[4][0] = blit->saved.texture[0];
1006 nvc0->textures[4][1] = blit->saved.texture[1];
1007 nvc0->samplers[4][0] = blit->saved.sampler[0];
1008 nvc0->samplers[4][1] = blit->saved.sampler[1];
1009
1010 nvc0->textures_dirty[4] |= 3;
1011 nvc0->samplers_dirty[4] |= 3;
1012
1013 if (nvc0->cond_query && !blit->render_condition_enable)
1014 nvc0->base.pipe.render_condition(&nvc0->base.pipe, nvc0->cond_query,
1015 nvc0->cond_cond, nvc0->cond_mode);
1016
1017 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_FB);
1018 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(4, 0));
1019 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(4, 1));
1020
1021 nvc0->dirty = blit->saved.dirty |
1022 (NVC0_NEW_FRAMEBUFFER | NVC0_NEW_SCISSOR | NVC0_NEW_SAMPLE_MASK |
1023 NVC0_NEW_RASTERIZER | NVC0_NEW_ZSA | NVC0_NEW_BLEND |
1024 NVC0_NEW_VIEWPORT |
1025 NVC0_NEW_TEXTURES | NVC0_NEW_SAMPLERS |
1026 NVC0_NEW_VERTPROG | NVC0_NEW_FRAGPROG |
1027 NVC0_NEW_TCTLPROG | NVC0_NEW_TEVLPROG | NVC0_NEW_GMTYPROG |
1028 NVC0_NEW_TFB_TARGETS | NVC0_NEW_VERTEX | NVC0_NEW_ARRAYS);
1029 nvc0->scissors_dirty |= 1;
1030 nvc0->viewports_dirty |= 1;
1031
1032 nvc0->base.pipe.set_min_samples(&nvc0->base.pipe, blit->saved.min_samples);
1033 }
1034
1035 static void
1036 nvc0_blit_3d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
1037 {
1038 struct nvc0_blitctx *blit = nvc0->blit;
1039 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
1040 struct pipe_resource *src = info->src.resource;
1041 struct pipe_resource *dst = info->dst.resource;
1042 struct nouveau_bo *vtxbuf_bo;
1043 uint32_t stride, length, *vbuf;
1044 uint64_t vtxbuf;
1045 int32_t minx, maxx, miny, maxy;
1046 int32_t i, n;
1047 float x0, x1, y0, y1, z;
1048 float dz;
1049 float x_range, y_range;
1050
1051 blit->mode = nv50_blit_select_mode(info);
1052 blit->color_mask = nv50_blit_derive_color_mask(info);
1053 blit->filter = nv50_blit_get_filter(info);
1054 blit->render_condition_enable = info->render_condition_enable;
1055
1056 nvc0_blit_select_fp(blit, info);
1057 nvc0_blitctx_pre_blit(blit);
1058
1059 nvc0_blit_set_dst(blit, dst, info->dst.level, -1, info->dst.format);
1060 nvc0_blit_set_src(blit, src, info->src.level, -1, info->src.format,
1061 blit->filter);
1062
1063 nvc0_blitctx_prepare_state(blit);
1064
1065 nvc0_state_validate(nvc0, ~0, 48);
1066
1067 x_range = (float)info->src.box.width / (float)info->dst.box.width;
1068 y_range = (float)info->src.box.height / (float)info->dst.box.height;
1069
1070 x0 = (float)info->src.box.x - x_range * (float)info->dst.box.x;
1071 y0 = (float)info->src.box.y - y_range * (float)info->dst.box.y;
1072
1073 x1 = x0 + 16384.0f * x_range;
1074 y1 = y0 + 16384.0f * y_range;
1075
1076 x0 *= (float)(1 << nv50_miptree(src)->ms_x);
1077 x1 *= (float)(1 << nv50_miptree(src)->ms_x);
1078 y0 *= (float)(1 << nv50_miptree(src)->ms_y);
1079 y1 *= (float)(1 << nv50_miptree(src)->ms_y);
1080
1081 dz = (float)info->src.box.depth / (float)info->dst.box.depth;
1082 z = (float)info->src.box.z;
1083 if (nv50_miptree(src)->layout_3d)
1084 z += 0.5f * dz;
1085
1086 if (src->last_level > 0) {
1087 /* If there are mip maps, GPU always assumes normalized coordinates. */
1088 const unsigned l = info->src.level;
1089 const float fh = u_minify(src->width0 << nv50_miptree(src)->ms_x, l);
1090 const float fv = u_minify(src->height0 << nv50_miptree(src)->ms_y, l);
1091 x0 /= fh;
1092 x1 /= fh;
1093 y0 /= fv;
1094 y1 /= fv;
1095 if (nv50_miptree(src)->layout_3d) {
1096 z /= u_minify(src->depth0, l);
1097 dz /= u_minify(src->depth0, l);
1098 }
1099 }
1100
1101 IMMED_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 0);
1102 IMMED_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 0x2 |
1103 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_RANGE_0_1);
1104 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_HORIZ(0)), 2);
1105 PUSH_DATA (push, nvc0->framebuffer.width << 16);
1106 PUSH_DATA (push, nvc0->framebuffer.height << 16);
1107
1108 /* Draw a large triangle in screen coordinates covering the whole
1109 * render target, with scissors defining the destination region.
1110 * The vertex is supplied with non-normalized texture coordinates
1111 * arranged in a way to yield the desired offset and scale.
1112 */
1113
1114 minx = info->dst.box.x;
1115 maxx = info->dst.box.x + info->dst.box.width;
1116 miny = info->dst.box.y;
1117 maxy = info->dst.box.y + info->dst.box.height;
1118 if (info->scissor_enable) {
1119 minx = MAX2(minx, info->scissor.minx);
1120 maxx = MIN2(maxx, info->scissor.maxx);
1121 miny = MAX2(miny, info->scissor.miny);
1122 maxy = MIN2(maxy, info->scissor.maxy);
1123 }
1124 BEGIN_NVC0(push, NVC0_3D(SCISSOR_HORIZ(0)), 2);
1125 PUSH_DATA (push, (maxx << 16) | minx);
1126 PUSH_DATA (push, (maxy << 16) | miny);
1127
1128 stride = (3 + 2) * 4;
1129 length = stride * 3 * info->dst.box.depth;
1130
1131 vbuf = nouveau_scratch_get(&nvc0->base, length, &vtxbuf, &vtxbuf_bo);
1132 if (!vbuf) {
1133 assert(vbuf);
1134 return;
1135 }
1136
1137 BCTX_REFN_bo(nvc0->bufctx_3d, VTX_TMP, NOUVEAU_BO_GART | NOUVEAU_BO_RD, vtxbuf_bo);
1138 nouveau_pushbuf_validate(push);
1139
1140 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(0)), 4);
1141 PUSH_DATA (push, NVC0_3D_VERTEX_ARRAY_FETCH_ENABLE | stride <<
1142 NVC0_3D_VERTEX_ARRAY_FETCH_STRIDE__SHIFT);
1143 PUSH_DATAh(push, vtxbuf);
1144 PUSH_DATA (push, vtxbuf);
1145 PUSH_DATA (push, 0);
1146 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_LIMIT_HIGH(0)), 2);
1147 PUSH_DATAh(push, vtxbuf + length - 1);
1148 PUSH_DATA (push, vtxbuf + length - 1);
1149
1150 n = MAX2(2, nvc0->state.num_vtxelts);
1151
1152 BEGIN_NVC0(push, NVC0_3D(VERTEX_ATTRIB_FORMAT(0)), n);
1153 PUSH_DATA (push, NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT |
1154 NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32_32 | 0x00 <<
1155 NVC0_3D_VERTEX_ATTRIB_FORMAT_OFFSET__SHIFT);
1156 PUSH_DATA (push, NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT |
1157 NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32_32_32 | 0x08 <<
1158 NVC0_3D_VERTEX_ATTRIB_FORMAT_OFFSET__SHIFT);
1159 for (i = 2; i < n; i++) {
1160 PUSH_DATA(push, NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT |
1161 NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32 |
1162 NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST);
1163 }
1164 if (nvc0->state.instance_elts) {
1165 nvc0->state.instance_elts = 0;
1166 BEGIN_NVC0(push, NVC0_3D(MACRO_VERTEX_ARRAY_PER_INSTANCE), 2);
1167 PUSH_DATA (push, n);
1168 PUSH_DATA (push, 0);
1169 }
1170 nvc0->state.num_vtxelts = 2;
1171
1172 for (i = 0; i < info->dst.box.depth; ++i, z += dz) {
1173 if (info->dst.box.z + i) {
1174 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1175 PUSH_DATA (push, info->dst.box.z + i);
1176 }
1177
1178 *(vbuf++) = fui(0.0f);
1179 *(vbuf++) = fui(0.0f);
1180 *(vbuf++) = fui(x0);
1181 *(vbuf++) = fui(y0);
1182 *(vbuf++) = fui(z);
1183
1184 *(vbuf++) = fui(16384 << nv50_miptree(dst)->ms_x);
1185 *(vbuf++) = fui(0.0f);
1186 *(vbuf++) = fui(x1);
1187 *(vbuf++) = fui(y0);
1188 *(vbuf++) = fui(z);
1189
1190 *(vbuf++) = fui(0.0f);
1191 *(vbuf++) = fui(16384 << nv50_miptree(dst)->ms_y);
1192 *(vbuf++) = fui(x0);
1193 *(vbuf++) = fui(y1);
1194 *(vbuf++) = fui(z);
1195
1196 IMMED_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL),
1197 NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES);
1198 BEGIN_NVC0(push, NVC0_3D(VERTEX_BUFFER_FIRST), 2);
1199 PUSH_DATA (push, i * 3);
1200 PUSH_DATA (push, 3);
1201 IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
1202 }
1203 if (info->dst.box.z + info->dst.box.depth - 1)
1204 IMMED_NVC0(push, NVC0_3D(LAYER), 0);
1205
1206 nvc0_blitctx_post_blit(blit);
1207
1208 /* restore viewport transform */
1209 IMMED_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1210 }
1211
1212 static void
1213 nvc0_blit_eng2d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
1214 {
1215 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
1216 struct nv50_miptree *dst = nv50_miptree(info->dst.resource);
1217 struct nv50_miptree *src = nv50_miptree(info->src.resource);
1218 const int32_t srcx_adj = info->src.box.width < 0 ? -1 : 0;
1219 const int32_t srcy_adj = info->src.box.height < 0 ? -1 : 0;
1220 const int dz = info->dst.box.z;
1221 const int sz = info->src.box.z;
1222 uint32_t dstw, dsth;
1223 int32_t dstx, dsty;
1224 int64_t srcx, srcy;
1225 int64_t du_dx, dv_dy;
1226 int i;
1227 uint32_t mode;
1228 uint32_t mask = nv50_blit_eng2d_get_mask(info);
1229 bool b;
1230
1231 mode = nv50_blit_get_filter(info) ?
1232 NV50_2D_BLIT_CONTROL_FILTER_BILINEAR :
1233 NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE;
1234 mode |= (src->base.base.nr_samples > dst->base.base.nr_samples) ?
1235 NV50_2D_BLIT_CONTROL_ORIGIN_CORNER : NV50_2D_BLIT_CONTROL_ORIGIN_CENTER;
1236
1237 du_dx = ((int64_t)info->src.box.width << 32) / info->dst.box.width;
1238 dv_dy = ((int64_t)info->src.box.height << 32) / info->dst.box.height;
1239
1240 b = info->dst.format == info->src.format;
1241 nvc0_2d_texture_set(push, 1, dst, info->dst.level, dz, info->dst.format, b);
1242 nvc0_2d_texture_set(push, 0, src, info->src.level, sz, info->src.format, b);
1243
1244 if (info->scissor_enable) {
1245 BEGIN_NVC0(push, NVC0_2D(CLIP_X), 5);
1246 PUSH_DATA (push, info->scissor.minx << dst->ms_x);
1247 PUSH_DATA (push, info->scissor.miny << dst->ms_y);
1248 PUSH_DATA (push, (info->scissor.maxx - info->scissor.minx) << dst->ms_x);
1249 PUSH_DATA (push, (info->scissor.maxy - info->scissor.miny) << dst->ms_y);
1250 PUSH_DATA (push, 1); /* enable */
1251 }
1252
1253 if (nvc0->cond_query && info->render_condition_enable)
1254 IMMED_NVC0(push, NVC0_2D(COND_MODE), nvc0->cond_condmode);
1255
1256 if (mask != 0xffffffff) {
1257 IMMED_NVC0(push, NVC0_2D(ROP), 0xca); /* DPSDxax */
1258 IMMED_NVC0(push, NVC0_2D(PATTERN_COLOR_FORMAT),
1259 NV50_2D_PATTERN_COLOR_FORMAT_A8R8G8B8);
1260 BEGIN_NVC0(push, NVC0_2D(PATTERN_BITMAP_COLOR(0)), 4);
1261 PUSH_DATA (push, 0x00000000);
1262 PUSH_DATA (push, mask);
1263 PUSH_DATA (push, 0xffffffff);
1264 PUSH_DATA (push, 0xffffffff);
1265 IMMED_NVC0(push, NVC0_2D(OPERATION), NV50_2D_OPERATION_ROP);
1266 } else
1267 if (info->src.format != info->dst.format) {
1268 if (info->src.format == PIPE_FORMAT_R8_UNORM ||
1269 info->src.format == PIPE_FORMAT_R8_SNORM ||
1270 info->src.format == PIPE_FORMAT_R16_UNORM ||
1271 info->src.format == PIPE_FORMAT_R16_SNORM ||
1272 info->src.format == PIPE_FORMAT_R16_FLOAT ||
1273 info->src.format == PIPE_FORMAT_R32_FLOAT) {
1274 mask = 0xffff0000; /* also makes condition for OPERATION reset true */
1275 BEGIN_NVC0(push, NVC0_2D(BETA4), 2);
1276 PUSH_DATA (push, mask);
1277 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY_PREMULT);
1278 } else
1279 if (info->src.format == PIPE_FORMAT_A8_UNORM) {
1280 mask = 0xff000000;
1281 BEGIN_NVC0(push, NVC0_2D(BETA4), 2);
1282 PUSH_DATA (push, mask);
1283 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY_PREMULT);
1284 }
1285 }
1286
1287 if (src->ms_x > dst->ms_x || src->ms_y > dst->ms_y) {
1288 /* ms_x is always >= ms_y */
1289 du_dx <<= src->ms_x - dst->ms_x;
1290 dv_dy <<= src->ms_y - dst->ms_y;
1291 } else {
1292 du_dx >>= dst->ms_x - src->ms_x;
1293 dv_dy >>= dst->ms_y - src->ms_y;
1294 }
1295
1296 srcx = (int64_t)(info->src.box.x + srcx_adj) << (src->ms_x + 32);
1297 srcy = (int64_t)(info->src.box.y + srcy_adj) << (src->ms_y + 32);
1298
1299 if (src->base.base.nr_samples > dst->base.base.nr_samples) {
1300 /* center src coorinates for proper MS resolve filtering */
1301 srcx += (int64_t)1 << (src->ms_x + 31);
1302 srcy += (int64_t)1 << (src->ms_y + 31);
1303 }
1304
1305 dstx = info->dst.box.x << dst->ms_x;
1306 dsty = info->dst.box.y << dst->ms_y;
1307
1308 dstw = info->dst.box.width << dst->ms_x;
1309 dsth = info->dst.box.height << dst->ms_y;
1310
1311 if (dstx < 0) {
1312 dstw += dstx;
1313 srcx -= du_dx * dstx;
1314 dstx = 0;
1315 }
1316 if (dsty < 0) {
1317 dsth += dsty;
1318 srcy -= dv_dy * dsty;
1319 dsty = 0;
1320 }
1321
1322 IMMED_NVC0(push, NVC0_2D(BLIT_CONTROL), mode);
1323 BEGIN_NVC0(push, NVC0_2D(BLIT_DST_X), 4);
1324 PUSH_DATA (push, dstx);
1325 PUSH_DATA (push, dsty);
1326 PUSH_DATA (push, dstw);
1327 PUSH_DATA (push, dsth);
1328 BEGIN_NVC0(push, NVC0_2D(BLIT_DU_DX_FRACT), 4);
1329 PUSH_DATA (push, du_dx);
1330 PUSH_DATA (push, du_dx >> 32);
1331 PUSH_DATA (push, dv_dy);
1332 PUSH_DATA (push, dv_dy >> 32);
1333
1334 BCTX_REFN(nvc0->bufctx, 2D, &dst->base, WR);
1335 BCTX_REFN(nvc0->bufctx, 2D, &src->base, RD);
1336 nouveau_pushbuf_bufctx(nvc0->base.pushbuf, nvc0->bufctx);
1337 if (nouveau_pushbuf_validate(nvc0->base.pushbuf))
1338 return;
1339
1340 for (i = 0; i < info->dst.box.depth; ++i) {
1341 if (i > 0) {
1342 /* no scaling in z-direction possible for eng2d blits */
1343 if (dst->layout_3d) {
1344 BEGIN_NVC0(push, NVC0_2D(DST_LAYER), 1);
1345 PUSH_DATA (push, info->dst.box.z + i);
1346 } else {
1347 const unsigned z = info->dst.box.z + i;
1348 const uint64_t address = dst->base.address +
1349 dst->level[info->dst.level].offset +
1350 z * dst->layer_stride;
1351 BEGIN_NVC0(push, NVC0_2D(DST_ADDRESS_HIGH), 2);
1352 PUSH_DATAh(push, address);
1353 PUSH_DATA (push, address);
1354 }
1355 if (src->layout_3d) {
1356 /* not possible because of depth tiling */
1357 assert(0);
1358 } else {
1359 const unsigned z = info->src.box.z + i;
1360 const uint64_t address = src->base.address +
1361 src->level[info->src.level].offset +
1362 z * src->layer_stride;
1363 BEGIN_NVC0(push, NVC0_2D(SRC_ADDRESS_HIGH), 2);
1364 PUSH_DATAh(push, address);
1365 PUSH_DATA (push, address);
1366 }
1367 BEGIN_NVC0(push, NVC0_2D(BLIT_SRC_Y_INT), 1); /* trigger */
1368 PUSH_DATA (push, srcy >> 32);
1369 } else {
1370 BEGIN_NVC0(push, NVC0_2D(BLIT_SRC_X_FRACT), 4);
1371 PUSH_DATA (push, srcx);
1372 PUSH_DATA (push, srcx >> 32);
1373 PUSH_DATA (push, srcy);
1374 PUSH_DATA (push, srcy >> 32);
1375 }
1376 }
1377 nvc0_resource_validate(&dst->base, NOUVEAU_BO_WR);
1378 nvc0_resource_validate(&src->base, NOUVEAU_BO_RD);
1379
1380 nouveau_bufctx_reset(nvc0->bufctx, NVC0_BIND_2D);
1381
1382 if (info->scissor_enable)
1383 IMMED_NVC0(push, NVC0_2D(CLIP_ENABLE), 0);
1384 if (mask != 0xffffffff)
1385 IMMED_NVC0(push, NVC0_2D(OPERATION), NV50_2D_OPERATION_SRCCOPY);
1386 if (nvc0->cond_query && info->render_condition_enable)
1387 IMMED_NVC0(push, NVC0_2D(COND_MODE), NV50_2D_COND_MODE_ALWAYS);
1388 }
1389
1390 static void
1391 nvc0_blit(struct pipe_context *pipe, const struct pipe_blit_info *info)
1392 {
1393 struct nvc0_context *nvc0 = nvc0_context(pipe);
1394 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
1395 bool eng3d = false;
1396
1397 if (util_format_is_depth_or_stencil(info->dst.resource->format)) {
1398 if (!(info->mask & PIPE_MASK_ZS))
1399 return;
1400 if (info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT ||
1401 info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
1402 eng3d = true;
1403 if (info->filter != PIPE_TEX_FILTER_NEAREST)
1404 eng3d = true;
1405 } else {
1406 if (!(info->mask & PIPE_MASK_RGBA))
1407 return;
1408 if (info->mask != PIPE_MASK_RGBA)
1409 eng3d = true;
1410 }
1411
1412 if (nv50_miptree(info->src.resource)->layout_3d) {
1413 eng3d = true;
1414 } else
1415 if (info->src.box.depth != info->dst.box.depth) {
1416 eng3d = true;
1417 debug_printf("blit: cannot filter array or cube textures in z direction");
1418 }
1419
1420 if (!eng3d && info->dst.format != info->src.format) {
1421 if (!nv50_2d_dst_format_faithful(info->dst.format)) {
1422 eng3d = true;
1423 } else
1424 if (!nv50_2d_src_format_faithful(info->src.format)) {
1425 if (!util_format_is_luminance(info->src.format)) {
1426 if (!nv50_2d_dst_format_ops_supported(info->dst.format))
1427 eng3d = true;
1428 else
1429 if (util_format_is_intensity(info->src.format))
1430 eng3d = info->src.format != PIPE_FORMAT_I8_UNORM;
1431 else
1432 if (util_format_is_alpha(info->src.format))
1433 eng3d = info->src.format != PIPE_FORMAT_A8_UNORM;
1434 else
1435 eng3d = !nv50_2d_format_supported(info->src.format);
1436 }
1437 } else
1438 if (util_format_is_luminance_alpha(info->src.format))
1439 eng3d = true;
1440 }
1441
1442 if (info->src.resource->nr_samples == 8 &&
1443 info->dst.resource->nr_samples <= 1)
1444 eng3d = true;
1445 #if 0
1446 /* FIXME: can't make this work with eng2d anymore, at least not on nv50 */
1447 if (info->src.resource->nr_samples > 1 ||
1448 info->dst.resource->nr_samples > 1)
1449 eng3d = true;
1450 #endif
1451 /* FIXME: find correct src coordinates adjustments */
1452 if ((info->src.box.width != info->dst.box.width &&
1453 info->src.box.width != -info->dst.box.width) ||
1454 (info->src.box.height != info->dst.box.height &&
1455 info->src.box.height != -info->dst.box.height))
1456 eng3d = true;
1457
1458 if (nvc0->screen->num_occlusion_queries_active)
1459 IMMED_NVC0(push, NVC0_3D(SAMPLECNT_ENABLE), 0);
1460
1461 if (!eng3d)
1462 nvc0_blit_eng2d(nvc0, info);
1463 else
1464 nvc0_blit_3d(nvc0, info);
1465
1466 if (nvc0->screen->num_occlusion_queries_active)
1467 IMMED_NVC0(push, NVC0_3D(SAMPLECNT_ENABLE), 1);
1468
1469 NOUVEAU_DRV_STAT(&nvc0->screen->base, tex_blit_count, 1);
1470 }
1471
1472 static void
1473 nvc0_flush_resource(struct pipe_context *ctx,
1474 struct pipe_resource *resource)
1475 {
1476 }
1477
1478 bool
1479 nvc0_blitter_create(struct nvc0_screen *screen)
1480 {
1481 screen->blitter = CALLOC_STRUCT(nvc0_blitter);
1482 if (!screen->blitter) {
1483 NOUVEAU_ERR("failed to allocate blitter struct\n");
1484 return false;
1485 }
1486 screen->blitter->screen = screen;
1487
1488 pipe_mutex_init(screen->blitter->mutex);
1489
1490 nvc0_blitter_make_vp(screen->blitter);
1491 nvc0_blitter_make_sampler(screen->blitter);
1492
1493 return true;
1494 }
1495
1496 void
1497 nvc0_blitter_destroy(struct nvc0_screen *screen)
1498 {
1499 struct nvc0_blitter *blitter = screen->blitter;
1500 unsigned i, m;
1501
1502 for (i = 0; i < NV50_BLIT_MAX_TEXTURE_TYPES; ++i) {
1503 for (m = 0; m < NV50_BLIT_MODES; ++m) {
1504 struct nvc0_program *prog = blitter->fp[i][m];
1505 if (prog) {
1506 nvc0_program_destroy(NULL, prog);
1507 FREE((void *)prog->pipe.tokens);
1508 FREE(prog);
1509 }
1510 }
1511 }
1512
1513 FREE(blitter);
1514 }
1515
1516 bool
1517 nvc0_blitctx_create(struct nvc0_context *nvc0)
1518 {
1519 nvc0->blit = CALLOC_STRUCT(nvc0_blitctx);
1520 if (!nvc0->blit) {
1521 NOUVEAU_ERR("failed to allocate blit context\n");
1522 return false;
1523 }
1524
1525 nvc0->blit->nvc0 = nvc0;
1526
1527 nvc0->blit->rast.pipe.half_pixel_center = 1;
1528
1529 return true;
1530 }
1531
1532 void
1533 nvc0_blitctx_destroy(struct nvc0_context *nvc0)
1534 {
1535 FREE(nvc0->blit);
1536 }
1537
1538 void
1539 nvc0_init_surface_functions(struct nvc0_context *nvc0)
1540 {
1541 struct pipe_context *pipe = &nvc0->base.pipe;
1542
1543 pipe->resource_copy_region = nvc0_resource_copy_region;
1544 pipe->blit = nvc0_blit;
1545 pipe->flush_resource = nvc0_flush_resource;
1546 pipe->clear_render_target = nvc0_clear_render_target;
1547 pipe->clear_depth_stencil = nvc0_clear_depth_stencil;
1548 pipe->clear_texture = nv50_clear_texture;
1549 pipe->clear_buffer = nvc0_clear_buffer;
1550 }