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[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_surface.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <stdint.h>
24
25 #include "pipe/p_defines.h"
26
27 #include "util/u_inlines.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_format.h"
30 #include "util/u_surface.h"
31
32 #include "os/os_thread.h"
33
34 #include "nvc0/nvc0_context.h"
35 #include "nvc0/nvc0_resource.h"
36
37 #include "nv50/nv50_defs.xml.h"
38 #include "nv50/nv50_texture.xml.h"
39
40 /* these are used in nv50_blit.h */
41 #define NV50_ENG2D_SUPPORTED_FORMATS 0xff9ccfe1cce3ccc9ULL
42 #define NV50_ENG2D_NOCONVERT_FORMATS 0x009cc02000000000ULL
43 #define NV50_ENG2D_LUMINANCE_FORMATS 0x001cc02000000000ULL
44 #define NV50_ENG2D_INTENSITY_FORMATS 0x0080000000000000ULL
45 #define NV50_ENG2D_OPERATION_FORMATS 0x060001c000638000ULL
46
47 #define NOUVEAU_DRIVER 0xc0
48 #include "nv50/nv50_blit.h"
49
50 static inline uint8_t
51 nvc0_2d_format(enum pipe_format format, bool dst, bool dst_src_equal)
52 {
53 uint8_t id = nvc0_format_table[format].rt;
54
55 /* A8_UNORM is treated as I8_UNORM as far as the 2D engine is concerned. */
56 if (!dst && unlikely(format == PIPE_FORMAT_I8_UNORM) && !dst_src_equal)
57 return NV50_SURFACE_FORMAT_A8_UNORM;
58
59 /* Hardware values for color formats range from 0xc0 to 0xff,
60 * but the 2D engine doesn't support all of them.
61 */
62 if (nv50_2d_format_supported(format))
63 return id;
64 assert(dst_src_equal);
65
66 switch (util_format_get_blocksize(format)) {
67 case 1:
68 return NV50_SURFACE_FORMAT_R8_UNORM;
69 case 2:
70 return NV50_SURFACE_FORMAT_RG8_UNORM;
71 case 4:
72 return NV50_SURFACE_FORMAT_BGRA8_UNORM;
73 case 8:
74 return NV50_SURFACE_FORMAT_RGBA16_UNORM;
75 case 16:
76 return NV50_SURFACE_FORMAT_RGBA32_FLOAT;
77 default:
78 assert(0);
79 return 0;
80 }
81 }
82
83 static int
84 nvc0_2d_texture_set(struct nouveau_pushbuf *push, bool dst,
85 struct nv50_miptree *mt, unsigned level, unsigned layer,
86 enum pipe_format pformat, bool dst_src_pformat_equal)
87 {
88 struct nouveau_bo *bo = mt->base.bo;
89 uint32_t width, height, depth;
90 uint32_t format;
91 uint32_t mthd = dst ? NV50_2D_DST_FORMAT : NV50_2D_SRC_FORMAT;
92 uint32_t offset = mt->level[level].offset;
93
94 format = nvc0_2d_format(pformat, dst, dst_src_pformat_equal);
95 if (!format) {
96 NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
97 util_format_name(pformat));
98 return 1;
99 }
100
101 width = u_minify(mt->base.base.width0, level) << mt->ms_x;
102 height = u_minify(mt->base.base.height0, level) << mt->ms_y;
103 depth = u_minify(mt->base.base.depth0, level);
104
105 /* layer has to be < depth, and depth > tile depth / 2 */
106
107 if (!mt->layout_3d) {
108 offset += mt->layer_stride * layer;
109 layer = 0;
110 depth = 1;
111 } else
112 if (!dst) {
113 offset += nvc0_mt_zslice_offset(mt, level, layer);
114 layer = 0;
115 }
116
117 if (!nouveau_bo_memtype(bo)) {
118 BEGIN_NVC0(push, SUBC_2D(mthd), 2);
119 PUSH_DATA (push, format);
120 PUSH_DATA (push, 1);
121 BEGIN_NVC0(push, SUBC_2D(mthd + 0x14), 5);
122 PUSH_DATA (push, mt->level[level].pitch);
123 PUSH_DATA (push, width);
124 PUSH_DATA (push, height);
125 PUSH_DATAh(push, bo->offset + offset);
126 PUSH_DATA (push, bo->offset + offset);
127 } else {
128 BEGIN_NVC0(push, SUBC_2D(mthd), 5);
129 PUSH_DATA (push, format);
130 PUSH_DATA (push, 0);
131 PUSH_DATA (push, mt->level[level].tile_mode);
132 PUSH_DATA (push, depth);
133 PUSH_DATA (push, layer);
134 BEGIN_NVC0(push, SUBC_2D(mthd + 0x18), 4);
135 PUSH_DATA (push, width);
136 PUSH_DATA (push, height);
137 PUSH_DATAh(push, bo->offset + offset);
138 PUSH_DATA (push, bo->offset + offset);
139 }
140
141 #if 0
142 if (dst) {
143 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_CLIP_X), 4);
144 PUSH_DATA (push, 0);
145 PUSH_DATA (push, 0);
146 PUSH_DATA (push, width);
147 PUSH_DATA (push, height);
148 }
149 #endif
150 return 0;
151 }
152
153 static int
154 nvc0_2d_texture_do_copy(struct nouveau_pushbuf *push,
155 struct nv50_miptree *dst, unsigned dst_level,
156 unsigned dx, unsigned dy, unsigned dz,
157 struct nv50_miptree *src, unsigned src_level,
158 unsigned sx, unsigned sy, unsigned sz,
159 unsigned w, unsigned h)
160 {
161 const enum pipe_format dfmt = dst->base.base.format;
162 const enum pipe_format sfmt = src->base.base.format;
163 int ret;
164 bool eqfmt = dfmt == sfmt;
165
166 if (!PUSH_SPACE(push, 2 * 16 + 32))
167 return PIPE_ERROR;
168
169 ret = nvc0_2d_texture_set(push, true, dst, dst_level, dz, dfmt, eqfmt);
170 if (ret)
171 return ret;
172
173 ret = nvc0_2d_texture_set(push, false, src, src_level, sz, sfmt, eqfmt);
174 if (ret)
175 return ret;
176
177 IMMED_NVC0(push, NVC0_2D(BLIT_CONTROL), 0x00);
178 BEGIN_NVC0(push, NVC0_2D(BLIT_DST_X), 4);
179 PUSH_DATA (push, dx << dst->ms_x);
180 PUSH_DATA (push, dy << dst->ms_y);
181 PUSH_DATA (push, w << dst->ms_x);
182 PUSH_DATA (push, h << dst->ms_y);
183 BEGIN_NVC0(push, NVC0_2D(BLIT_DU_DX_FRACT), 4);
184 PUSH_DATA (push, 0);
185 PUSH_DATA (push, 1);
186 PUSH_DATA (push, 0);
187 PUSH_DATA (push, 1);
188 BEGIN_NVC0(push, NVC0_2D(BLIT_SRC_X_FRACT), 4);
189 PUSH_DATA (push, 0);
190 PUSH_DATA (push, sx << src->ms_x);
191 PUSH_DATA (push, 0);
192 PUSH_DATA (push, sy << src->ms_y);
193
194 return 0;
195 }
196
197 static void
198 nvc0_resource_copy_region(struct pipe_context *pipe,
199 struct pipe_resource *dst, unsigned dst_level,
200 unsigned dstx, unsigned dsty, unsigned dstz,
201 struct pipe_resource *src, unsigned src_level,
202 const struct pipe_box *src_box)
203 {
204 struct nvc0_context *nvc0 = nvc0_context(pipe);
205 int ret;
206 bool m2mf;
207 unsigned dst_layer = dstz, src_layer = src_box->z;
208
209 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
210 nouveau_copy_buffer(&nvc0->base,
211 nv04_resource(dst), dstx,
212 nv04_resource(src), src_box->x, src_box->width);
213 NOUVEAU_DRV_STAT(&nvc0->screen->base, buf_copy_bytes, src_box->width);
214 return;
215 }
216 NOUVEAU_DRV_STAT(&nvc0->screen->base, tex_copy_count, 1);
217
218 /* 0 and 1 are equal, only supporting 0/1, 2, 4 and 8 */
219 assert((src->nr_samples | 1) == (dst->nr_samples | 1));
220
221 m2mf = (src->format == dst->format) ||
222 (util_format_get_blocksizebits(src->format) ==
223 util_format_get_blocksizebits(dst->format));
224
225 nv04_resource(dst)->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
226
227 if (m2mf) {
228 struct nv50_miptree *src_mt = nv50_miptree(src);
229 struct nv50_miptree *dst_mt = nv50_miptree(dst);
230 struct nv50_m2mf_rect drect, srect;
231 unsigned i;
232 unsigned nx = util_format_get_nblocksx(src->format, src_box->width)
233 << src_mt->ms_x;
234 unsigned ny = util_format_get_nblocksy(src->format, src_box->height)
235 << src_mt->ms_y;
236
237 nv50_m2mf_rect_setup(&drect, dst, dst_level, dstx, dsty, dstz);
238 nv50_m2mf_rect_setup(&srect, src, src_level,
239 src_box->x, src_box->y, src_box->z);
240
241 for (i = 0; i < src_box->depth; ++i) {
242 nvc0->m2mf_copy_rect(nvc0, &drect, &srect, nx, ny);
243
244 if (dst_mt->layout_3d)
245 drect.z++;
246 else
247 drect.base += dst_mt->layer_stride;
248
249 if (src_mt->layout_3d)
250 srect.z++;
251 else
252 srect.base += src_mt->layer_stride;
253 }
254 return;
255 }
256
257 assert(nv50_2d_dst_format_faithful(dst->format));
258 assert(nv50_2d_src_format_faithful(src->format));
259
260 BCTX_REFN(nvc0->bufctx, 2D, nv04_resource(src), RD);
261 BCTX_REFN(nvc0->bufctx, 2D, nv04_resource(dst), WR);
262 nouveau_pushbuf_bufctx(nvc0->base.pushbuf, nvc0->bufctx);
263 nouveau_pushbuf_validate(nvc0->base.pushbuf);
264
265 for (; dst_layer < dstz + src_box->depth; ++dst_layer, ++src_layer) {
266 ret = nvc0_2d_texture_do_copy(nvc0->base.pushbuf,
267 nv50_miptree(dst), dst_level,
268 dstx, dsty, dst_layer,
269 nv50_miptree(src), src_level,
270 src_box->x, src_box->y, src_layer,
271 src_box->width, src_box->height);
272 if (ret)
273 break;
274 }
275 nouveau_bufctx_reset(nvc0->bufctx, 0);
276 }
277
278 static void
279 nvc0_clear_render_target(struct pipe_context *pipe,
280 struct pipe_surface *dst,
281 const union pipe_color_union *color,
282 unsigned dstx, unsigned dsty,
283 unsigned width, unsigned height)
284 {
285 struct nvc0_context *nvc0 = nvc0_context(pipe);
286 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
287 struct nv50_surface *sf = nv50_surface(dst);
288 struct nv04_resource *res = nv04_resource(sf->base.texture);
289 unsigned z;
290
291 assert(dst->texture->target != PIPE_BUFFER);
292
293 if (!PUSH_SPACE(push, 32 + sf->depth))
294 return;
295
296 PUSH_REFN (push, res->bo, res->domain | NOUVEAU_BO_WR);
297
298 BEGIN_NVC0(push, NVC0_3D(CLEAR_COLOR(0)), 4);
299 PUSH_DATAf(push, color->f[0]);
300 PUSH_DATAf(push, color->f[1]);
301 PUSH_DATAf(push, color->f[2]);
302 PUSH_DATAf(push, color->f[3]);
303
304 BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
305 PUSH_DATA (push, ( width << 16) | dstx);
306 PUSH_DATA (push, (height << 16) | dsty);
307
308 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
309 PUSH_DATA (push, 1);
310 BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(0)), 9);
311 PUSH_DATAh(push, res->address + sf->offset);
312 PUSH_DATA (push, res->address + sf->offset);
313 if (likely(nouveau_bo_memtype(res->bo))) {
314 struct nv50_miptree *mt = nv50_miptree(dst->texture);
315
316 PUSH_DATA(push, sf->width);
317 PUSH_DATA(push, sf->height);
318 PUSH_DATA(push, nvc0_format_table[dst->format].rt);
319 PUSH_DATA(push, (mt->layout_3d << 16) |
320 mt->level[sf->base.u.tex.level].tile_mode);
321 PUSH_DATA(push, dst->u.tex.first_layer + sf->depth);
322 PUSH_DATA(push, mt->layer_stride >> 2);
323 PUSH_DATA(push, dst->u.tex.first_layer);
324 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), mt->ms_mode);
325 } else {
326 if (res->base.target == PIPE_BUFFER) {
327 PUSH_DATA(push, 262144);
328 PUSH_DATA(push, 1);
329 } else {
330 PUSH_DATA(push, nv50_miptree(&res->base)->level[0].pitch);
331 PUSH_DATA(push, sf->height);
332 }
333 PUSH_DATA(push, nvc0_format_table[sf->base.format].rt);
334 PUSH_DATA(push, 1 << 12);
335 PUSH_DATA(push, 1);
336 PUSH_DATA(push, 0);
337 PUSH_DATA(push, 0);
338
339 IMMED_NVC0(push, NVC0_3D(ZETA_ENABLE), 0);
340 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 0);
341
342 /* tiled textures don't have to be fenced, they're not mapped directly */
343 nvc0_resource_fence(res, NOUVEAU_BO_WR);
344 }
345
346 IMMED_NVC0(push, NVC0_3D(COND_MODE), NVC0_3D_COND_MODE_ALWAYS);
347
348 BEGIN_NIC0(push, NVC0_3D(CLEAR_BUFFERS), sf->depth);
349 for (z = 0; z < sf->depth; ++z) {
350 PUSH_DATA (push, 0x3c |
351 (z << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
352 }
353
354 IMMED_NVC0(push, NVC0_3D(COND_MODE), nvc0->cond_condmode);
355
356 nvc0->dirty |= NVC0_NEW_FRAMEBUFFER;
357 }
358
359 static void
360 nvc0_clear_buffer_cpu(struct pipe_context *pipe,
361 struct pipe_resource *res,
362 unsigned offset, unsigned size,
363 const void *data, int data_size)
364 {
365 struct nv04_resource *buf = nv04_resource(res);
366 struct pipe_transfer *pt;
367 struct pipe_box box;
368 unsigned elements, i;
369
370 elements = size / data_size;
371
372 u_box_1d(offset, size, &box);
373
374 uint8_t *map = buf->vtbl->transfer_map(pipe, res, 0, PIPE_TRANSFER_WRITE,
375 &box, &pt);
376
377 for (i = 0; i < elements; ++i)
378 memcpy(&map[i*data_size], data, data_size);
379
380 buf->vtbl->transfer_unmap(pipe, pt);
381 }
382
383 static void
384 nvc0_clear_buffer(struct pipe_context *pipe,
385 struct pipe_resource *res,
386 unsigned offset, unsigned size,
387 const void *data, int data_size)
388 {
389 struct nvc0_context *nvc0 = nvc0_context(pipe);
390 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
391 struct nv04_resource *buf = nv04_resource(res);
392 union pipe_color_union color;
393 enum pipe_format dst_fmt;
394 unsigned width, height, elements;
395
396 assert(res->target == PIPE_BUFFER);
397 assert(nouveau_bo_memtype(buf->bo) == 0);
398
399 switch (data_size) {
400 case 16:
401 dst_fmt = PIPE_FORMAT_R32G32B32A32_UINT;
402 memcpy(&color.ui, data, 16);
403 break;
404 case 12:
405 /* This doesn't work, RGB32 is not a valid RT format.
406 * dst_fmt = PIPE_FORMAT_R32G32B32_UINT;
407 * memcpy(&color.ui, data, 12);
408 * memset(&color.ui[3], 0, 4);
409 */
410 break;
411 case 8:
412 dst_fmt = PIPE_FORMAT_R32G32_UINT;
413 memcpy(&color.ui, data, 8);
414 memset(&color.ui[2], 0, 8);
415 break;
416 case 4:
417 dst_fmt = PIPE_FORMAT_R32_UINT;
418 memcpy(&color.ui, data, 4);
419 memset(&color.ui[1], 0, 12);
420 break;
421 case 2:
422 dst_fmt = PIPE_FORMAT_R16_UINT;
423 color.ui[0] = util_cpu_to_le32(
424 util_le16_to_cpu(*(unsigned short *)data));
425 memset(&color.ui[1], 0, 12);
426 break;
427 case 1:
428 dst_fmt = PIPE_FORMAT_R8_UINT;
429 color.ui[0] = util_cpu_to_le32(*(unsigned char *)data);
430 memset(&color.ui[1], 0, 12);
431 break;
432 default:
433 assert(!"Unsupported element size");
434 return;
435 }
436
437 assert(size % data_size == 0);
438
439 if (data_size == 12) {
440 /* TODO: Find a way to do this with the GPU! */
441 nvc0_clear_buffer_cpu(pipe, res, offset, size, data, data_size);
442 return;
443 }
444
445 elements = size / data_size;
446 height = (elements + 16383) / 16384;
447 width = elements / height;
448
449 if (!PUSH_SPACE(push, 40))
450 return;
451
452 PUSH_REFN (push, buf->bo, buf->domain | NOUVEAU_BO_WR);
453
454 BEGIN_NVC0(push, NVC0_3D(CLEAR_COLOR(0)), 4);
455 PUSH_DATAf(push, color.f[0]);
456 PUSH_DATAf(push, color.f[1]);
457 PUSH_DATAf(push, color.f[2]);
458 PUSH_DATAf(push, color.f[3]);
459 BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
460 PUSH_DATA (push, width << 16);
461 PUSH_DATA (push, height << 16);
462
463 IMMED_NVC0(push, NVC0_3D(RT_CONTROL), 1);
464
465 BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(0)), 9);
466 PUSH_DATAh(push, buf->address + offset);
467 PUSH_DATA (push, buf->address + offset);
468 PUSH_DATA (push, width * data_size);
469 PUSH_DATA (push, height);
470 PUSH_DATA (push, nvc0_format_table[dst_fmt].rt);
471 PUSH_DATA (push, NVC0_3D_RT_TILE_MODE_LINEAR);
472 PUSH_DATA (push, 1);
473 PUSH_DATA (push, 0);
474 PUSH_DATA (push, 0);
475
476 IMMED_NVC0(push, NVC0_3D(ZETA_ENABLE), 0);
477 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 0);
478
479 IMMED_NVC0(push, NVC0_3D(COND_MODE), NVC0_3D_COND_MODE_ALWAYS);
480
481 IMMED_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 0x3c);
482
483 if (width * height != elements) {
484 offset += width * height * data_size;
485 width = elements - width * height;
486 height = 1;
487
488 BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(0)), 4);
489 PUSH_DATAh(push, buf->address + offset);
490 PUSH_DATA (push, buf->address + offset);
491 PUSH_DATA (push, width * data_size);
492 PUSH_DATA (push, height);
493
494 IMMED_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 0x3c);
495 }
496
497 IMMED_NVC0(push, NVC0_3D(COND_MODE), nvc0->cond_condmode);
498
499 nouveau_fence_ref(nvc0->screen->base.fence.current, &buf->fence);
500 nouveau_fence_ref(nvc0->screen->base.fence.current, &buf->fence_wr);
501 nvc0->dirty |= NVC0_NEW_FRAMEBUFFER;
502 }
503
504 static void
505 nvc0_clear_depth_stencil(struct pipe_context *pipe,
506 struct pipe_surface *dst,
507 unsigned clear_flags,
508 double depth,
509 unsigned stencil,
510 unsigned dstx, unsigned dsty,
511 unsigned width, unsigned height)
512 {
513 struct nvc0_context *nvc0 = nvc0_context(pipe);
514 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
515 struct nv50_miptree *mt = nv50_miptree(dst->texture);
516 struct nv50_surface *sf = nv50_surface(dst);
517 uint32_t mode = 0;
518 int unk = mt->base.base.target == PIPE_TEXTURE_2D;
519 unsigned z;
520
521 assert(dst->texture->target != PIPE_BUFFER);
522
523 if (!PUSH_SPACE(push, 32 + sf->depth))
524 return;
525
526 PUSH_REFN (push, mt->base.bo, mt->base.domain | NOUVEAU_BO_WR);
527
528 if (clear_flags & PIPE_CLEAR_DEPTH) {
529 BEGIN_NVC0(push, NVC0_3D(CLEAR_DEPTH), 1);
530 PUSH_DATAf(push, depth);
531 mode |= NVC0_3D_CLEAR_BUFFERS_Z;
532 }
533
534 if (clear_flags & PIPE_CLEAR_STENCIL) {
535 BEGIN_NVC0(push, NVC0_3D(CLEAR_STENCIL), 1);
536 PUSH_DATA (push, stencil & 0xff);
537 mode |= NVC0_3D_CLEAR_BUFFERS_S;
538 }
539
540 BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
541 PUSH_DATA (push, ( width << 16) | dstx);
542 PUSH_DATA (push, (height << 16) | dsty);
543
544 BEGIN_NVC0(push, NVC0_3D(ZETA_ADDRESS_HIGH), 5);
545 PUSH_DATAh(push, mt->base.address + sf->offset);
546 PUSH_DATA (push, mt->base.address + sf->offset);
547 PUSH_DATA (push, nvc0_format_table[dst->format].rt);
548 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
549 PUSH_DATA (push, mt->layer_stride >> 2);
550 BEGIN_NVC0(push, NVC0_3D(ZETA_ENABLE), 1);
551 PUSH_DATA (push, 1);
552 BEGIN_NVC0(push, NVC0_3D(ZETA_HORIZ), 3);
553 PUSH_DATA (push, sf->width);
554 PUSH_DATA (push, sf->height);
555 PUSH_DATA (push, (unk << 16) | (dst->u.tex.first_layer + sf->depth));
556 BEGIN_NVC0(push, NVC0_3D(ZETA_BASE_LAYER), 1);
557 PUSH_DATA (push, dst->u.tex.first_layer);
558 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), mt->ms_mode);
559
560 IMMED_NVC0(push, NVC0_3D(COND_MODE), NVC0_3D_COND_MODE_ALWAYS);
561
562 BEGIN_NIC0(push, NVC0_3D(CLEAR_BUFFERS), sf->depth);
563 for (z = 0; z < sf->depth; ++z) {
564 PUSH_DATA (push, mode |
565 (z << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
566 }
567
568 IMMED_NVC0(push, NVC0_3D(COND_MODE), nvc0->cond_condmode);
569
570 nvc0->dirty |= NVC0_NEW_FRAMEBUFFER;
571 }
572
573 void
574 nvc0_clear(struct pipe_context *pipe, unsigned buffers,
575 const union pipe_color_union *color,
576 double depth, unsigned stencil)
577 {
578 struct nvc0_context *nvc0 = nvc0_context(pipe);
579 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
580 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
581 unsigned i, j, k;
582 uint32_t mode = 0;
583
584 /* don't need NEW_BLEND, COLOR_MASK doesn't affect CLEAR_BUFFERS */
585 if (!nvc0_state_validate(nvc0, NVC0_NEW_FRAMEBUFFER, 9 + (fb->nr_cbufs * 2)))
586 return;
587
588 if (buffers & PIPE_CLEAR_COLOR && fb->nr_cbufs) {
589 BEGIN_NVC0(push, NVC0_3D(CLEAR_COLOR(0)), 4);
590 PUSH_DATAf(push, color->f[0]);
591 PUSH_DATAf(push, color->f[1]);
592 PUSH_DATAf(push, color->f[2]);
593 PUSH_DATAf(push, color->f[3]);
594 if (buffers & PIPE_CLEAR_COLOR0)
595 mode =
596 NVC0_3D_CLEAR_BUFFERS_R | NVC0_3D_CLEAR_BUFFERS_G |
597 NVC0_3D_CLEAR_BUFFERS_B | NVC0_3D_CLEAR_BUFFERS_A;
598 }
599
600 if (buffers & PIPE_CLEAR_DEPTH) {
601 BEGIN_NVC0(push, NVC0_3D(CLEAR_DEPTH), 1);
602 PUSH_DATA (push, fui(depth));
603 mode |= NVC0_3D_CLEAR_BUFFERS_Z;
604 }
605
606 if (buffers & PIPE_CLEAR_STENCIL) {
607 BEGIN_NVC0(push, NVC0_3D(CLEAR_STENCIL), 1);
608 PUSH_DATA (push, stencil & 0xff);
609 mode |= NVC0_3D_CLEAR_BUFFERS_S;
610 }
611
612 if (mode) {
613 int zs_layers = 0, color0_layers = 0;
614 if (fb->cbufs[0] && (mode & 0x3c))
615 color0_layers = fb->cbufs[0]->u.tex.last_layer -
616 fb->cbufs[0]->u.tex.first_layer + 1;
617 if (fb->zsbuf && (mode & ~0x3c))
618 zs_layers = fb->zsbuf->u.tex.last_layer -
619 fb->zsbuf->u.tex.first_layer + 1;
620
621 for (j = 0; j < MIN2(zs_layers, color0_layers); j++) {
622 BEGIN_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 1);
623 PUSH_DATA(push, mode | (j << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
624 }
625 for (k = j; k < zs_layers; k++) {
626 BEGIN_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 1);
627 PUSH_DATA(push, (mode & ~0x3c) | (k << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
628 }
629 for (k = j; k < color0_layers; k++) {
630 BEGIN_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 1);
631 PUSH_DATA(push, (mode & 0x3c) | (k << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
632 }
633 }
634
635 for (i = 1; i < fb->nr_cbufs; i++) {
636 struct pipe_surface *sf = fb->cbufs[i];
637 if (!sf || !(buffers & (PIPE_CLEAR_COLOR0 << i)))
638 continue;
639 for (j = 0; j <= sf->u.tex.last_layer - sf->u.tex.first_layer; j++) {
640 BEGIN_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 1);
641 PUSH_DATA (push, (i << 6) | 0x3c |
642 (j << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
643 }
644 }
645 }
646
647
648 /* =============================== BLIT CODE ===================================
649 */
650
651 struct nvc0_blitter
652 {
653 struct nvc0_program *fp[NV50_BLIT_MAX_TEXTURE_TYPES][NV50_BLIT_MODES];
654 struct nvc0_program vp;
655
656 struct nv50_tsc_entry sampler[2]; /* nearest, bilinear */
657
658 pipe_mutex mutex;
659
660 struct nvc0_screen *screen;
661 };
662
663 struct nvc0_blitctx
664 {
665 struct nvc0_context *nvc0;
666 struct nvc0_program *fp;
667 uint8_t mode;
668 uint16_t color_mask;
669 uint8_t filter;
670 uint8_t render_condition_enable;
671 enum pipe_texture_target target;
672 struct {
673 struct pipe_framebuffer_state fb;
674 struct nvc0_rasterizer_stateobj *rast;
675 struct nvc0_program *vp;
676 struct nvc0_program *tcp;
677 struct nvc0_program *tep;
678 struct nvc0_program *gp;
679 struct nvc0_program *fp;
680 unsigned num_textures[5];
681 unsigned num_samplers[5];
682 struct pipe_sampler_view *texture[2];
683 struct nv50_tsc_entry *sampler[2];
684 unsigned min_samples;
685 uint32_t dirty;
686 } saved;
687 struct nvc0_rasterizer_stateobj rast;
688 };
689
690 static void
691 nvc0_blitter_make_vp(struct nvc0_blitter *blit)
692 {
693 static const uint32_t code_nvc0[] =
694 {
695 0xfff11c26, 0x06000080, /* vfetch b64 $r4:$r5 a[0x80] */
696 0xfff01c46, 0x06000090, /* vfetch b96 $r0:$r1:$r2 a[0x90] */
697 0x13f01c26, 0x0a7e0070, /* export b64 o[0x70] $r4:$r5 */
698 0x03f01c46, 0x0a7e0080, /* export b96 o[0x80] $r0:$r1:$r2 */
699 0x00001de7, 0x80000000, /* exit */
700 };
701 static const uint32_t code_nve4[] =
702 {
703 0x00000007, 0x20000000, /* sched */
704 0xfff11c26, 0x06000080, /* vfetch b64 $r4:$r5 a[0x80] */
705 0xfff01c46, 0x06000090, /* vfetch b96 $r0:$r1:$r2 a[0x90] */
706 0x13f01c26, 0x0a7e0070, /* export b64 o[0x70] $r4:$r5 */
707 0x03f01c46, 0x0a7e0080, /* export b96 o[0x80] $r0:$r1:$r2 */
708 0x00001de7, 0x80000000, /* exit */
709 };
710 static const uint32_t code_gk110[] =
711 {
712 0x00000000, 0x08000000, /* sched */
713 0x401ffc12, 0x7ec7fc00, /* ld b64 $r4d a[0x80] 0x0 0x0 */
714 0x481ffc02, 0x7ecbfc00, /* ld b96 $r0t a[0x90] 0x0 0x0 */
715 0x381ffc12, 0x7f07fc00, /* st b64 a[0x70] $r4d 0x0 0x0 */
716 0x401ffc02, 0x7f0bfc00, /* st b96 a[0x80] $r0t 0x0 0x0 */
717 0x001c003c, 0x18000000, /* exit */
718 };
719 static const uint32_t code_gm107[] =
720 {
721 0xfc0007e0, 0x001f8000, /* sched 0x7e0 0x7e0 0x7e0 */
722 0x0807ff04, 0xefd8ff80, /* ld b64 $r4 a[0x80] 0x0 */
723 0x0907ff00, 0xefd97f80, /* ld b96 $r0 a[0x90] 0x0 */
724 0x0707ff04, 0xeff0ff80, /* st b64 a[0x70] $r4 0x0 */
725 0xfc0007e0, 0x00000000, /* sched 0x7e0 0x7e0 0x0 */
726 0x0807ff00, 0xeff17f80, /* st b96 a[0x80] $r0 0x0 */
727 0x0007000f, 0xe3000000, /* exit */
728 };
729
730 blit->vp.type = PIPE_SHADER_VERTEX;
731 blit->vp.translated = true;
732 if (blit->screen->base.class_3d >= GM107_3D_CLASS) {
733 blit->vp.code = (uint32_t *)code_gm107; /* const_cast */
734 blit->vp.code_size = sizeof(code_gm107);
735 } else
736 if (blit->screen->base.class_3d >= NVF0_3D_CLASS) {
737 blit->vp.code = (uint32_t *)code_gk110; /* const_cast */
738 blit->vp.code_size = sizeof(code_gk110);
739 } else
740 if (blit->screen->base.class_3d >= NVE4_3D_CLASS) {
741 blit->vp.code = (uint32_t *)code_nve4; /* const_cast */
742 blit->vp.code_size = sizeof(code_nve4);
743 } else {
744 blit->vp.code = (uint32_t *)code_nvc0; /* const_cast */
745 blit->vp.code_size = sizeof(code_nvc0);
746 }
747 blit->vp.num_gprs = 6;
748 blit->vp.vp.edgeflag = PIPE_MAX_ATTRIBS;
749
750 blit->vp.hdr[0] = 0x00020461; /* vertprog magic */
751 blit->vp.hdr[4] = 0x000ff000; /* no outputs read */
752 blit->vp.hdr[6] = 0x00000073; /* a[0x80].xy, a[0x90].xyz */
753 blit->vp.hdr[13] = 0x00073000; /* o[0x70].xy, o[0x80].xyz */
754 }
755
756 static void
757 nvc0_blitter_make_sampler(struct nvc0_blitter *blit)
758 {
759 /* clamp to edge, min/max lod = 0, nearest filtering */
760
761 blit->sampler[0].id = -1;
762
763 blit->sampler[0].tsc[0] = NV50_TSC_0_SRGB_CONVERSION_ALLOWED |
764 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPS__SHIFT) |
765 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPT__SHIFT) |
766 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPR__SHIFT);
767 blit->sampler[0].tsc[1] =
768 NV50_TSC_1_MAGF_NEAREST | NV50_TSC_1_MINF_NEAREST | NV50_TSC_1_MIPF_NONE;
769
770 /* clamp to edge, min/max lod = 0, bilinear filtering */
771
772 blit->sampler[1].id = -1;
773
774 blit->sampler[1].tsc[0] = blit->sampler[0].tsc[0];
775 blit->sampler[1].tsc[1] =
776 NV50_TSC_1_MAGF_LINEAR | NV50_TSC_1_MINF_LINEAR | NV50_TSC_1_MIPF_NONE;
777 }
778
779 static void
780 nvc0_blit_select_fp(struct nvc0_blitctx *ctx, const struct pipe_blit_info *info)
781 {
782 struct nvc0_blitter *blitter = ctx->nvc0->screen->blitter;
783
784 const enum pipe_texture_target ptarg =
785 nv50_blit_reinterpret_pipe_texture_target(info->src.resource->target);
786
787 const unsigned targ = nv50_blit_texture_type(ptarg);
788 const unsigned mode = ctx->mode;
789
790 if (!blitter->fp[targ][mode]) {
791 pipe_mutex_lock(blitter->mutex);
792 if (!blitter->fp[targ][mode])
793 blitter->fp[targ][mode] =
794 nv50_blitter_make_fp(&ctx->nvc0->base.pipe, mode, ptarg);
795 pipe_mutex_unlock(blitter->mutex);
796 }
797 ctx->fp = blitter->fp[targ][mode];
798 }
799
800 static void
801 nvc0_blit_set_dst(struct nvc0_blitctx *ctx,
802 struct pipe_resource *res, unsigned level, unsigned layer,
803 enum pipe_format format)
804 {
805 struct nvc0_context *nvc0 = ctx->nvc0;
806 struct pipe_context *pipe = &nvc0->base.pipe;
807 struct pipe_surface templ;
808
809 if (util_format_is_depth_or_stencil(format))
810 templ.format = nv50_blit_zeta_to_colour_format(format);
811 else
812 templ.format = format;
813
814 templ.u.tex.level = level;
815 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
816
817 if (layer == -1) {
818 templ.u.tex.first_layer = 0;
819 templ.u.tex.last_layer =
820 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
821 }
822
823 nvc0->framebuffer.cbufs[0] = nvc0_miptree_surface_new(pipe, res, &templ);
824 nvc0->framebuffer.nr_cbufs = 1;
825 nvc0->framebuffer.zsbuf = NULL;
826 nvc0->framebuffer.width = nvc0->framebuffer.cbufs[0]->width;
827 nvc0->framebuffer.height = nvc0->framebuffer.cbufs[0]->height;
828 }
829
830 static void
831 nvc0_blit_set_src(struct nvc0_blitctx *ctx,
832 struct pipe_resource *res, unsigned level, unsigned layer,
833 enum pipe_format format, const uint8_t filter)
834 {
835 struct nvc0_context *nvc0 = ctx->nvc0;
836 struct pipe_context *pipe = &nvc0->base.pipe;
837 struct pipe_sampler_view templ;
838 uint32_t flags;
839 unsigned s;
840 enum pipe_texture_target target;
841
842 target = nv50_blit_reinterpret_pipe_texture_target(res->target);
843
844 templ.format = format;
845 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
846 templ.u.tex.first_level = templ.u.tex.last_level = level;
847 templ.swizzle_r = PIPE_SWIZZLE_RED;
848 templ.swizzle_g = PIPE_SWIZZLE_GREEN;
849 templ.swizzle_b = PIPE_SWIZZLE_BLUE;
850 templ.swizzle_a = PIPE_SWIZZLE_ALPHA;
851
852 if (layer == -1) {
853 templ.u.tex.first_layer = 0;
854 templ.u.tex.last_layer =
855 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
856 }
857
858 flags = res->last_level ? 0 : NV50_TEXVIEW_SCALED_COORDS;
859 flags |= NV50_TEXVIEW_ACCESS_RESOLVE;
860 if (filter && res->nr_samples == 8)
861 flags |= NV50_TEXVIEW_FILTER_MSAA8;
862
863 nvc0->textures[4][0] = nvc0_create_texture_view(
864 pipe, res, &templ, flags, target);
865 nvc0->textures[4][1] = NULL;
866
867 for (s = 0; s <= 3; ++s)
868 nvc0->num_textures[s] = 0;
869 nvc0->num_textures[4] = 1;
870
871 templ.format = nv50_zs_to_s_format(format);
872 if (templ.format != format) {
873 nvc0->textures[4][1] = nvc0_create_texture_view(
874 pipe, res, &templ, flags, target);
875 nvc0->num_textures[4] = 2;
876 }
877 }
878
879 static void
880 nvc0_blitctx_prepare_state(struct nvc0_blitctx *blit)
881 {
882 struct nouveau_pushbuf *push = blit->nvc0->base.pushbuf;
883
884 /* TODO: maybe make this a MACRO (if we need more logic) ? */
885
886 if (blit->nvc0->cond_query && !blit->render_condition_enable)
887 IMMED_NVC0(push, NVC0_3D(COND_MODE), NVC0_3D_COND_MODE_ALWAYS);
888
889 /* blend state */
890 BEGIN_NVC0(push, NVC0_3D(COLOR_MASK(0)), 1);
891 PUSH_DATA (push, blit->color_mask);
892 IMMED_NVC0(push, NVC0_3D(BLEND_ENABLE(0)), 0);
893 IMMED_NVC0(push, NVC0_3D(LOGIC_OP_ENABLE), 0);
894
895 /* rasterizer state */
896 IMMED_NVC0(push, NVC0_3D(FRAG_COLOR_CLAMP_EN), 0);
897 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 0);
898 BEGIN_NVC0(push, NVC0_3D(MSAA_MASK(0)), 4);
899 PUSH_DATA (push, 0xffff);
900 PUSH_DATA (push, 0xffff);
901 PUSH_DATA (push, 0xffff);
902 PUSH_DATA (push, 0xffff);
903 BEGIN_NVC0(push, NVC0_3D(MACRO_POLYGON_MODE_FRONT), 1);
904 PUSH_DATA (push, NVC0_3D_MACRO_POLYGON_MODE_FRONT_FILL);
905 BEGIN_NVC0(push, NVC0_3D(MACRO_POLYGON_MODE_BACK), 1);
906 PUSH_DATA (push, NVC0_3D_MACRO_POLYGON_MODE_BACK_FILL);
907 IMMED_NVC0(push, NVC0_3D(POLYGON_SMOOTH_ENABLE), 0);
908 IMMED_NVC0(push, NVC0_3D(POLYGON_OFFSET_FILL_ENABLE), 0);
909 IMMED_NVC0(push, NVC0_3D(POLYGON_STIPPLE_ENABLE), 0);
910 IMMED_NVC0(push, NVC0_3D(CULL_FACE_ENABLE), 0);
911
912 /* zsa state */
913 IMMED_NVC0(push, NVC0_3D(DEPTH_TEST_ENABLE), 0);
914 IMMED_NVC0(push, NVC0_3D(DEPTH_BOUNDS_EN), 0);
915 IMMED_NVC0(push, NVC0_3D(STENCIL_ENABLE), 0);
916 IMMED_NVC0(push, NVC0_3D(ALPHA_TEST_ENABLE), 0);
917
918 /* disable transform feedback */
919 IMMED_NVC0(push, NVC0_3D(TFB_ENABLE), 0);
920 }
921
922 static void
923 nvc0_blitctx_pre_blit(struct nvc0_blitctx *ctx)
924 {
925 struct nvc0_context *nvc0 = ctx->nvc0;
926 struct nvc0_blitter *blitter = nvc0->screen->blitter;
927 int s;
928
929 ctx->saved.fb.width = nvc0->framebuffer.width;
930 ctx->saved.fb.height = nvc0->framebuffer.height;
931 ctx->saved.fb.nr_cbufs = nvc0->framebuffer.nr_cbufs;
932 ctx->saved.fb.cbufs[0] = nvc0->framebuffer.cbufs[0];
933 ctx->saved.fb.zsbuf = nvc0->framebuffer.zsbuf;
934
935 ctx->saved.rast = nvc0->rast;
936
937 ctx->saved.vp = nvc0->vertprog;
938 ctx->saved.tcp = nvc0->tctlprog;
939 ctx->saved.tep = nvc0->tevlprog;
940 ctx->saved.gp = nvc0->gmtyprog;
941 ctx->saved.fp = nvc0->fragprog;
942
943 ctx->saved.min_samples = nvc0->min_samples;
944
945 nvc0->rast = &ctx->rast;
946
947 nvc0->vertprog = &blitter->vp;
948 nvc0->tctlprog = NULL;
949 nvc0->tevlprog = NULL;
950 nvc0->gmtyprog = NULL;
951 nvc0->fragprog = ctx->fp;
952
953 for (s = 0; s <= 4; ++s) {
954 ctx->saved.num_textures[s] = nvc0->num_textures[s];
955 ctx->saved.num_samplers[s] = nvc0->num_samplers[s];
956 nvc0->textures_dirty[s] = (1 << nvc0->num_textures[s]) - 1;
957 nvc0->samplers_dirty[s] = (1 << nvc0->num_samplers[s]) - 1;
958 }
959 ctx->saved.texture[0] = nvc0->textures[4][0];
960 ctx->saved.texture[1] = nvc0->textures[4][1];
961 ctx->saved.sampler[0] = nvc0->samplers[4][0];
962 ctx->saved.sampler[1] = nvc0->samplers[4][1];
963
964 nvc0->samplers[4][0] = &blitter->sampler[ctx->filter];
965 nvc0->samplers[4][1] = &blitter->sampler[ctx->filter];
966
967 for (s = 0; s <= 3; ++s)
968 nvc0->num_samplers[s] = 0;
969 nvc0->num_samplers[4] = 2;
970
971 nvc0->min_samples = 1;
972
973 ctx->saved.dirty = nvc0->dirty;
974
975 nvc0->textures_dirty[4] |= 3;
976 nvc0->samplers_dirty[4] |= 3;
977
978 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_FB);
979 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(4, 0));
980 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(4, 1));
981
982 nvc0->dirty = NVC0_NEW_FRAMEBUFFER | NVC0_NEW_MIN_SAMPLES |
983 NVC0_NEW_VERTPROG | NVC0_NEW_FRAGPROG |
984 NVC0_NEW_TCTLPROG | NVC0_NEW_TEVLPROG | NVC0_NEW_GMTYPROG |
985 NVC0_NEW_TEXTURES | NVC0_NEW_SAMPLERS;
986 }
987
988 static void
989 nvc0_blitctx_post_blit(struct nvc0_blitctx *blit)
990 {
991 struct nvc0_context *nvc0 = blit->nvc0;
992 int s;
993
994 pipe_surface_reference(&nvc0->framebuffer.cbufs[0], NULL);
995
996 nvc0->framebuffer.width = blit->saved.fb.width;
997 nvc0->framebuffer.height = blit->saved.fb.height;
998 nvc0->framebuffer.nr_cbufs = blit->saved.fb.nr_cbufs;
999 nvc0->framebuffer.cbufs[0] = blit->saved.fb.cbufs[0];
1000 nvc0->framebuffer.zsbuf = blit->saved.fb.zsbuf;
1001
1002 nvc0->rast = blit->saved.rast;
1003
1004 nvc0->vertprog = blit->saved.vp;
1005 nvc0->tctlprog = blit->saved.tcp;
1006 nvc0->tevlprog = blit->saved.tep;
1007 nvc0->gmtyprog = blit->saved.gp;
1008 nvc0->fragprog = blit->saved.fp;
1009
1010 nvc0->min_samples = blit->saved.min_samples;
1011
1012 pipe_sampler_view_reference(&nvc0->textures[4][0], NULL);
1013 pipe_sampler_view_reference(&nvc0->textures[4][1], NULL);
1014
1015 for (s = 0; s <= 4; ++s) {
1016 nvc0->num_textures[s] = blit->saved.num_textures[s];
1017 nvc0->num_samplers[s] = blit->saved.num_samplers[s];
1018 nvc0->textures_dirty[s] = (1 << nvc0->num_textures[s]) - 1;
1019 nvc0->samplers_dirty[s] = (1 << nvc0->num_samplers[s]) - 1;
1020 }
1021 nvc0->textures[4][0] = blit->saved.texture[0];
1022 nvc0->textures[4][1] = blit->saved.texture[1];
1023 nvc0->samplers[4][0] = blit->saved.sampler[0];
1024 nvc0->samplers[4][1] = blit->saved.sampler[1];
1025
1026 nvc0->textures_dirty[4] |= 3;
1027 nvc0->samplers_dirty[4] |= 3;
1028
1029 if (nvc0->cond_query && !blit->render_condition_enable)
1030 nvc0->base.pipe.render_condition(&nvc0->base.pipe, nvc0->cond_query,
1031 nvc0->cond_cond, nvc0->cond_mode);
1032
1033 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_FB);
1034 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(4, 0));
1035 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(4, 1));
1036
1037 nvc0->dirty = blit->saved.dirty |
1038 (NVC0_NEW_FRAMEBUFFER | NVC0_NEW_SCISSOR | NVC0_NEW_SAMPLE_MASK |
1039 NVC0_NEW_RASTERIZER | NVC0_NEW_ZSA | NVC0_NEW_BLEND |
1040 NVC0_NEW_VIEWPORT |
1041 NVC0_NEW_TEXTURES | NVC0_NEW_SAMPLERS |
1042 NVC0_NEW_VERTPROG | NVC0_NEW_FRAGPROG |
1043 NVC0_NEW_TCTLPROG | NVC0_NEW_TEVLPROG | NVC0_NEW_GMTYPROG |
1044 NVC0_NEW_TFB_TARGETS | NVC0_NEW_VERTEX | NVC0_NEW_ARRAYS);
1045 nvc0->scissors_dirty |= 1;
1046 nvc0->viewports_dirty |= 1;
1047
1048 nvc0->base.pipe.set_min_samples(&nvc0->base.pipe, blit->saved.min_samples);
1049 }
1050
1051 static void
1052 nvc0_blit_3d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
1053 {
1054 struct nvc0_blitctx *blit = nvc0->blit;
1055 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
1056 struct pipe_resource *src = info->src.resource;
1057 struct pipe_resource *dst = info->dst.resource;
1058 struct nouveau_bo *vtxbuf_bo;
1059 uint32_t stride, length, *vbuf;
1060 uint64_t vtxbuf;
1061 int32_t minx, maxx, miny, maxy;
1062 int32_t i, n;
1063 float x0, x1, y0, y1, z;
1064 float dz;
1065 float x_range, y_range;
1066
1067 blit->mode = nv50_blit_select_mode(info);
1068 blit->color_mask = nv50_blit_derive_color_mask(info);
1069 blit->filter = nv50_blit_get_filter(info);
1070 blit->render_condition_enable = info->render_condition_enable;
1071
1072 nvc0_blit_select_fp(blit, info);
1073 nvc0_blitctx_pre_blit(blit);
1074
1075 nvc0_blit_set_dst(blit, dst, info->dst.level, -1, info->dst.format);
1076 nvc0_blit_set_src(blit, src, info->src.level, -1, info->src.format,
1077 blit->filter);
1078
1079 nvc0_blitctx_prepare_state(blit);
1080
1081 nvc0_state_validate(nvc0, ~0, 48);
1082
1083 x_range = (float)info->src.box.width / (float)info->dst.box.width;
1084 y_range = (float)info->src.box.height / (float)info->dst.box.height;
1085
1086 x0 = (float)info->src.box.x - x_range * (float)info->dst.box.x;
1087 y0 = (float)info->src.box.y - y_range * (float)info->dst.box.y;
1088
1089 x1 = x0 + 16384.0f * x_range;
1090 y1 = y0 + 16384.0f * y_range;
1091
1092 x0 *= (float)(1 << nv50_miptree(src)->ms_x);
1093 x1 *= (float)(1 << nv50_miptree(src)->ms_x);
1094 y0 *= (float)(1 << nv50_miptree(src)->ms_y);
1095 y1 *= (float)(1 << nv50_miptree(src)->ms_y);
1096
1097 dz = (float)info->src.box.depth / (float)info->dst.box.depth;
1098 z = (float)info->src.box.z;
1099 if (nv50_miptree(src)->layout_3d)
1100 z += 0.5f * dz;
1101
1102 if (src->last_level > 0) {
1103 /* If there are mip maps, GPU always assumes normalized coordinates. */
1104 const unsigned l = info->src.level;
1105 const float fh = u_minify(src->width0 << nv50_miptree(src)->ms_x, l);
1106 const float fv = u_minify(src->height0 << nv50_miptree(src)->ms_y, l);
1107 x0 /= fh;
1108 x1 /= fh;
1109 y0 /= fv;
1110 y1 /= fv;
1111 if (nv50_miptree(src)->layout_3d) {
1112 z /= u_minify(src->depth0, l);
1113 dz /= u_minify(src->depth0, l);
1114 }
1115 }
1116
1117 IMMED_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 0);
1118 IMMED_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 0x2 |
1119 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_RANGE_0_1);
1120 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_HORIZ(0)), 2);
1121 PUSH_DATA (push, nvc0->framebuffer.width << 16);
1122 PUSH_DATA (push, nvc0->framebuffer.height << 16);
1123
1124 /* Draw a large triangle in screen coordinates covering the whole
1125 * render target, with scissors defining the destination region.
1126 * The vertex is supplied with non-normalized texture coordinates
1127 * arranged in a way to yield the desired offset and scale.
1128 */
1129
1130 minx = info->dst.box.x;
1131 maxx = info->dst.box.x + info->dst.box.width;
1132 miny = info->dst.box.y;
1133 maxy = info->dst.box.y + info->dst.box.height;
1134 if (info->scissor_enable) {
1135 minx = MAX2(minx, info->scissor.minx);
1136 maxx = MIN2(maxx, info->scissor.maxx);
1137 miny = MAX2(miny, info->scissor.miny);
1138 maxy = MIN2(maxy, info->scissor.maxy);
1139 }
1140 BEGIN_NVC0(push, NVC0_3D(SCISSOR_HORIZ(0)), 2);
1141 PUSH_DATA (push, (maxx << 16) | minx);
1142 PUSH_DATA (push, (maxy << 16) | miny);
1143
1144 stride = (3 + 2) * 4;
1145 length = stride * 3 * info->dst.box.depth;
1146
1147 vbuf = nouveau_scratch_get(&nvc0->base, length, &vtxbuf, &vtxbuf_bo);
1148 if (!vbuf) {
1149 assert(vbuf);
1150 return;
1151 }
1152
1153 BCTX_REFN_bo(nvc0->bufctx_3d, VTX_TMP, NOUVEAU_BO_GART | NOUVEAU_BO_RD, vtxbuf_bo);
1154 nouveau_pushbuf_validate(push);
1155
1156 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(0)), 4);
1157 PUSH_DATA (push, NVC0_3D_VERTEX_ARRAY_FETCH_ENABLE | stride <<
1158 NVC0_3D_VERTEX_ARRAY_FETCH_STRIDE__SHIFT);
1159 PUSH_DATAh(push, vtxbuf);
1160 PUSH_DATA (push, vtxbuf);
1161 PUSH_DATA (push, 0);
1162 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_LIMIT_HIGH(0)), 2);
1163 PUSH_DATAh(push, vtxbuf + length - 1);
1164 PUSH_DATA (push, vtxbuf + length - 1);
1165
1166 n = MAX2(2, nvc0->state.num_vtxelts);
1167
1168 BEGIN_NVC0(push, NVC0_3D(VERTEX_ATTRIB_FORMAT(0)), n);
1169 PUSH_DATA (push, NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT |
1170 NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32_32 | 0x00 <<
1171 NVC0_3D_VERTEX_ATTRIB_FORMAT_OFFSET__SHIFT);
1172 PUSH_DATA (push, NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT |
1173 NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32_32_32 | 0x08 <<
1174 NVC0_3D_VERTEX_ATTRIB_FORMAT_OFFSET__SHIFT);
1175 for (i = 2; i < n; i++) {
1176 PUSH_DATA(push, NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT |
1177 NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32 |
1178 NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST);
1179 }
1180 if (nvc0->state.instance_elts) {
1181 nvc0->state.instance_elts = 0;
1182 BEGIN_NVC0(push, NVC0_3D(MACRO_VERTEX_ARRAY_PER_INSTANCE), 2);
1183 PUSH_DATA (push, n);
1184 PUSH_DATA (push, 0);
1185 }
1186 nvc0->state.num_vtxelts = 2;
1187
1188 for (i = 0; i < info->dst.box.depth; ++i, z += dz) {
1189 if (info->dst.box.z + i) {
1190 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1191 PUSH_DATA (push, info->dst.box.z + i);
1192 }
1193
1194 *(vbuf++) = fui(0.0f);
1195 *(vbuf++) = fui(0.0f);
1196 *(vbuf++) = fui(x0);
1197 *(vbuf++) = fui(y0);
1198 *(vbuf++) = fui(z);
1199
1200 *(vbuf++) = fui(16384 << nv50_miptree(dst)->ms_x);
1201 *(vbuf++) = fui(0.0f);
1202 *(vbuf++) = fui(x1);
1203 *(vbuf++) = fui(y0);
1204 *(vbuf++) = fui(z);
1205
1206 *(vbuf++) = fui(0.0f);
1207 *(vbuf++) = fui(16384 << nv50_miptree(dst)->ms_y);
1208 *(vbuf++) = fui(x0);
1209 *(vbuf++) = fui(y1);
1210 *(vbuf++) = fui(z);
1211
1212 IMMED_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL),
1213 NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES);
1214 BEGIN_NVC0(push, NVC0_3D(VERTEX_BUFFER_FIRST), 2);
1215 PUSH_DATA (push, i * 3);
1216 PUSH_DATA (push, 3);
1217 IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
1218 }
1219 if (info->dst.box.z + info->dst.box.depth - 1)
1220 IMMED_NVC0(push, NVC0_3D(LAYER), 0);
1221
1222 nvc0_blitctx_post_blit(blit);
1223
1224 /* restore viewport transform */
1225 IMMED_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1226 }
1227
1228 static void
1229 nvc0_blit_eng2d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
1230 {
1231 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
1232 struct nv50_miptree *dst = nv50_miptree(info->dst.resource);
1233 struct nv50_miptree *src = nv50_miptree(info->src.resource);
1234 const int32_t srcx_adj = info->src.box.width < 0 ? -1 : 0;
1235 const int32_t srcy_adj = info->src.box.height < 0 ? -1 : 0;
1236 const int dz = info->dst.box.z;
1237 const int sz = info->src.box.z;
1238 uint32_t dstw, dsth;
1239 int32_t dstx, dsty;
1240 int64_t srcx, srcy;
1241 int64_t du_dx, dv_dy;
1242 int i;
1243 uint32_t mode;
1244 uint32_t mask = nv50_blit_eng2d_get_mask(info);
1245 bool b;
1246
1247 mode = nv50_blit_get_filter(info) ?
1248 NV50_2D_BLIT_CONTROL_FILTER_BILINEAR :
1249 NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE;
1250 mode |= (src->base.base.nr_samples > dst->base.base.nr_samples) ?
1251 NV50_2D_BLIT_CONTROL_ORIGIN_CORNER : NV50_2D_BLIT_CONTROL_ORIGIN_CENTER;
1252
1253 du_dx = ((int64_t)info->src.box.width << 32) / info->dst.box.width;
1254 dv_dy = ((int64_t)info->src.box.height << 32) / info->dst.box.height;
1255
1256 b = info->dst.format == info->src.format;
1257 nvc0_2d_texture_set(push, 1, dst, info->dst.level, dz, info->dst.format, b);
1258 nvc0_2d_texture_set(push, 0, src, info->src.level, sz, info->src.format, b);
1259
1260 if (info->scissor_enable) {
1261 BEGIN_NVC0(push, NVC0_2D(CLIP_X), 5);
1262 PUSH_DATA (push, info->scissor.minx << dst->ms_x);
1263 PUSH_DATA (push, info->scissor.miny << dst->ms_y);
1264 PUSH_DATA (push, (info->scissor.maxx - info->scissor.minx) << dst->ms_x);
1265 PUSH_DATA (push, (info->scissor.maxy - info->scissor.miny) << dst->ms_y);
1266 PUSH_DATA (push, 1); /* enable */
1267 }
1268
1269 if (nvc0->cond_query && info->render_condition_enable)
1270 IMMED_NVC0(push, NVC0_2D(COND_MODE), nvc0->cond_condmode);
1271
1272 if (mask != 0xffffffff) {
1273 IMMED_NVC0(push, NVC0_2D(ROP), 0xca); /* DPSDxax */
1274 IMMED_NVC0(push, NVC0_2D(PATTERN_COLOR_FORMAT),
1275 NV50_2D_PATTERN_COLOR_FORMAT_A8R8G8B8);
1276 BEGIN_NVC0(push, NVC0_2D(PATTERN_BITMAP_COLOR(0)), 4);
1277 PUSH_DATA (push, 0x00000000);
1278 PUSH_DATA (push, mask);
1279 PUSH_DATA (push, 0xffffffff);
1280 PUSH_DATA (push, 0xffffffff);
1281 IMMED_NVC0(push, NVC0_2D(OPERATION), NV50_2D_OPERATION_ROP);
1282 } else
1283 if (info->src.format != info->dst.format) {
1284 if (info->src.format == PIPE_FORMAT_R8_UNORM ||
1285 info->src.format == PIPE_FORMAT_R8_SNORM ||
1286 info->src.format == PIPE_FORMAT_R16_UNORM ||
1287 info->src.format == PIPE_FORMAT_R16_SNORM ||
1288 info->src.format == PIPE_FORMAT_R16_FLOAT ||
1289 info->src.format == PIPE_FORMAT_R32_FLOAT) {
1290 mask = 0xffff0000; /* also makes condition for OPERATION reset true */
1291 BEGIN_NVC0(push, NVC0_2D(BETA4), 2);
1292 PUSH_DATA (push, mask);
1293 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY_PREMULT);
1294 } else
1295 if (info->src.format == PIPE_FORMAT_A8_UNORM) {
1296 mask = 0xff000000;
1297 BEGIN_NVC0(push, NVC0_2D(BETA4), 2);
1298 PUSH_DATA (push, mask);
1299 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY_PREMULT);
1300 }
1301 }
1302
1303 if (src->ms_x > dst->ms_x || src->ms_y > dst->ms_y) {
1304 /* ms_x is always >= ms_y */
1305 du_dx <<= src->ms_x - dst->ms_x;
1306 dv_dy <<= src->ms_y - dst->ms_y;
1307 } else {
1308 du_dx >>= dst->ms_x - src->ms_x;
1309 dv_dy >>= dst->ms_y - src->ms_y;
1310 }
1311
1312 srcx = (int64_t)(info->src.box.x + srcx_adj) << (src->ms_x + 32);
1313 srcy = (int64_t)(info->src.box.y + srcy_adj) << (src->ms_y + 32);
1314
1315 if (src->base.base.nr_samples > dst->base.base.nr_samples) {
1316 /* center src coorinates for proper MS resolve filtering */
1317 srcx += (int64_t)1 << (src->ms_x + 31);
1318 srcy += (int64_t)1 << (src->ms_y + 31);
1319 }
1320
1321 dstx = info->dst.box.x << dst->ms_x;
1322 dsty = info->dst.box.y << dst->ms_y;
1323
1324 dstw = info->dst.box.width << dst->ms_x;
1325 dsth = info->dst.box.height << dst->ms_y;
1326
1327 if (dstx < 0) {
1328 dstw += dstx;
1329 srcx -= du_dx * dstx;
1330 dstx = 0;
1331 }
1332 if (dsty < 0) {
1333 dsth += dsty;
1334 srcy -= dv_dy * dsty;
1335 dsty = 0;
1336 }
1337
1338 IMMED_NVC0(push, NVC0_2D(BLIT_CONTROL), mode);
1339 BEGIN_NVC0(push, NVC0_2D(BLIT_DST_X), 4);
1340 PUSH_DATA (push, dstx);
1341 PUSH_DATA (push, dsty);
1342 PUSH_DATA (push, dstw);
1343 PUSH_DATA (push, dsth);
1344 BEGIN_NVC0(push, NVC0_2D(BLIT_DU_DX_FRACT), 4);
1345 PUSH_DATA (push, du_dx);
1346 PUSH_DATA (push, du_dx >> 32);
1347 PUSH_DATA (push, dv_dy);
1348 PUSH_DATA (push, dv_dy >> 32);
1349
1350 BCTX_REFN(nvc0->bufctx, 2D, &dst->base, WR);
1351 BCTX_REFN(nvc0->bufctx, 2D, &src->base, RD);
1352 nouveau_pushbuf_bufctx(nvc0->base.pushbuf, nvc0->bufctx);
1353 if (nouveau_pushbuf_validate(nvc0->base.pushbuf))
1354 return;
1355
1356 for (i = 0; i < info->dst.box.depth; ++i) {
1357 if (i > 0) {
1358 /* no scaling in z-direction possible for eng2d blits */
1359 if (dst->layout_3d) {
1360 BEGIN_NVC0(push, NVC0_2D(DST_LAYER), 1);
1361 PUSH_DATA (push, info->dst.box.z + i);
1362 } else {
1363 const unsigned z = info->dst.box.z + i;
1364 const uint64_t address = dst->base.address +
1365 dst->level[info->dst.level].offset +
1366 z * dst->layer_stride;
1367 BEGIN_NVC0(push, NVC0_2D(DST_ADDRESS_HIGH), 2);
1368 PUSH_DATAh(push, address);
1369 PUSH_DATA (push, address);
1370 }
1371 if (src->layout_3d) {
1372 /* not possible because of depth tiling */
1373 assert(0);
1374 } else {
1375 const unsigned z = info->src.box.z + i;
1376 const uint64_t address = src->base.address +
1377 src->level[info->src.level].offset +
1378 z * src->layer_stride;
1379 BEGIN_NVC0(push, NVC0_2D(SRC_ADDRESS_HIGH), 2);
1380 PUSH_DATAh(push, address);
1381 PUSH_DATA (push, address);
1382 }
1383 BEGIN_NVC0(push, NVC0_2D(BLIT_SRC_Y_INT), 1); /* trigger */
1384 PUSH_DATA (push, srcy >> 32);
1385 } else {
1386 BEGIN_NVC0(push, NVC0_2D(BLIT_SRC_X_FRACT), 4);
1387 PUSH_DATA (push, srcx);
1388 PUSH_DATA (push, srcx >> 32);
1389 PUSH_DATA (push, srcy);
1390 PUSH_DATA (push, srcy >> 32);
1391 }
1392 }
1393 nvc0_resource_validate(&dst->base, NOUVEAU_BO_WR);
1394 nvc0_resource_validate(&src->base, NOUVEAU_BO_RD);
1395
1396 nouveau_bufctx_reset(nvc0->bufctx, NVC0_BIND_2D);
1397
1398 if (info->scissor_enable)
1399 IMMED_NVC0(push, NVC0_2D(CLIP_ENABLE), 0);
1400 if (mask != 0xffffffff)
1401 IMMED_NVC0(push, NVC0_2D(OPERATION), NV50_2D_OPERATION_SRCCOPY);
1402 if (nvc0->cond_query && info->render_condition_enable)
1403 IMMED_NVC0(push, NVC0_2D(COND_MODE), NV50_2D_COND_MODE_ALWAYS);
1404 }
1405
1406 static void
1407 nvc0_blit(struct pipe_context *pipe, const struct pipe_blit_info *info)
1408 {
1409 struct nvc0_context *nvc0 = nvc0_context(pipe);
1410 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
1411 bool eng3d = false;
1412
1413 if (util_format_is_depth_or_stencil(info->dst.resource->format)) {
1414 if (!(info->mask & PIPE_MASK_ZS))
1415 return;
1416 if (info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT ||
1417 info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
1418 eng3d = true;
1419 if (info->filter != PIPE_TEX_FILTER_NEAREST)
1420 eng3d = true;
1421 } else {
1422 if (!(info->mask & PIPE_MASK_RGBA))
1423 return;
1424 if (info->mask != PIPE_MASK_RGBA)
1425 eng3d = true;
1426 }
1427
1428 if (nv50_miptree(info->src.resource)->layout_3d) {
1429 eng3d = true;
1430 } else
1431 if (info->src.box.depth != info->dst.box.depth) {
1432 eng3d = true;
1433 debug_printf("blit: cannot filter array or cube textures in z direction");
1434 }
1435
1436 if (!eng3d && info->dst.format != info->src.format) {
1437 if (!nv50_2d_dst_format_faithful(info->dst.format)) {
1438 eng3d = true;
1439 } else
1440 if (!nv50_2d_src_format_faithful(info->src.format)) {
1441 if (!util_format_is_luminance(info->src.format)) {
1442 if (!nv50_2d_dst_format_ops_supported(info->dst.format))
1443 eng3d = true;
1444 else
1445 if (util_format_is_intensity(info->src.format))
1446 eng3d = info->src.format != PIPE_FORMAT_I8_UNORM;
1447 else
1448 if (util_format_is_alpha(info->src.format))
1449 eng3d = info->src.format != PIPE_FORMAT_A8_UNORM;
1450 else
1451 eng3d = !nv50_2d_format_supported(info->src.format);
1452 }
1453 } else
1454 if (util_format_is_luminance_alpha(info->src.format))
1455 eng3d = true;
1456 }
1457
1458 if (info->src.resource->nr_samples == 8 &&
1459 info->dst.resource->nr_samples <= 1)
1460 eng3d = true;
1461 #if 0
1462 /* FIXME: can't make this work with eng2d anymore, at least not on nv50 */
1463 if (info->src.resource->nr_samples > 1 ||
1464 info->dst.resource->nr_samples > 1)
1465 eng3d = true;
1466 #endif
1467 /* FIXME: find correct src coordinates adjustments */
1468 if ((info->src.box.width != info->dst.box.width &&
1469 info->src.box.width != -info->dst.box.width) ||
1470 (info->src.box.height != info->dst.box.height &&
1471 info->src.box.height != -info->dst.box.height))
1472 eng3d = true;
1473
1474 if (nvc0->screen->num_occlusion_queries_active)
1475 IMMED_NVC0(push, NVC0_3D(SAMPLECNT_ENABLE), 0);
1476
1477 if (!eng3d)
1478 nvc0_blit_eng2d(nvc0, info);
1479 else
1480 nvc0_blit_3d(nvc0, info);
1481
1482 if (nvc0->screen->num_occlusion_queries_active)
1483 IMMED_NVC0(push, NVC0_3D(SAMPLECNT_ENABLE), 1);
1484
1485 NOUVEAU_DRV_STAT(&nvc0->screen->base, tex_blit_count, 1);
1486 }
1487
1488 static void
1489 nvc0_flush_resource(struct pipe_context *ctx,
1490 struct pipe_resource *resource)
1491 {
1492 }
1493
1494 bool
1495 nvc0_blitter_create(struct nvc0_screen *screen)
1496 {
1497 screen->blitter = CALLOC_STRUCT(nvc0_blitter);
1498 if (!screen->blitter) {
1499 NOUVEAU_ERR("failed to allocate blitter struct\n");
1500 return false;
1501 }
1502 screen->blitter->screen = screen;
1503
1504 pipe_mutex_init(screen->blitter->mutex);
1505
1506 nvc0_blitter_make_vp(screen->blitter);
1507 nvc0_blitter_make_sampler(screen->blitter);
1508
1509 return true;
1510 }
1511
1512 void
1513 nvc0_blitter_destroy(struct nvc0_screen *screen)
1514 {
1515 struct nvc0_blitter *blitter = screen->blitter;
1516 unsigned i, m;
1517
1518 for (i = 0; i < NV50_BLIT_MAX_TEXTURE_TYPES; ++i) {
1519 for (m = 0; m < NV50_BLIT_MODES; ++m) {
1520 struct nvc0_program *prog = blitter->fp[i][m];
1521 if (prog) {
1522 nvc0_program_destroy(NULL, prog);
1523 FREE((void *)prog->pipe.tokens);
1524 FREE(prog);
1525 }
1526 }
1527 }
1528
1529 FREE(blitter);
1530 }
1531
1532 bool
1533 nvc0_blitctx_create(struct nvc0_context *nvc0)
1534 {
1535 nvc0->blit = CALLOC_STRUCT(nvc0_blitctx);
1536 if (!nvc0->blit) {
1537 NOUVEAU_ERR("failed to allocate blit context\n");
1538 return false;
1539 }
1540
1541 nvc0->blit->nvc0 = nvc0;
1542
1543 nvc0->blit->rast.pipe.half_pixel_center = 1;
1544
1545 return true;
1546 }
1547
1548 void
1549 nvc0_blitctx_destroy(struct nvc0_context *nvc0)
1550 {
1551 FREE(nvc0->blit);
1552 }
1553
1554 void
1555 nvc0_init_surface_functions(struct nvc0_context *nvc0)
1556 {
1557 struct pipe_context *pipe = &nvc0->base.pipe;
1558
1559 pipe->resource_copy_region = nvc0_resource_copy_region;
1560 pipe->blit = nvc0_blit;
1561 pipe->flush_resource = nvc0_flush_resource;
1562 pipe->clear_render_target = nvc0_clear_render_target;
1563 pipe->clear_depth_stencil = nvc0_clear_depth_stencil;
1564 pipe->clear_texture = nv50_clear_texture;
1565 pipe->clear_buffer = nvc0_clear_buffer;
1566 }