2 * Copyright 2008 Ben Skeggs
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_defines.h"
27 #include "util/u_inlines.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_format.h"
30 #include "util/u_surface.h"
32 #include "os/os_thread.h"
34 #include "nvc0/nvc0_context.h"
35 #include "nvc0/nvc0_resource.h"
37 #include "nv50/g80_defs.xml.h"
38 #include "nv50/g80_texture.xml.h"
40 /* these are used in nv50_blit.h */
41 #define NV50_ENG2D_SUPPORTED_FORMATS 0xff9ccfe1cce3ccc9ULL
42 #define NV50_ENG2D_NOCONVERT_FORMATS 0x009cc02000000000ULL
43 #define NV50_ENG2D_LUMINANCE_FORMATS 0x001cc02000000000ULL
44 #define NV50_ENG2D_INTENSITY_FORMATS 0x0080000000000000ULL
45 #define NV50_ENG2D_OPERATION_FORMATS 0x060001c000638000ULL
47 #define NOUVEAU_DRIVER 0xc0
48 #include "nv50/nv50_blit.h"
51 nvc0_2d_format(enum pipe_format format
, bool dst
, bool dst_src_equal
)
53 uint8_t id
= nvc0_format_table
[format
].rt
;
55 /* A8_UNORM is treated as I8_UNORM as far as the 2D engine is concerned. */
56 if (!dst
&& unlikely(format
== PIPE_FORMAT_I8_UNORM
) && !dst_src_equal
)
57 return G80_SURFACE_FORMAT_A8_UNORM
;
59 /* Hardware values for color formats range from 0xc0 to 0xff,
60 * but the 2D engine doesn't support all of them.
62 if (nv50_2d_format_supported(format
))
64 assert(dst_src_equal
);
66 switch (util_format_get_blocksize(format
)) {
68 return G80_SURFACE_FORMAT_R8_UNORM
;
70 return G80_SURFACE_FORMAT_RG8_UNORM
;
72 return G80_SURFACE_FORMAT_BGRA8_UNORM
;
74 return G80_SURFACE_FORMAT_RGBA16_UNORM
;
76 return G80_SURFACE_FORMAT_RGBA32_FLOAT
;
84 nvc0_2d_texture_set(struct nouveau_pushbuf
*push
, bool dst
,
85 struct nv50_miptree
*mt
, unsigned level
, unsigned layer
,
86 enum pipe_format pformat
, bool dst_src_pformat_equal
)
88 struct nouveau_bo
*bo
= mt
->base
.bo
;
89 uint32_t width
, height
, depth
;
91 uint32_t mthd
= dst
? NV50_2D_DST_FORMAT
: NV50_2D_SRC_FORMAT
;
92 uint32_t offset
= mt
->level
[level
].offset
;
94 format
= nvc0_2d_format(pformat
, dst
, dst_src_pformat_equal
);
96 NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
97 util_format_name(pformat
));
101 width
= u_minify(mt
->base
.base
.width0
, level
) << mt
->ms_x
;
102 height
= u_minify(mt
->base
.base
.height0
, level
) << mt
->ms_y
;
103 depth
= u_minify(mt
->base
.base
.depth0
, level
);
105 /* layer has to be < depth, and depth > tile depth / 2 */
107 if (!mt
->layout_3d
) {
108 offset
+= mt
->layer_stride
* layer
;
113 offset
+= nvc0_mt_zslice_offset(mt
, level
, layer
);
117 if (!nouveau_bo_memtype(bo
)) {
118 BEGIN_NVC0(push
, SUBC_2D(mthd
), 2);
119 PUSH_DATA (push
, format
);
121 BEGIN_NVC0(push
, SUBC_2D(mthd
+ 0x14), 5);
122 PUSH_DATA (push
, mt
->level
[level
].pitch
);
123 PUSH_DATA (push
, width
);
124 PUSH_DATA (push
, height
);
125 PUSH_DATAh(push
, bo
->offset
+ offset
);
126 PUSH_DATA (push
, bo
->offset
+ offset
);
128 BEGIN_NVC0(push
, SUBC_2D(mthd
), 5);
129 PUSH_DATA (push
, format
);
131 PUSH_DATA (push
, mt
->level
[level
].tile_mode
);
132 PUSH_DATA (push
, depth
);
133 PUSH_DATA (push
, layer
);
134 BEGIN_NVC0(push
, SUBC_2D(mthd
+ 0x18), 4);
135 PUSH_DATA (push
, width
);
136 PUSH_DATA (push
, height
);
137 PUSH_DATAh(push
, bo
->offset
+ offset
);
138 PUSH_DATA (push
, bo
->offset
+ offset
);
143 BEGIN_NVC0(push
, SUBC_2D(NVC0_2D_CLIP_X
), 4);
146 PUSH_DATA (push
, width
);
147 PUSH_DATA (push
, height
);
154 nvc0_2d_texture_do_copy(struct nouveau_pushbuf
*push
,
155 struct nv50_miptree
*dst
, unsigned dst_level
,
156 unsigned dx
, unsigned dy
, unsigned dz
,
157 struct nv50_miptree
*src
, unsigned src_level
,
158 unsigned sx
, unsigned sy
, unsigned sz
,
159 unsigned w
, unsigned h
)
161 const enum pipe_format dfmt
= dst
->base
.base
.format
;
162 const enum pipe_format sfmt
= src
->base
.base
.format
;
164 bool eqfmt
= dfmt
== sfmt
;
166 if (!PUSH_SPACE(push
, 2 * 16 + 32))
169 ret
= nvc0_2d_texture_set(push
, true, dst
, dst_level
, dz
, dfmt
, eqfmt
);
173 ret
= nvc0_2d_texture_set(push
, false, src
, src_level
, sz
, sfmt
, eqfmt
);
177 IMMED_NVC0(push
, NVC0_2D(BLIT_CONTROL
), 0x00);
178 BEGIN_NVC0(push
, NVC0_2D(BLIT_DST_X
), 4);
179 PUSH_DATA (push
, dx
<< dst
->ms_x
);
180 PUSH_DATA (push
, dy
<< dst
->ms_y
);
181 PUSH_DATA (push
, w
<< dst
->ms_x
);
182 PUSH_DATA (push
, h
<< dst
->ms_y
);
183 BEGIN_NVC0(push
, NVC0_2D(BLIT_DU_DX_FRACT
), 4);
188 BEGIN_NVC0(push
, NVC0_2D(BLIT_SRC_X_FRACT
), 4);
190 PUSH_DATA (push
, sx
<< src
->ms_x
);
192 PUSH_DATA (push
, sy
<< src
->ms_y
);
198 nvc0_resource_copy_region(struct pipe_context
*pipe
,
199 struct pipe_resource
*dst
, unsigned dst_level
,
200 unsigned dstx
, unsigned dsty
, unsigned dstz
,
201 struct pipe_resource
*src
, unsigned src_level
,
202 const struct pipe_box
*src_box
)
204 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
207 unsigned dst_layer
= dstz
, src_layer
= src_box
->z
;
209 if (dst
->target
== PIPE_BUFFER
&& src
->target
== PIPE_BUFFER
) {
210 nouveau_copy_buffer(&nvc0
->base
,
211 nv04_resource(dst
), dstx
,
212 nv04_resource(src
), src_box
->x
, src_box
->width
);
213 NOUVEAU_DRV_STAT(&nvc0
->screen
->base
, buf_copy_bytes
, src_box
->width
);
216 NOUVEAU_DRV_STAT(&nvc0
->screen
->base
, tex_copy_count
, 1);
218 /* 0 and 1 are equal, only supporting 0/1, 2, 4 and 8 */
219 assert((src
->nr_samples
| 1) == (dst
->nr_samples
| 1));
221 m2mf
= (src
->format
== dst
->format
) ||
222 (util_format_get_blocksizebits(src
->format
) ==
223 util_format_get_blocksizebits(dst
->format
));
225 nv04_resource(dst
)->status
|= NOUVEAU_BUFFER_STATUS_GPU_WRITING
;
228 struct nv50_miptree
*src_mt
= nv50_miptree(src
);
229 struct nv50_miptree
*dst_mt
= nv50_miptree(dst
);
230 struct nv50_m2mf_rect drect
, srect
;
232 unsigned nx
= util_format_get_nblocksx(src
->format
, src_box
->width
)
234 unsigned ny
= util_format_get_nblocksy(src
->format
, src_box
->height
)
237 nv50_m2mf_rect_setup(&drect
, dst
, dst_level
, dstx
, dsty
, dstz
);
238 nv50_m2mf_rect_setup(&srect
, src
, src_level
,
239 src_box
->x
, src_box
->y
, src_box
->z
);
241 for (i
= 0; i
< src_box
->depth
; ++i
) {
242 nvc0
->m2mf_copy_rect(nvc0
, &drect
, &srect
, nx
, ny
);
244 if (dst_mt
->layout_3d
)
247 drect
.base
+= dst_mt
->layer_stride
;
249 if (src_mt
->layout_3d
)
252 srect
.base
+= src_mt
->layer_stride
;
257 assert(nv50_2d_dst_format_faithful(dst
->format
));
258 assert(nv50_2d_src_format_faithful(src
->format
));
260 BCTX_REFN(nvc0
->bufctx
, 2D
, nv04_resource(src
), RD
);
261 BCTX_REFN(nvc0
->bufctx
, 2D
, nv04_resource(dst
), WR
);
262 nouveau_pushbuf_bufctx(nvc0
->base
.pushbuf
, nvc0
->bufctx
);
263 nouveau_pushbuf_validate(nvc0
->base
.pushbuf
);
265 for (; dst_layer
< dstz
+ src_box
->depth
; ++dst_layer
, ++src_layer
) {
266 ret
= nvc0_2d_texture_do_copy(nvc0
->base
.pushbuf
,
267 nv50_miptree(dst
), dst_level
,
268 dstx
, dsty
, dst_layer
,
269 nv50_miptree(src
), src_level
,
270 src_box
->x
, src_box
->y
, src_layer
,
271 src_box
->width
, src_box
->height
);
275 nouveau_bufctx_reset(nvc0
->bufctx
, 0);
279 nvc0_clear_render_target(struct pipe_context
*pipe
,
280 struct pipe_surface
*dst
,
281 const union pipe_color_union
*color
,
282 unsigned dstx
, unsigned dsty
,
283 unsigned width
, unsigned height
)
285 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
286 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
287 struct nv50_surface
*sf
= nv50_surface(dst
);
288 struct nv04_resource
*res
= nv04_resource(sf
->base
.texture
);
291 assert(dst
->texture
->target
!= PIPE_BUFFER
);
293 if (!PUSH_SPACE(push
, 32 + sf
->depth
))
296 PUSH_REFN (push
, res
->bo
, res
->domain
| NOUVEAU_BO_WR
);
298 BEGIN_NVC0(push
, NVC0_3D(CLEAR_COLOR(0)), 4);
299 PUSH_DATAf(push
, color
->f
[0]);
300 PUSH_DATAf(push
, color
->f
[1]);
301 PUSH_DATAf(push
, color
->f
[2]);
302 PUSH_DATAf(push
, color
->f
[3]);
304 BEGIN_NVC0(push
, NVC0_3D(SCREEN_SCISSOR_HORIZ
), 2);
305 PUSH_DATA (push
, ( width
<< 16) | dstx
);
306 PUSH_DATA (push
, (height
<< 16) | dsty
);
308 BEGIN_NVC0(push
, NVC0_3D(RT_CONTROL
), 1);
310 BEGIN_NVC0(push
, NVC0_3D(RT_ADDRESS_HIGH(0)), 9);
311 PUSH_DATAh(push
, res
->address
+ sf
->offset
);
312 PUSH_DATA (push
, res
->address
+ sf
->offset
);
313 if (likely(nouveau_bo_memtype(res
->bo
))) {
314 struct nv50_miptree
*mt
= nv50_miptree(dst
->texture
);
316 PUSH_DATA(push
, sf
->width
);
317 PUSH_DATA(push
, sf
->height
);
318 PUSH_DATA(push
, nvc0_format_table
[dst
->format
].rt
);
319 PUSH_DATA(push
, (mt
->layout_3d
<< 16) |
320 mt
->level
[sf
->base
.u
.tex
.level
].tile_mode
);
321 PUSH_DATA(push
, dst
->u
.tex
.first_layer
+ sf
->depth
);
322 PUSH_DATA(push
, mt
->layer_stride
>> 2);
323 PUSH_DATA(push
, dst
->u
.tex
.first_layer
);
324 IMMED_NVC0(push
, NVC0_3D(MULTISAMPLE_MODE
), mt
->ms_mode
);
326 if (res
->base
.target
== PIPE_BUFFER
) {
327 PUSH_DATA(push
, 262144);
330 PUSH_DATA(push
, nv50_miptree(&res
->base
)->level
[0].pitch
);
331 PUSH_DATA(push
, sf
->height
);
333 PUSH_DATA(push
, nvc0_format_table
[sf
->base
.format
].rt
);
334 PUSH_DATA(push
, 1 << 12);
339 IMMED_NVC0(push
, NVC0_3D(ZETA_ENABLE
), 0);
340 IMMED_NVC0(push
, NVC0_3D(MULTISAMPLE_MODE
), 0);
342 /* tiled textures don't have to be fenced, they're not mapped directly */
343 nvc0_resource_fence(res
, NOUVEAU_BO_WR
);
346 IMMED_NVC0(push
, NVC0_3D(COND_MODE
), NVC0_3D_COND_MODE_ALWAYS
);
348 BEGIN_NIC0(push
, NVC0_3D(CLEAR_BUFFERS
), sf
->depth
);
349 for (z
= 0; z
< sf
->depth
; ++z
) {
350 PUSH_DATA (push
, 0x3c |
351 (z
<< NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT
));
354 IMMED_NVC0(push
, NVC0_3D(COND_MODE
), nvc0
->cond_condmode
);
356 nvc0
->dirty_3d
|= NVC0_NEW_3D_FRAMEBUFFER
;
360 nvc0_clear_buffer_push_nvc0(struct pipe_context
*pipe
,
361 struct pipe_resource
*res
,
362 unsigned offset
, unsigned size
,
363 const void *data
, int data_size
)
365 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
366 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
367 struct nv04_resource
*buf
= nv04_resource(res
);
370 nouveau_bufctx_refn(nvc0
->bufctx
, 0, buf
->bo
, buf
->domain
| NOUVEAU_BO_WR
);
371 nouveau_pushbuf_bufctx(push
, nvc0
->bufctx
);
372 nouveau_pushbuf_validate(push
);
374 unsigned count
= (size
+ 3) / 4;
375 unsigned data_words
= data_size
/ 4;
378 unsigned nr_data
= MIN2(count
, NV04_PFIFO_MAX_PACKET_LEN
) / data_words
;
379 unsigned nr
= nr_data
* data_words
;
381 if (!PUSH_SPACE(push
, nr
+ 9))
384 BEGIN_NVC0(push
, NVC0_M2MF(OFFSET_OUT_HIGH
), 2);
385 PUSH_DATAh(push
, buf
->address
+ offset
);
386 PUSH_DATA (push
, buf
->address
+ offset
);
387 BEGIN_NVC0(push
, NVC0_M2MF(LINE_LENGTH_IN
), 2);
388 PUSH_DATA (push
, MIN2(size
, nr
* 4));
390 BEGIN_NVC0(push
, NVC0_M2MF(EXEC
), 1);
391 PUSH_DATA (push
, 0x100111);
393 /* must not be interrupted (trap on QUERY fence, 0x50 works however) */
394 BEGIN_NIC0(push
, NVC0_M2MF(DATA
), nr
);
395 for (i
= 0; i
< nr_data
; i
++)
396 PUSH_DATAp(push
, data
, data_words
);
404 nouveau_fence_ref(nvc0
->screen
->base
.fence
.current
, &buf
->fence
);
405 nouveau_fence_ref(nvc0
->screen
->base
.fence
.current
, &buf
->fence_wr
);
408 nouveau_bufctx_reset(nvc0
->bufctx
, 0);
412 nvc0_clear_buffer_push_nve4(struct pipe_context
*pipe
,
413 struct pipe_resource
*res
,
414 unsigned offset
, unsigned size
,
415 const void *data
, int data_size
)
417 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
418 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
419 struct nv04_resource
*buf
= nv04_resource(res
);
422 nouveau_bufctx_refn(nvc0
->bufctx
, 0, buf
->bo
, buf
->domain
| NOUVEAU_BO_WR
);
423 nouveau_pushbuf_bufctx(push
, nvc0
->bufctx
);
424 nouveau_pushbuf_validate(push
);
426 unsigned count
= (size
+ 3) / 4;
427 unsigned data_words
= data_size
/ 4;
430 unsigned nr_data
= MIN2(count
, NV04_PFIFO_MAX_PACKET_LEN
) / data_words
;
431 unsigned nr
= nr_data
* data_words
;
433 if (!PUSH_SPACE(push
, nr
+ 10))
436 BEGIN_NVC0(push
, NVE4_P2MF(UPLOAD_DST_ADDRESS_HIGH
), 2);
437 PUSH_DATAh(push
, buf
->address
+ offset
);
438 PUSH_DATA (push
, buf
->address
+ offset
);
439 BEGIN_NVC0(push
, NVE4_P2MF(UPLOAD_LINE_LENGTH_IN
), 2);
440 PUSH_DATA (push
, MIN2(size
, nr
* 4));
442 /* must not be interrupted (trap on QUERY fence, 0x50 works however) */
443 BEGIN_1IC0(push
, NVE4_P2MF(UPLOAD_EXEC
), nr
+ 1);
444 PUSH_DATA (push
, 0x1001);
445 for (i
= 0; i
< nr_data
; i
++)
446 PUSH_DATAp(push
, data
, data_words
);
454 nouveau_fence_ref(nvc0
->screen
->base
.fence
.current
, &buf
->fence
);
455 nouveau_fence_ref(nvc0
->screen
->base
.fence
.current
, &buf
->fence_wr
);
458 nouveau_bufctx_reset(nvc0
->bufctx
, 0);
462 nvc0_clear_buffer_push(struct pipe_context
*pipe
,
463 struct pipe_resource
*res
,
464 unsigned offset
, unsigned size
,
465 const void *data
, int data_size
)
467 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
470 if (data_size
== 1) {
471 tmp
= *(unsigned char *)data
;
472 tmp
= (tmp
<< 24) | (tmp
<< 16) | (tmp
<< 8) | tmp
;
475 } else if (data_size
== 2) {
476 tmp
= *(unsigned short *)data
;
477 tmp
= (tmp
<< 16) | tmp
;
482 if (nvc0
->screen
->base
.class_3d
< NVE4_3D_CLASS
)
483 nvc0_clear_buffer_push_nvc0(pipe
, res
, offset
, size
, data
, data_size
);
485 nvc0_clear_buffer_push_nve4(pipe
, res
, offset
, size
, data
, data_size
);
489 nvc0_clear_buffer(struct pipe_context
*pipe
,
490 struct pipe_resource
*res
,
491 unsigned offset
, unsigned size
,
492 const void *data
, int data_size
)
494 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
495 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
496 struct nv04_resource
*buf
= nv04_resource(res
);
497 union pipe_color_union color
;
498 enum pipe_format dst_fmt
;
499 unsigned width
, height
, elements
;
501 assert(res
->target
== PIPE_BUFFER
);
502 assert(nouveau_bo_memtype(buf
->bo
) == 0);
506 dst_fmt
= PIPE_FORMAT_R32G32B32A32_UINT
;
507 memcpy(&color
.ui
, data
, 16);
510 /* RGB32 is not a valid RT format. This will be handled by the pushbuf
515 dst_fmt
= PIPE_FORMAT_R32G32_UINT
;
516 memcpy(&color
.ui
, data
, 8);
517 memset(&color
.ui
[2], 0, 8);
520 dst_fmt
= PIPE_FORMAT_R32_UINT
;
521 memcpy(&color
.ui
, data
, 4);
522 memset(&color
.ui
[1], 0, 12);
525 dst_fmt
= PIPE_FORMAT_R16_UINT
;
526 color
.ui
[0] = util_cpu_to_le32(
527 util_le16_to_cpu(*(unsigned short *)data
));
528 memset(&color
.ui
[1], 0, 12);
531 dst_fmt
= PIPE_FORMAT_R8_UINT
;
532 color
.ui
[0] = util_cpu_to_le32(*(unsigned char *)data
);
533 memset(&color
.ui
[1], 0, 12);
536 assert(!"Unsupported element size");
540 assert(size
% data_size
== 0);
542 if (data_size
== 12) {
543 nvc0_clear_buffer_push(pipe
, res
, offset
, size
, data
, data_size
);
548 unsigned fixup_size
= MIN2(size
, align(offset
, 0x100) - offset
);
549 assert(fixup_size
% data_size
== 0);
550 nvc0_clear_buffer_push(pipe
, res
, offset
, fixup_size
, data
, data_size
);
551 offset
+= fixup_size
;
557 elements
= size
/ data_size
;
558 height
= (elements
+ 16383) / 16384;
559 width
= elements
/ height
;
564 if (!PUSH_SPACE(push
, 40))
567 PUSH_REFN (push
, buf
->bo
, buf
->domain
| NOUVEAU_BO_WR
);
569 BEGIN_NVC0(push
, NVC0_3D(CLEAR_COLOR(0)), 4);
570 PUSH_DATAf(push
, color
.f
[0]);
571 PUSH_DATAf(push
, color
.f
[1]);
572 PUSH_DATAf(push
, color
.f
[2]);
573 PUSH_DATAf(push
, color
.f
[3]);
574 BEGIN_NVC0(push
, NVC0_3D(SCREEN_SCISSOR_HORIZ
), 2);
575 PUSH_DATA (push
, width
<< 16);
576 PUSH_DATA (push
, height
<< 16);
578 IMMED_NVC0(push
, NVC0_3D(RT_CONTROL
), 1);
580 BEGIN_NVC0(push
, NVC0_3D(RT_ADDRESS_HIGH(0)), 9);
581 PUSH_DATAh(push
, buf
->address
+ offset
);
582 PUSH_DATA (push
, buf
->address
+ offset
);
583 PUSH_DATA (push
, align(width
* data_size
, 0x100));
584 PUSH_DATA (push
, height
);
585 PUSH_DATA (push
, nvc0_format_table
[dst_fmt
].rt
);
586 PUSH_DATA (push
, NVC0_3D_RT_TILE_MODE_LINEAR
);
591 IMMED_NVC0(push
, NVC0_3D(ZETA_ENABLE
), 0);
592 IMMED_NVC0(push
, NVC0_3D(MULTISAMPLE_MODE
), 0);
594 IMMED_NVC0(push
, NVC0_3D(COND_MODE
), NVC0_3D_COND_MODE_ALWAYS
);
596 IMMED_NVC0(push
, NVC0_3D(CLEAR_BUFFERS
), 0x3c);
598 IMMED_NVC0(push
, NVC0_3D(COND_MODE
), nvc0
->cond_condmode
);
601 nouveau_fence_ref(nvc0
->screen
->base
.fence
.current
, &buf
->fence
);
602 nouveau_fence_ref(nvc0
->screen
->base
.fence
.current
, &buf
->fence_wr
);
605 if (width
* height
!= elements
) {
606 offset
+= width
* height
* data_size
;
607 width
= elements
- width
* height
;
608 nvc0_clear_buffer_push(pipe
, res
, offset
, width
* data_size
,
612 nvc0
->dirty_3d
|= NVC0_NEW_3D_FRAMEBUFFER
;
616 nvc0_clear_depth_stencil(struct pipe_context
*pipe
,
617 struct pipe_surface
*dst
,
618 unsigned clear_flags
,
621 unsigned dstx
, unsigned dsty
,
622 unsigned width
, unsigned height
)
624 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
625 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
626 struct nv50_miptree
*mt
= nv50_miptree(dst
->texture
);
627 struct nv50_surface
*sf
= nv50_surface(dst
);
629 int unk
= mt
->base
.base
.target
== PIPE_TEXTURE_2D
;
632 assert(dst
->texture
->target
!= PIPE_BUFFER
);
634 if (!PUSH_SPACE(push
, 32 + sf
->depth
))
637 PUSH_REFN (push
, mt
->base
.bo
, mt
->base
.domain
| NOUVEAU_BO_WR
);
639 if (clear_flags
& PIPE_CLEAR_DEPTH
) {
640 BEGIN_NVC0(push
, NVC0_3D(CLEAR_DEPTH
), 1);
641 PUSH_DATAf(push
, depth
);
642 mode
|= NVC0_3D_CLEAR_BUFFERS_Z
;
645 if (clear_flags
& PIPE_CLEAR_STENCIL
) {
646 BEGIN_NVC0(push
, NVC0_3D(CLEAR_STENCIL
), 1);
647 PUSH_DATA (push
, stencil
& 0xff);
648 mode
|= NVC0_3D_CLEAR_BUFFERS_S
;
651 BEGIN_NVC0(push
, NVC0_3D(SCREEN_SCISSOR_HORIZ
), 2);
652 PUSH_DATA (push
, ( width
<< 16) | dstx
);
653 PUSH_DATA (push
, (height
<< 16) | dsty
);
655 BEGIN_NVC0(push
, NVC0_3D(ZETA_ADDRESS_HIGH
), 5);
656 PUSH_DATAh(push
, mt
->base
.address
+ sf
->offset
);
657 PUSH_DATA (push
, mt
->base
.address
+ sf
->offset
);
658 PUSH_DATA (push
, nvc0_format_table
[dst
->format
].rt
);
659 PUSH_DATA (push
, mt
->level
[sf
->base
.u
.tex
.level
].tile_mode
);
660 PUSH_DATA (push
, mt
->layer_stride
>> 2);
661 BEGIN_NVC0(push
, NVC0_3D(ZETA_ENABLE
), 1);
663 BEGIN_NVC0(push
, NVC0_3D(ZETA_HORIZ
), 3);
664 PUSH_DATA (push
, sf
->width
);
665 PUSH_DATA (push
, sf
->height
);
666 PUSH_DATA (push
, (unk
<< 16) | (dst
->u
.tex
.first_layer
+ sf
->depth
));
667 BEGIN_NVC0(push
, NVC0_3D(ZETA_BASE_LAYER
), 1);
668 PUSH_DATA (push
, dst
->u
.tex
.first_layer
);
669 IMMED_NVC0(push
, NVC0_3D(MULTISAMPLE_MODE
), mt
->ms_mode
);
671 IMMED_NVC0(push
, NVC0_3D(COND_MODE
), NVC0_3D_COND_MODE_ALWAYS
);
673 BEGIN_NIC0(push
, NVC0_3D(CLEAR_BUFFERS
), sf
->depth
);
674 for (z
= 0; z
< sf
->depth
; ++z
) {
675 PUSH_DATA (push
, mode
|
676 (z
<< NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT
));
679 IMMED_NVC0(push
, NVC0_3D(COND_MODE
), nvc0
->cond_condmode
);
681 nvc0
->dirty_3d
|= NVC0_NEW_3D_FRAMEBUFFER
;
685 nvc0_clear(struct pipe_context
*pipe
, unsigned buffers
,
686 const union pipe_color_union
*color
,
687 double depth
, unsigned stencil
)
689 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
690 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
691 struct pipe_framebuffer_state
*fb
= &nvc0
->framebuffer
;
695 /* don't need NEW_BLEND, COLOR_MASK doesn't affect CLEAR_BUFFERS */
696 if (!nvc0_state_validate_3d(nvc0
, NVC0_NEW_3D_FRAMEBUFFER
))
699 if (buffers
& PIPE_CLEAR_COLOR
&& fb
->nr_cbufs
) {
700 BEGIN_NVC0(push
, NVC0_3D(CLEAR_COLOR(0)), 4);
701 PUSH_DATAf(push
, color
->f
[0]);
702 PUSH_DATAf(push
, color
->f
[1]);
703 PUSH_DATAf(push
, color
->f
[2]);
704 PUSH_DATAf(push
, color
->f
[3]);
705 if (buffers
& PIPE_CLEAR_COLOR0
)
707 NVC0_3D_CLEAR_BUFFERS_R
| NVC0_3D_CLEAR_BUFFERS_G
|
708 NVC0_3D_CLEAR_BUFFERS_B
| NVC0_3D_CLEAR_BUFFERS_A
;
711 if (buffers
& PIPE_CLEAR_DEPTH
) {
712 BEGIN_NVC0(push
, NVC0_3D(CLEAR_DEPTH
), 1);
713 PUSH_DATA (push
, fui(depth
));
714 mode
|= NVC0_3D_CLEAR_BUFFERS_Z
;
717 if (buffers
& PIPE_CLEAR_STENCIL
) {
718 BEGIN_NVC0(push
, NVC0_3D(CLEAR_STENCIL
), 1);
719 PUSH_DATA (push
, stencil
& 0xff);
720 mode
|= NVC0_3D_CLEAR_BUFFERS_S
;
724 int zs_layers
= 0, color0_layers
= 0;
725 if (fb
->cbufs
[0] && (mode
& 0x3c))
726 color0_layers
= fb
->cbufs
[0]->u
.tex
.last_layer
-
727 fb
->cbufs
[0]->u
.tex
.first_layer
+ 1;
728 if (fb
->zsbuf
&& (mode
& ~0x3c))
729 zs_layers
= fb
->zsbuf
->u
.tex
.last_layer
-
730 fb
->zsbuf
->u
.tex
.first_layer
+ 1;
732 for (j
= 0; j
< MIN2(zs_layers
, color0_layers
); j
++) {
733 BEGIN_NVC0(push
, NVC0_3D(CLEAR_BUFFERS
), 1);
734 PUSH_DATA(push
, mode
| (j
<< NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT
));
736 for (k
= j
; k
< zs_layers
; k
++) {
737 BEGIN_NVC0(push
, NVC0_3D(CLEAR_BUFFERS
), 1);
738 PUSH_DATA(push
, (mode
& ~0x3c) | (k
<< NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT
));
740 for (k
= j
; k
< color0_layers
; k
++) {
741 BEGIN_NVC0(push
, NVC0_3D(CLEAR_BUFFERS
), 1);
742 PUSH_DATA(push
, (mode
& 0x3c) | (k
<< NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT
));
746 for (i
= 1; i
< fb
->nr_cbufs
; i
++) {
747 struct pipe_surface
*sf
= fb
->cbufs
[i
];
748 if (!sf
|| !(buffers
& (PIPE_CLEAR_COLOR0
<< i
)))
750 for (j
= 0; j
<= sf
->u
.tex
.last_layer
- sf
->u
.tex
.first_layer
; j
++) {
751 BEGIN_NVC0(push
, NVC0_3D(CLEAR_BUFFERS
), 1);
752 PUSH_DATA (push
, (i
<< 6) | 0x3c |
753 (j
<< NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT
));
759 /* =============================== BLIT CODE ===================================
764 struct nvc0_program
*fp
[NV50_BLIT_MAX_TEXTURE_TYPES
][NV50_BLIT_MODES
];
765 struct nvc0_program vp
;
767 struct nv50_tsc_entry sampler
[2]; /* nearest, bilinear */
771 struct nvc0_screen
*screen
;
776 struct nvc0_context
*nvc0
;
777 struct nvc0_program
*fp
;
781 uint8_t render_condition_enable
;
782 enum pipe_texture_target target
;
784 struct pipe_framebuffer_state fb
;
785 struct nvc0_rasterizer_stateobj
*rast
;
786 struct nvc0_program
*vp
;
787 struct nvc0_program
*tcp
;
788 struct nvc0_program
*tep
;
789 struct nvc0_program
*gp
;
790 struct nvc0_program
*fp
;
791 unsigned num_textures
[5];
792 unsigned num_samplers
[5];
793 struct pipe_sampler_view
*texture
[2];
794 struct nv50_tsc_entry
*sampler
[2];
795 unsigned min_samples
;
798 struct nvc0_rasterizer_stateobj rast
;
802 nvc0_blitter_make_vp(struct nvc0_blitter
*blit
)
804 static const uint32_t code_nvc0
[] =
806 0xfff11c26, 0x06000080, /* vfetch b64 $r4:$r5 a[0x80] */
807 0xfff01c46, 0x06000090, /* vfetch b96 $r0:$r1:$r2 a[0x90] */
808 0x13f01c26, 0x0a7e0070, /* export b64 o[0x70] $r4:$r5 */
809 0x03f01c46, 0x0a7e0080, /* export b96 o[0x80] $r0:$r1:$r2 */
810 0x00001de7, 0x80000000, /* exit */
812 static const uint32_t code_nve4
[] =
814 0x00000007, 0x20000000, /* sched */
815 0xfff11c26, 0x06000080, /* vfetch b64 $r4:$r5 a[0x80] */
816 0xfff01c46, 0x06000090, /* vfetch b96 $r0:$r1:$r2 a[0x90] */
817 0x13f01c26, 0x0a7e0070, /* export b64 o[0x70] $r4:$r5 */
818 0x03f01c46, 0x0a7e0080, /* export b96 o[0x80] $r0:$r1:$r2 */
819 0x00001de7, 0x80000000, /* exit */
821 static const uint32_t code_gk110
[] =
823 0x00000000, 0x08000000, /* sched */
824 0x401ffc12, 0x7ec7fc00, /* ld b64 $r4d a[0x80] 0x0 0x0 */
825 0x481ffc02, 0x7ecbfc00, /* ld b96 $r0t a[0x90] 0x0 0x0 */
826 0x381ffc12, 0x7f07fc00, /* st b64 a[0x70] $r4d 0x0 0x0 */
827 0x401ffc02, 0x7f0bfc00, /* st b96 a[0x80] $r0t 0x0 0x0 */
828 0x001c003c, 0x18000000, /* exit */
830 static const uint32_t code_gm107
[] =
832 0xfc0007e0, 0x001f8000, /* sched 0x7e0 0x7e0 0x7e0 */
833 0x0807ff04, 0xefd8ff80, /* ld b64 $r4 a[0x80] 0x0 */
834 0x0907ff00, 0xefd97f80, /* ld b96 $r0 a[0x90] 0x0 */
835 0x0707ff04, 0xeff0ff80, /* st b64 a[0x70] $r4 0x0 */
836 0xfc0007e0, 0x00000000, /* sched 0x7e0 0x7e0 0x0 */
837 0x0807ff00, 0xeff17f80, /* st b96 a[0x80] $r0 0x0 */
838 0x0007000f, 0xe3000000, /* exit */
841 blit
->vp
.type
= PIPE_SHADER_VERTEX
;
842 blit
->vp
.translated
= true;
843 if (blit
->screen
->base
.class_3d
>= GM107_3D_CLASS
) {
844 blit
->vp
.code
= (uint32_t *)code_gm107
; /* const_cast */
845 blit
->vp
.code_size
= sizeof(code_gm107
);
847 if (blit
->screen
->base
.class_3d
>= NVF0_3D_CLASS
) {
848 blit
->vp
.code
= (uint32_t *)code_gk110
; /* const_cast */
849 blit
->vp
.code_size
= sizeof(code_gk110
);
851 if (blit
->screen
->base
.class_3d
>= NVE4_3D_CLASS
) {
852 blit
->vp
.code
= (uint32_t *)code_nve4
; /* const_cast */
853 blit
->vp
.code_size
= sizeof(code_nve4
);
855 blit
->vp
.code
= (uint32_t *)code_nvc0
; /* const_cast */
856 blit
->vp
.code_size
= sizeof(code_nvc0
);
858 blit
->vp
.num_gprs
= 6;
859 blit
->vp
.vp
.edgeflag
= PIPE_MAX_ATTRIBS
;
861 blit
->vp
.hdr
[0] = 0x00020461; /* vertprog magic */
862 blit
->vp
.hdr
[4] = 0x000ff000; /* no outputs read */
863 blit
->vp
.hdr
[6] = 0x00000073; /* a[0x80].xy, a[0x90].xyz */
864 blit
->vp
.hdr
[13] = 0x00073000; /* o[0x70].xy, o[0x80].xyz */
868 nvc0_blitter_make_sampler(struct nvc0_blitter
*blit
)
870 /* clamp to edge, min/max lod = 0, nearest filtering */
872 blit
->sampler
[0].id
= -1;
874 blit
->sampler
[0].tsc
[0] = G80_TSC_0_SRGB_CONVERSION
|
875 (G80_TSC_WRAP_CLAMP_TO_EDGE
<< G80_TSC_0_ADDRESS_U__SHIFT
) |
876 (G80_TSC_WRAP_CLAMP_TO_EDGE
<< G80_TSC_0_ADDRESS_V__SHIFT
) |
877 (G80_TSC_WRAP_CLAMP_TO_EDGE
<< G80_TSC_0_ADDRESS_P__SHIFT
);
878 blit
->sampler
[0].tsc
[1] =
879 G80_TSC_1_MAG_FILTER_NEAREST
|
880 G80_TSC_1_MIN_FILTER_NEAREST
|
881 G80_TSC_1_MIP_FILTER_NONE
;
883 /* clamp to edge, min/max lod = 0, bilinear filtering */
885 blit
->sampler
[1].id
= -1;
887 blit
->sampler
[1].tsc
[0] = blit
->sampler
[0].tsc
[0];
888 blit
->sampler
[1].tsc
[1] =
889 G80_TSC_1_MAG_FILTER_LINEAR
|
890 G80_TSC_1_MIN_FILTER_LINEAR
|
891 G80_TSC_1_MIP_FILTER_NONE
;
895 nvc0_blit_select_fp(struct nvc0_blitctx
*ctx
, const struct pipe_blit_info
*info
)
897 struct nvc0_blitter
*blitter
= ctx
->nvc0
->screen
->blitter
;
899 const enum pipe_texture_target ptarg
=
900 nv50_blit_reinterpret_pipe_texture_target(info
->src
.resource
->target
);
902 const unsigned targ
= nv50_blit_texture_type(ptarg
);
903 const unsigned mode
= ctx
->mode
;
905 if (!blitter
->fp
[targ
][mode
]) {
906 pipe_mutex_lock(blitter
->mutex
);
907 if (!blitter
->fp
[targ
][mode
])
908 blitter
->fp
[targ
][mode
] =
909 nv50_blitter_make_fp(&ctx
->nvc0
->base
.pipe
, mode
, ptarg
);
910 pipe_mutex_unlock(blitter
->mutex
);
912 ctx
->fp
= blitter
->fp
[targ
][mode
];
916 nvc0_blit_set_dst(struct nvc0_blitctx
*ctx
,
917 struct pipe_resource
*res
, unsigned level
, unsigned layer
,
918 enum pipe_format format
)
920 struct nvc0_context
*nvc0
= ctx
->nvc0
;
921 struct pipe_context
*pipe
= &nvc0
->base
.pipe
;
922 struct pipe_surface templ
;
924 if (util_format_is_depth_or_stencil(format
))
925 templ
.format
= nv50_blit_zeta_to_colour_format(format
);
927 templ
.format
= format
;
929 templ
.u
.tex
.level
= level
;
930 templ
.u
.tex
.first_layer
= templ
.u
.tex
.last_layer
= layer
;
933 templ
.u
.tex
.first_layer
= 0;
934 templ
.u
.tex
.last_layer
=
935 (res
->target
== PIPE_TEXTURE_3D
? res
->depth0
: res
->array_size
) - 1;
938 nvc0
->framebuffer
.cbufs
[0] = nvc0_miptree_surface_new(pipe
, res
, &templ
);
939 nvc0
->framebuffer
.nr_cbufs
= 1;
940 nvc0
->framebuffer
.zsbuf
= NULL
;
941 nvc0
->framebuffer
.width
= nvc0
->framebuffer
.cbufs
[0]->width
;
942 nvc0
->framebuffer
.height
= nvc0
->framebuffer
.cbufs
[0]->height
;
946 nvc0_blit_set_src(struct nvc0_blitctx
*ctx
,
947 struct pipe_resource
*res
, unsigned level
, unsigned layer
,
948 enum pipe_format format
, const uint8_t filter
)
950 struct nvc0_context
*nvc0
= ctx
->nvc0
;
951 struct pipe_context
*pipe
= &nvc0
->base
.pipe
;
952 struct pipe_sampler_view templ
;
955 enum pipe_texture_target target
;
957 target
= nv50_blit_reinterpret_pipe_texture_target(res
->target
);
959 templ
.format
= format
;
960 templ
.u
.tex
.first_layer
= templ
.u
.tex
.last_layer
= layer
;
961 templ
.u
.tex
.first_level
= templ
.u
.tex
.last_level
= level
;
962 templ
.swizzle_r
= PIPE_SWIZZLE_RED
;
963 templ
.swizzle_g
= PIPE_SWIZZLE_GREEN
;
964 templ
.swizzle_b
= PIPE_SWIZZLE_BLUE
;
965 templ
.swizzle_a
= PIPE_SWIZZLE_ALPHA
;
968 templ
.u
.tex
.first_layer
= 0;
969 templ
.u
.tex
.last_layer
=
970 (res
->target
== PIPE_TEXTURE_3D
? res
->depth0
: res
->array_size
) - 1;
973 flags
= res
->last_level
? 0 : NV50_TEXVIEW_SCALED_COORDS
;
974 flags
|= NV50_TEXVIEW_ACCESS_RESOLVE
;
975 if (filter
&& res
->nr_samples
== 8)
976 flags
|= NV50_TEXVIEW_FILTER_MSAA8
;
978 nvc0
->textures
[4][0] = nvc0_create_texture_view(
979 pipe
, res
, &templ
, flags
, target
);
980 nvc0
->textures
[4][1] = NULL
;
982 for (s
= 0; s
<= 3; ++s
)
983 nvc0
->num_textures
[s
] = 0;
984 nvc0
->num_textures
[4] = 1;
986 templ
.format
= nv50_zs_to_s_format(format
);
987 if (templ
.format
!= format
) {
988 nvc0
->textures
[4][1] = nvc0_create_texture_view(
989 pipe
, res
, &templ
, flags
, target
);
990 nvc0
->num_textures
[4] = 2;
995 nvc0_blitctx_prepare_state(struct nvc0_blitctx
*blit
)
997 struct nouveau_pushbuf
*push
= blit
->nvc0
->base
.pushbuf
;
999 /* TODO: maybe make this a MACRO (if we need more logic) ? */
1001 if (blit
->nvc0
->cond_query
&& !blit
->render_condition_enable
)
1002 IMMED_NVC0(push
, NVC0_3D(COND_MODE
), NVC0_3D_COND_MODE_ALWAYS
);
1005 BEGIN_NVC0(push
, NVC0_3D(COLOR_MASK(0)), 1);
1006 PUSH_DATA (push
, blit
->color_mask
);
1007 IMMED_NVC0(push
, NVC0_3D(BLEND_ENABLE(0)), 0);
1008 IMMED_NVC0(push
, NVC0_3D(LOGIC_OP_ENABLE
), 0);
1010 /* rasterizer state */
1011 IMMED_NVC0(push
, NVC0_3D(FRAG_COLOR_CLAMP_EN
), 0);
1012 IMMED_NVC0(push
, NVC0_3D(MULTISAMPLE_ENABLE
), 0);
1013 BEGIN_NVC0(push
, NVC0_3D(MSAA_MASK(0)), 4);
1014 PUSH_DATA (push
, 0xffff);
1015 PUSH_DATA (push
, 0xffff);
1016 PUSH_DATA (push
, 0xffff);
1017 PUSH_DATA (push
, 0xffff);
1018 BEGIN_NVC0(push
, NVC0_3D(MACRO_POLYGON_MODE_FRONT
), 1);
1019 PUSH_DATA (push
, NVC0_3D_MACRO_POLYGON_MODE_FRONT_FILL
);
1020 BEGIN_NVC0(push
, NVC0_3D(MACRO_POLYGON_MODE_BACK
), 1);
1021 PUSH_DATA (push
, NVC0_3D_MACRO_POLYGON_MODE_BACK_FILL
);
1022 IMMED_NVC0(push
, NVC0_3D(POLYGON_SMOOTH_ENABLE
), 0);
1023 IMMED_NVC0(push
, NVC0_3D(POLYGON_OFFSET_FILL_ENABLE
), 0);
1024 IMMED_NVC0(push
, NVC0_3D(POLYGON_STIPPLE_ENABLE
), 0);
1025 IMMED_NVC0(push
, NVC0_3D(CULL_FACE_ENABLE
), 0);
1028 IMMED_NVC0(push
, NVC0_3D(DEPTH_TEST_ENABLE
), 0);
1029 IMMED_NVC0(push
, NVC0_3D(DEPTH_BOUNDS_EN
), 0);
1030 IMMED_NVC0(push
, NVC0_3D(STENCIL_ENABLE
), 0);
1031 IMMED_NVC0(push
, NVC0_3D(ALPHA_TEST_ENABLE
), 0);
1033 /* disable transform feedback */
1034 IMMED_NVC0(push
, NVC0_3D(TFB_ENABLE
), 0);
1038 nvc0_blitctx_pre_blit(struct nvc0_blitctx
*ctx
)
1040 struct nvc0_context
*nvc0
= ctx
->nvc0
;
1041 struct nvc0_blitter
*blitter
= nvc0
->screen
->blitter
;
1044 ctx
->saved
.fb
.width
= nvc0
->framebuffer
.width
;
1045 ctx
->saved
.fb
.height
= nvc0
->framebuffer
.height
;
1046 ctx
->saved
.fb
.samples
= nvc0
->framebuffer
.samples
;
1047 ctx
->saved
.fb
.layers
= nvc0
->framebuffer
.layers
;
1048 ctx
->saved
.fb
.nr_cbufs
= nvc0
->framebuffer
.nr_cbufs
;
1049 ctx
->saved
.fb
.cbufs
[0] = nvc0
->framebuffer
.cbufs
[0];
1050 ctx
->saved
.fb
.zsbuf
= nvc0
->framebuffer
.zsbuf
;
1052 ctx
->saved
.rast
= nvc0
->rast
;
1054 ctx
->saved
.vp
= nvc0
->vertprog
;
1055 ctx
->saved
.tcp
= nvc0
->tctlprog
;
1056 ctx
->saved
.tep
= nvc0
->tevlprog
;
1057 ctx
->saved
.gp
= nvc0
->gmtyprog
;
1058 ctx
->saved
.fp
= nvc0
->fragprog
;
1060 ctx
->saved
.min_samples
= nvc0
->min_samples
;
1062 nvc0
->rast
= &ctx
->rast
;
1064 nvc0
->vertprog
= &blitter
->vp
;
1065 nvc0
->tctlprog
= NULL
;
1066 nvc0
->tevlprog
= NULL
;
1067 nvc0
->gmtyprog
= NULL
;
1068 nvc0
->fragprog
= ctx
->fp
;
1070 for (s
= 0; s
<= 4; ++s
) {
1071 ctx
->saved
.num_textures
[s
] = nvc0
->num_textures
[s
];
1072 ctx
->saved
.num_samplers
[s
] = nvc0
->num_samplers
[s
];
1073 nvc0
->textures_dirty
[s
] = (1 << nvc0
->num_textures
[s
]) - 1;
1074 nvc0
->samplers_dirty
[s
] = (1 << nvc0
->num_samplers
[s
]) - 1;
1076 ctx
->saved
.texture
[0] = nvc0
->textures
[4][0];
1077 ctx
->saved
.texture
[1] = nvc0
->textures
[4][1];
1078 ctx
->saved
.sampler
[0] = nvc0
->samplers
[4][0];
1079 ctx
->saved
.sampler
[1] = nvc0
->samplers
[4][1];
1081 nvc0
->samplers
[4][0] = &blitter
->sampler
[ctx
->filter
];
1082 nvc0
->samplers
[4][1] = &blitter
->sampler
[ctx
->filter
];
1084 for (s
= 0; s
<= 3; ++s
)
1085 nvc0
->num_samplers
[s
] = 0;
1086 nvc0
->num_samplers
[4] = 2;
1088 nvc0
->min_samples
= 1;
1090 ctx
->saved
.dirty_3d
= nvc0
->dirty_3d
;
1092 nvc0
->textures_dirty
[4] |= 3;
1093 nvc0
->samplers_dirty
[4] |= 3;
1095 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_3D_FB
);
1096 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_3D_TEX(4, 0));
1097 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_3D_TEX(4, 1));
1099 nvc0
->dirty_3d
= NVC0_NEW_3D_FRAMEBUFFER
| NVC0_NEW_3D_MIN_SAMPLES
|
1100 NVC0_NEW_3D_VERTPROG
| NVC0_NEW_3D_FRAGPROG
|
1101 NVC0_NEW_3D_TCTLPROG
| NVC0_NEW_3D_TEVLPROG
| NVC0_NEW_3D_GMTYPROG
|
1102 NVC0_NEW_3D_TEXTURES
| NVC0_NEW_3D_SAMPLERS
;
1106 nvc0_blitctx_post_blit(struct nvc0_blitctx
*blit
)
1108 struct nvc0_context
*nvc0
= blit
->nvc0
;
1111 pipe_surface_reference(&nvc0
->framebuffer
.cbufs
[0], NULL
);
1113 nvc0
->framebuffer
.width
= blit
->saved
.fb
.width
;
1114 nvc0
->framebuffer
.height
= blit
->saved
.fb
.height
;
1115 nvc0
->framebuffer
.samples
= blit
->saved
.fb
.samples
;
1116 nvc0
->framebuffer
.layers
= blit
->saved
.fb
.layers
;
1117 nvc0
->framebuffer
.nr_cbufs
= blit
->saved
.fb
.nr_cbufs
;
1118 nvc0
->framebuffer
.cbufs
[0] = blit
->saved
.fb
.cbufs
[0];
1119 nvc0
->framebuffer
.zsbuf
= blit
->saved
.fb
.zsbuf
;
1121 nvc0
->rast
= blit
->saved
.rast
;
1123 nvc0
->vertprog
= blit
->saved
.vp
;
1124 nvc0
->tctlprog
= blit
->saved
.tcp
;
1125 nvc0
->tevlprog
= blit
->saved
.tep
;
1126 nvc0
->gmtyprog
= blit
->saved
.gp
;
1127 nvc0
->fragprog
= blit
->saved
.fp
;
1129 nvc0
->min_samples
= blit
->saved
.min_samples
;
1131 pipe_sampler_view_reference(&nvc0
->textures
[4][0], NULL
);
1132 pipe_sampler_view_reference(&nvc0
->textures
[4][1], NULL
);
1134 for (s
= 0; s
<= 4; ++s
) {
1135 nvc0
->num_textures
[s
] = blit
->saved
.num_textures
[s
];
1136 nvc0
->num_samplers
[s
] = blit
->saved
.num_samplers
[s
];
1137 nvc0
->textures_dirty
[s
] = (1 << nvc0
->num_textures
[s
]) - 1;
1138 nvc0
->samplers_dirty
[s
] = (1 << nvc0
->num_samplers
[s
]) - 1;
1140 nvc0
->textures
[4][0] = blit
->saved
.texture
[0];
1141 nvc0
->textures
[4][1] = blit
->saved
.texture
[1];
1142 nvc0
->samplers
[4][0] = blit
->saved
.sampler
[0];
1143 nvc0
->samplers
[4][1] = blit
->saved
.sampler
[1];
1145 nvc0
->textures_dirty
[4] |= 3;
1146 nvc0
->samplers_dirty
[4] |= 3;
1148 if (nvc0
->cond_query
&& !blit
->render_condition_enable
)
1149 nvc0
->base
.pipe
.render_condition(&nvc0
->base
.pipe
, nvc0
->cond_query
,
1150 nvc0
->cond_cond
, nvc0
->cond_mode
);
1152 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_3D_VTX_TMP
);
1153 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_3D_FB
);
1154 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_3D_TEX(4, 0));
1155 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_3D_TEX(4, 1));
1156 nouveau_scratch_done(&nvc0
->base
);
1158 nvc0
->dirty_3d
= blit
->saved
.dirty_3d
|
1159 (NVC0_NEW_3D_FRAMEBUFFER
| NVC0_NEW_3D_SCISSOR
| NVC0_NEW_3D_SAMPLE_MASK
|
1160 NVC0_NEW_3D_RASTERIZER
| NVC0_NEW_3D_ZSA
| NVC0_NEW_3D_BLEND
|
1161 NVC0_NEW_3D_VIEWPORT
|
1162 NVC0_NEW_3D_TEXTURES
| NVC0_NEW_3D_SAMPLERS
|
1163 NVC0_NEW_3D_VERTPROG
| NVC0_NEW_3D_FRAGPROG
|
1164 NVC0_NEW_3D_TCTLPROG
| NVC0_NEW_3D_TEVLPROG
| NVC0_NEW_3D_GMTYPROG
|
1165 NVC0_NEW_3D_TFB_TARGETS
| NVC0_NEW_3D_VERTEX
| NVC0_NEW_3D_ARRAYS
);
1166 nvc0
->scissors_dirty
|= 1;
1167 nvc0
->viewports_dirty
|= 1;
1169 nvc0
->base
.pipe
.set_min_samples(&nvc0
->base
.pipe
, blit
->saved
.min_samples
);
1173 nvc0_blit_3d(struct nvc0_context
*nvc0
, const struct pipe_blit_info
*info
)
1175 struct nvc0_blitctx
*blit
= nvc0
->blit
;
1176 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
1177 struct pipe_resource
*src
= info
->src
.resource
;
1178 struct pipe_resource
*dst
= info
->dst
.resource
;
1179 struct nouveau_bo
*vtxbuf_bo
;
1180 uint32_t stride
, length
, *vbuf
;
1182 int32_t minx
, maxx
, miny
, maxy
;
1184 float x0
, x1
, y0
, y1
, z
;
1186 float x_range
, y_range
;
1188 blit
->mode
= nv50_blit_select_mode(info
);
1189 blit
->color_mask
= nv50_blit_derive_color_mask(info
);
1190 blit
->filter
= nv50_blit_get_filter(info
);
1191 blit
->render_condition_enable
= info
->render_condition_enable
;
1193 nvc0_blit_select_fp(blit
, info
);
1194 nvc0_blitctx_pre_blit(blit
);
1196 nvc0_blit_set_dst(blit
, dst
, info
->dst
.level
, -1, info
->dst
.format
);
1197 nvc0_blit_set_src(blit
, src
, info
->src
.level
, -1, info
->src
.format
,
1200 nvc0_blitctx_prepare_state(blit
);
1202 nvc0_state_validate_3d(nvc0
, ~0);
1204 x_range
= (float)info
->src
.box
.width
/ (float)info
->dst
.box
.width
;
1205 y_range
= (float)info
->src
.box
.height
/ (float)info
->dst
.box
.height
;
1207 x0
= (float)info
->src
.box
.x
- x_range
* (float)info
->dst
.box
.x
;
1208 y0
= (float)info
->src
.box
.y
- y_range
* (float)info
->dst
.box
.y
;
1210 x1
= x0
+ 32768.0f
* x_range
;
1211 y1
= y0
+ 32768.0f
* y_range
;
1213 x0
*= (float)(1 << nv50_miptree(src
)->ms_x
);
1214 x1
*= (float)(1 << nv50_miptree(src
)->ms_x
);
1215 y0
*= (float)(1 << nv50_miptree(src
)->ms_y
);
1216 y1
*= (float)(1 << nv50_miptree(src
)->ms_y
);
1218 dz
= (float)info
->src
.box
.depth
/ (float)info
->dst
.box
.depth
;
1219 z
= (float)info
->src
.box
.z
;
1220 if (nv50_miptree(src
)->layout_3d
)
1223 if (src
->last_level
> 0) {
1224 /* If there are mip maps, GPU always assumes normalized coordinates. */
1225 const unsigned l
= info
->src
.level
;
1226 const float fh
= u_minify(src
->width0
<< nv50_miptree(src
)->ms_x
, l
);
1227 const float fv
= u_minify(src
->height0
<< nv50_miptree(src
)->ms_y
, l
);
1232 if (nv50_miptree(src
)->layout_3d
) {
1233 z
/= u_minify(src
->depth0
, l
);
1234 dz
/= u_minify(src
->depth0
, l
);
1238 IMMED_NVC0(push
, NVC0_3D(VIEWPORT_TRANSFORM_EN
), 0);
1239 IMMED_NVC0(push
, NVC0_3D(VIEW_VOLUME_CLIP_CTRL
), 0x2 |
1240 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_RANGE_0_1
);
1241 BEGIN_NVC0(push
, NVC0_3D(VIEWPORT_HORIZ(0)), 2);
1242 PUSH_DATA (push
, nvc0
->framebuffer
.width
<< 16);
1243 PUSH_DATA (push
, nvc0
->framebuffer
.height
<< 16);
1245 /* Draw a large triangle in screen coordinates covering the whole
1246 * render target, with scissors defining the destination region.
1247 * The vertex is supplied with non-normalized texture coordinates
1248 * arranged in a way to yield the desired offset and scale.
1251 minx
= info
->dst
.box
.x
;
1252 maxx
= info
->dst
.box
.x
+ info
->dst
.box
.width
;
1253 miny
= info
->dst
.box
.y
;
1254 maxy
= info
->dst
.box
.y
+ info
->dst
.box
.height
;
1255 if (info
->scissor_enable
) {
1256 minx
= MAX2(minx
, info
->scissor
.minx
);
1257 maxx
= MIN2(maxx
, info
->scissor
.maxx
);
1258 miny
= MAX2(miny
, info
->scissor
.miny
);
1259 maxy
= MIN2(maxy
, info
->scissor
.maxy
);
1261 BEGIN_NVC0(push
, NVC0_3D(SCISSOR_HORIZ(0)), 2);
1262 PUSH_DATA (push
, (maxx
<< 16) | minx
);
1263 PUSH_DATA (push
, (maxy
<< 16) | miny
);
1265 stride
= (3 + 2) * 4;
1266 length
= stride
* 3 * info
->dst
.box
.depth
;
1268 vbuf
= nouveau_scratch_get(&nvc0
->base
, length
, &vtxbuf
, &vtxbuf_bo
);
1274 BCTX_REFN_bo(nvc0
->bufctx_3d
, 3D_VTX_TMP
,
1275 NOUVEAU_BO_GART
| NOUVEAU_BO_RD
, vtxbuf_bo
);
1276 nouveau_pushbuf_validate(push
);
1278 BEGIN_NVC0(push
, NVC0_3D(VERTEX_ARRAY_FETCH(0)), 4);
1279 PUSH_DATA (push
, NVC0_3D_VERTEX_ARRAY_FETCH_ENABLE
| stride
<<
1280 NVC0_3D_VERTEX_ARRAY_FETCH_STRIDE__SHIFT
);
1281 PUSH_DATAh(push
, vtxbuf
);
1282 PUSH_DATA (push
, vtxbuf
);
1283 PUSH_DATA (push
, 0);
1284 BEGIN_NVC0(push
, NVC0_3D(VERTEX_ARRAY_LIMIT_HIGH(0)), 2);
1285 PUSH_DATAh(push
, vtxbuf
+ length
- 1);
1286 PUSH_DATA (push
, vtxbuf
+ length
- 1);
1288 n
= MAX2(2, nvc0
->state
.num_vtxelts
);
1290 BEGIN_NVC0(push
, NVC0_3D(VERTEX_ATTRIB_FORMAT(0)), n
);
1291 PUSH_DATA (push
, NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT
|
1292 NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32_32
| 0x00 <<
1293 NVC0_3D_VERTEX_ATTRIB_FORMAT_OFFSET__SHIFT
);
1294 PUSH_DATA (push
, NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT
|
1295 NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32_32_32
| 0x08 <<
1296 NVC0_3D_VERTEX_ATTRIB_FORMAT_OFFSET__SHIFT
);
1297 for (i
= 2; i
< n
; i
++) {
1298 PUSH_DATA(push
, NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT
|
1299 NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32
|
1300 NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST
);
1302 for (i
= 1; i
< n
; ++i
)
1303 IMMED_NVC0(push
, NVC0_3D(VERTEX_ARRAY_FETCH(i
)), 0);
1304 if (nvc0
->state
.instance_elts
) {
1305 nvc0
->state
.instance_elts
= 0;
1306 BEGIN_NVC0(push
, NVC0_3D(MACRO_VERTEX_ARRAY_PER_INSTANCE
), 2);
1307 PUSH_DATA (push
, n
);
1308 PUSH_DATA (push
, 0);
1310 nvc0
->state
.num_vtxelts
= 2;
1312 if (nvc0
->state
.prim_restart
) {
1313 IMMED_NVC0(push
, NVC0_3D(PRIM_RESTART_ENABLE
), 0);
1314 nvc0
->state
.prim_restart
= 0;
1317 if (nvc0
->state
.index_bias
) {
1318 IMMED_NVC0(push
, NVC0_3D(VB_ELEMENT_BASE
), 0);
1319 IMMED_NVC0(push
, NVC0_3D(VERTEX_ID_BASE
), 0);
1320 nvc0
->state
.index_bias
= 0;
1323 for (i
= 0; i
< info
->dst
.box
.depth
; ++i
, z
+= dz
) {
1324 if (info
->dst
.box
.z
+ i
) {
1325 BEGIN_NVC0(push
, NVC0_3D(LAYER
), 1);
1326 PUSH_DATA (push
, info
->dst
.box
.z
+ i
);
1329 *(vbuf
++) = fui(0.0f
);
1330 *(vbuf
++) = fui(0.0f
);
1331 *(vbuf
++) = fui(x0
);
1332 *(vbuf
++) = fui(y0
);
1335 *(vbuf
++) = fui(32768 << nv50_miptree(dst
)->ms_x
);
1336 *(vbuf
++) = fui(0.0f
);
1337 *(vbuf
++) = fui(x1
);
1338 *(vbuf
++) = fui(y0
);
1341 *(vbuf
++) = fui(0.0f
);
1342 *(vbuf
++) = fui(32768 << nv50_miptree(dst
)->ms_y
);
1343 *(vbuf
++) = fui(x0
);
1344 *(vbuf
++) = fui(y1
);
1347 IMMED_NVC0(push
, NVC0_3D(VERTEX_BEGIN_GL
),
1348 NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES
);
1349 BEGIN_NVC0(push
, NVC0_3D(VERTEX_BUFFER_FIRST
), 2);
1350 PUSH_DATA (push
, i
* 3);
1351 PUSH_DATA (push
, 3);
1352 IMMED_NVC0(push
, NVC0_3D(VERTEX_END_GL
), 0);
1354 if (info
->dst
.box
.z
+ info
->dst
.box
.depth
- 1)
1355 IMMED_NVC0(push
, NVC0_3D(LAYER
), 0);
1357 nvc0_blitctx_post_blit(blit
);
1359 /* restore viewport transform */
1360 IMMED_NVC0(push
, NVC0_3D(VIEWPORT_TRANSFORM_EN
), 1);
1364 nvc0_blit_eng2d(struct nvc0_context
*nvc0
, const struct pipe_blit_info
*info
)
1366 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
1367 struct nv50_miptree
*dst
= nv50_miptree(info
->dst
.resource
);
1368 struct nv50_miptree
*src
= nv50_miptree(info
->src
.resource
);
1369 const int32_t srcx_adj
= info
->src
.box
.width
< 0 ? -1 : 0;
1370 const int32_t srcy_adj
= info
->src
.box
.height
< 0 ? -1 : 0;
1371 const int dz
= info
->dst
.box
.z
;
1372 const int sz
= info
->src
.box
.z
;
1373 uint32_t dstw
, dsth
;
1376 int64_t du_dx
, dv_dy
;
1379 uint32_t mask
= nv50_blit_eng2d_get_mask(info
);
1382 mode
= nv50_blit_get_filter(info
) ?
1383 NV50_2D_BLIT_CONTROL_FILTER_BILINEAR
:
1384 NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE
;
1385 mode
|= (src
->base
.base
.nr_samples
> dst
->base
.base
.nr_samples
) ?
1386 NV50_2D_BLIT_CONTROL_ORIGIN_CORNER
: NV50_2D_BLIT_CONTROL_ORIGIN_CENTER
;
1388 du_dx
= ((int64_t)info
->src
.box
.width
<< 32) / info
->dst
.box
.width
;
1389 dv_dy
= ((int64_t)info
->src
.box
.height
<< 32) / info
->dst
.box
.height
;
1391 b
= info
->dst
.format
== info
->src
.format
;
1392 nvc0_2d_texture_set(push
, 1, dst
, info
->dst
.level
, dz
, info
->dst
.format
, b
);
1393 nvc0_2d_texture_set(push
, 0, src
, info
->src
.level
, sz
, info
->src
.format
, b
);
1395 if (info
->scissor_enable
) {
1396 BEGIN_NVC0(push
, NVC0_2D(CLIP_X
), 5);
1397 PUSH_DATA (push
, info
->scissor
.minx
<< dst
->ms_x
);
1398 PUSH_DATA (push
, info
->scissor
.miny
<< dst
->ms_y
);
1399 PUSH_DATA (push
, (info
->scissor
.maxx
- info
->scissor
.minx
) << dst
->ms_x
);
1400 PUSH_DATA (push
, (info
->scissor
.maxy
- info
->scissor
.miny
) << dst
->ms_y
);
1401 PUSH_DATA (push
, 1); /* enable */
1404 if (nvc0
->cond_query
&& info
->render_condition_enable
)
1405 IMMED_NVC0(push
, NVC0_2D(COND_MODE
), nvc0
->cond_condmode
);
1407 if (mask
!= 0xffffffff) {
1408 IMMED_NVC0(push
, NVC0_2D(ROP
), 0xca); /* DPSDxax */
1409 IMMED_NVC0(push
, NVC0_2D(PATTERN_COLOR_FORMAT
),
1410 NV50_2D_PATTERN_COLOR_FORMAT_A8R8G8B8
);
1411 BEGIN_NVC0(push
, NVC0_2D(PATTERN_BITMAP_COLOR(0)), 4);
1412 PUSH_DATA (push
, 0x00000000);
1413 PUSH_DATA (push
, mask
);
1414 PUSH_DATA (push
, 0xffffffff);
1415 PUSH_DATA (push
, 0xffffffff);
1416 IMMED_NVC0(push
, NVC0_2D(OPERATION
), NV50_2D_OPERATION_ROP
);
1418 if (info
->src
.format
!= info
->dst
.format
) {
1419 if (info
->src
.format
== PIPE_FORMAT_R8_UNORM
||
1420 info
->src
.format
== PIPE_FORMAT_R8_SNORM
||
1421 info
->src
.format
== PIPE_FORMAT_R16_UNORM
||
1422 info
->src
.format
== PIPE_FORMAT_R16_SNORM
||
1423 info
->src
.format
== PIPE_FORMAT_R16_FLOAT
||
1424 info
->src
.format
== PIPE_FORMAT_R32_FLOAT
) {
1425 mask
= 0xffff0000; /* also makes condition for OPERATION reset true */
1426 BEGIN_NVC0(push
, NVC0_2D(BETA4
), 2);
1427 PUSH_DATA (push
, mask
);
1428 PUSH_DATA (push
, NV50_2D_OPERATION_SRCCOPY_PREMULT
);
1430 if (info
->src
.format
== PIPE_FORMAT_A8_UNORM
) {
1432 BEGIN_NVC0(push
, NVC0_2D(BETA4
), 2);
1433 PUSH_DATA (push
, mask
);
1434 PUSH_DATA (push
, NV50_2D_OPERATION_SRCCOPY_PREMULT
);
1438 if (src
->ms_x
> dst
->ms_x
|| src
->ms_y
> dst
->ms_y
) {
1439 /* ms_x is always >= ms_y */
1440 du_dx
<<= src
->ms_x
- dst
->ms_x
;
1441 dv_dy
<<= src
->ms_y
- dst
->ms_y
;
1443 du_dx
>>= dst
->ms_x
- src
->ms_x
;
1444 dv_dy
>>= dst
->ms_y
- src
->ms_y
;
1447 srcx
= (int64_t)(info
->src
.box
.x
+ srcx_adj
) << (src
->ms_x
+ 32);
1448 srcy
= (int64_t)(info
->src
.box
.y
+ srcy_adj
) << (src
->ms_y
+ 32);
1450 if (src
->base
.base
.nr_samples
> dst
->base
.base
.nr_samples
) {
1451 /* center src coorinates for proper MS resolve filtering */
1452 srcx
+= (int64_t)1 << (src
->ms_x
+ 31);
1453 srcy
+= (int64_t)1 << (src
->ms_y
+ 31);
1456 dstx
= info
->dst
.box
.x
<< dst
->ms_x
;
1457 dsty
= info
->dst
.box
.y
<< dst
->ms_y
;
1459 dstw
= info
->dst
.box
.width
<< dst
->ms_x
;
1460 dsth
= info
->dst
.box
.height
<< dst
->ms_y
;
1464 srcx
-= du_dx
* dstx
;
1469 srcy
-= dv_dy
* dsty
;
1473 IMMED_NVC0(push
, NVC0_2D(BLIT_CONTROL
), mode
);
1474 BEGIN_NVC0(push
, NVC0_2D(BLIT_DST_X
), 4);
1475 PUSH_DATA (push
, dstx
);
1476 PUSH_DATA (push
, dsty
);
1477 PUSH_DATA (push
, dstw
);
1478 PUSH_DATA (push
, dsth
);
1479 BEGIN_NVC0(push
, NVC0_2D(BLIT_DU_DX_FRACT
), 4);
1480 PUSH_DATA (push
, du_dx
);
1481 PUSH_DATA (push
, du_dx
>> 32);
1482 PUSH_DATA (push
, dv_dy
);
1483 PUSH_DATA (push
, dv_dy
>> 32);
1485 BCTX_REFN(nvc0
->bufctx
, 2D
, &dst
->base
, WR
);
1486 BCTX_REFN(nvc0
->bufctx
, 2D
, &src
->base
, RD
);
1487 nouveau_pushbuf_bufctx(nvc0
->base
.pushbuf
, nvc0
->bufctx
);
1488 if (nouveau_pushbuf_validate(nvc0
->base
.pushbuf
))
1491 for (i
= 0; i
< info
->dst
.box
.depth
; ++i
) {
1493 /* no scaling in z-direction possible for eng2d blits */
1494 if (dst
->layout_3d
) {
1495 BEGIN_NVC0(push
, NVC0_2D(DST_LAYER
), 1);
1496 PUSH_DATA (push
, info
->dst
.box
.z
+ i
);
1498 const unsigned z
= info
->dst
.box
.z
+ i
;
1499 const uint64_t address
= dst
->base
.address
+
1500 dst
->level
[info
->dst
.level
].offset
+
1501 z
* dst
->layer_stride
;
1502 BEGIN_NVC0(push
, NVC0_2D(DST_ADDRESS_HIGH
), 2);
1503 PUSH_DATAh(push
, address
);
1504 PUSH_DATA (push
, address
);
1506 if (src
->layout_3d
) {
1507 /* not possible because of depth tiling */
1510 const unsigned z
= info
->src
.box
.z
+ i
;
1511 const uint64_t address
= src
->base
.address
+
1512 src
->level
[info
->src
.level
].offset
+
1513 z
* src
->layer_stride
;
1514 BEGIN_NVC0(push
, NVC0_2D(SRC_ADDRESS_HIGH
), 2);
1515 PUSH_DATAh(push
, address
);
1516 PUSH_DATA (push
, address
);
1518 BEGIN_NVC0(push
, NVC0_2D(BLIT_SRC_Y_INT
), 1); /* trigger */
1519 PUSH_DATA (push
, srcy
>> 32);
1521 BEGIN_NVC0(push
, NVC0_2D(BLIT_SRC_X_FRACT
), 4);
1522 PUSH_DATA (push
, srcx
);
1523 PUSH_DATA (push
, srcx
>> 32);
1524 PUSH_DATA (push
, srcy
);
1525 PUSH_DATA (push
, srcy
>> 32);
1528 nvc0_resource_validate(&dst
->base
, NOUVEAU_BO_WR
);
1529 nvc0_resource_validate(&src
->base
, NOUVEAU_BO_RD
);
1531 nouveau_bufctx_reset(nvc0
->bufctx
, NVC0_BIND_2D
);
1533 if (info
->scissor_enable
)
1534 IMMED_NVC0(push
, NVC0_2D(CLIP_ENABLE
), 0);
1535 if (mask
!= 0xffffffff)
1536 IMMED_NVC0(push
, NVC0_2D(OPERATION
), NV50_2D_OPERATION_SRCCOPY
);
1537 if (nvc0
->cond_query
&& info
->render_condition_enable
)
1538 IMMED_NVC0(push
, NVC0_2D(COND_MODE
), NV50_2D_COND_MODE_ALWAYS
);
1542 nvc0_blit(struct pipe_context
*pipe
, const struct pipe_blit_info
*info
)
1544 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
1545 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
1548 if (util_format_is_depth_or_stencil(info
->dst
.resource
->format
)) {
1549 if (!(info
->mask
& PIPE_MASK_ZS
))
1551 if (info
->dst
.resource
->format
== PIPE_FORMAT_Z32_FLOAT
||
1552 info
->dst
.resource
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
)
1554 if (info
->filter
!= PIPE_TEX_FILTER_NEAREST
)
1557 if (!(info
->mask
& PIPE_MASK_RGBA
))
1559 if (info
->mask
!= PIPE_MASK_RGBA
)
1563 if (nv50_miptree(info
->src
.resource
)->layout_3d
) {
1566 if (info
->src
.box
.depth
!= info
->dst
.box
.depth
) {
1568 debug_printf("blit: cannot filter array or cube textures in z direction");
1571 if (!eng3d
&& info
->dst
.format
!= info
->src
.format
) {
1572 if (!nv50_2d_dst_format_faithful(info
->dst
.format
)) {
1575 if (!nv50_2d_src_format_faithful(info
->src
.format
)) {
1576 if (!util_format_is_luminance(info
->src
.format
)) {
1577 if (!nv50_2d_dst_format_ops_supported(info
->dst
.format
))
1580 if (util_format_is_intensity(info
->src
.format
))
1581 eng3d
= info
->src
.format
!= PIPE_FORMAT_I8_UNORM
;
1583 if (util_format_is_alpha(info
->src
.format
))
1584 eng3d
= info
->src
.format
!= PIPE_FORMAT_A8_UNORM
;
1586 eng3d
= !nv50_2d_format_supported(info
->src
.format
);
1589 if (util_format_is_luminance_alpha(info
->src
.format
))
1593 if (info
->src
.resource
->nr_samples
== 8 &&
1594 info
->dst
.resource
->nr_samples
<= 1)
1597 /* FIXME: can't make this work with eng2d anymore, at least not on nv50 */
1598 if (info
->src
.resource
->nr_samples
> 1 ||
1599 info
->dst
.resource
->nr_samples
> 1)
1602 /* FIXME: find correct src coordinates adjustments */
1603 if ((info
->src
.box
.width
!= info
->dst
.box
.width
&&
1604 info
->src
.box
.width
!= -info
->dst
.box
.width
) ||
1605 (info
->src
.box
.height
!= info
->dst
.box
.height
&&
1606 info
->src
.box
.height
!= -info
->dst
.box
.height
))
1609 if (nvc0
->screen
->num_occlusion_queries_active
)
1610 IMMED_NVC0(push
, NVC0_3D(SAMPLECNT_ENABLE
), 0);
1613 nvc0_blit_eng2d(nvc0
, info
);
1615 nvc0_blit_3d(nvc0
, info
);
1617 if (nvc0
->screen
->num_occlusion_queries_active
)
1618 IMMED_NVC0(push
, NVC0_3D(SAMPLECNT_ENABLE
), 1);
1620 NOUVEAU_DRV_STAT(&nvc0
->screen
->base
, tex_blit_count
, 1);
1624 nvc0_flush_resource(struct pipe_context
*ctx
,
1625 struct pipe_resource
*resource
)
1630 nvc0_blitter_create(struct nvc0_screen
*screen
)
1632 screen
->blitter
= CALLOC_STRUCT(nvc0_blitter
);
1633 if (!screen
->blitter
) {
1634 NOUVEAU_ERR("failed to allocate blitter struct\n");
1637 screen
->blitter
->screen
= screen
;
1639 pipe_mutex_init(screen
->blitter
->mutex
);
1641 nvc0_blitter_make_vp(screen
->blitter
);
1642 nvc0_blitter_make_sampler(screen
->blitter
);
1648 nvc0_blitter_destroy(struct nvc0_screen
*screen
)
1650 struct nvc0_blitter
*blitter
= screen
->blitter
;
1653 for (i
= 0; i
< NV50_BLIT_MAX_TEXTURE_TYPES
; ++i
) {
1654 for (m
= 0; m
< NV50_BLIT_MODES
; ++m
) {
1655 struct nvc0_program
*prog
= blitter
->fp
[i
][m
];
1657 nvc0_program_destroy(NULL
, prog
);
1658 FREE((void *)prog
->pipe
.tokens
);
1664 pipe_mutex_destroy(blitter
->mutex
);
1669 nvc0_blitctx_create(struct nvc0_context
*nvc0
)
1671 nvc0
->blit
= CALLOC_STRUCT(nvc0_blitctx
);
1673 NOUVEAU_ERR("failed to allocate blit context\n");
1677 nvc0
->blit
->nvc0
= nvc0
;
1679 nvc0
->blit
->rast
.pipe
.half_pixel_center
= 1;
1685 nvc0_blitctx_destroy(struct nvc0_context
*nvc0
)
1691 nvc0_init_surface_functions(struct nvc0_context
*nvc0
)
1693 struct pipe_context
*pipe
= &nvc0
->base
.pipe
;
1695 pipe
->resource_copy_region
= nvc0_resource_copy_region
;
1696 pipe
->blit
= nvc0_blit
;
1697 pipe
->flush_resource
= nvc0_flush_resource
;
1698 pipe
->clear_render_target
= nvc0_clear_render_target
;
1699 pipe
->clear_depth_stencil
= nvc0_clear_depth_stencil
;
1700 pipe
->clear_texture
= nv50_clear_texture
;
1701 pipe
->clear_buffer
= nvc0_clear_buffer
;