2 * Copyright 2008 Ben Skeggs
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include "nvc0/nvc0_context.h"
24 #include "nvc0/nvc0_resource.h"
25 #include "nvc0/gm107_texture.xml.h"
26 #include "nvc0/nvc0_compute.xml.h"
27 #include "nv50/g80_texture.xml.h"
28 #include "nv50/g80_defs.xml.h"
30 #include "util/u_format.h"
32 #define NVE4_TIC_ENTRY_INVALID 0x000fffff
33 #define NVE4_TSC_ENTRY_INVALID 0xfff00000
35 static inline uint32_t
36 nv50_tic_swizzle(const struct nvc0_format
*fmt
, unsigned swz
, bool tex_int
)
39 case PIPE_SWIZZLE_X
: return fmt
->tic
.src_x
;
40 case PIPE_SWIZZLE_Y
: return fmt
->tic
.src_y
;
41 case PIPE_SWIZZLE_Z
: return fmt
->tic
.src_z
;
42 case PIPE_SWIZZLE_W
: return fmt
->tic
.src_w
;
44 return tex_int
? G80_TIC_SOURCE_ONE_INT
: G80_TIC_SOURCE_ONE_FLOAT
;
47 return G80_TIC_SOURCE_ZERO
;
51 struct pipe_sampler_view
*
52 nvc0_create_sampler_view(struct pipe_context
*pipe
,
53 struct pipe_resource
*res
,
54 const struct pipe_sampler_view
*templ
)
58 if (templ
->target
== PIPE_TEXTURE_RECT
|| templ
->target
== PIPE_BUFFER
)
59 flags
|= NV50_TEXVIEW_SCALED_COORDS
;
61 return nvc0_create_texture_view(pipe
, res
, templ
, flags
, templ
->target
);
64 static struct pipe_sampler_view
*
65 gm107_create_texture_view(struct pipe_context
*pipe
,
66 struct pipe_resource
*texture
,
67 const struct pipe_sampler_view
*templ
,
69 enum pipe_texture_target target
)
71 const struct util_format_description
*desc
;
72 const struct nvc0_format
*fmt
;
76 uint32_t width
, height
;
78 struct nv50_tic_entry
*view
;
79 struct nv50_miptree
*mt
;
82 view
= MALLOC_STRUCT(nv50_tic_entry
);
85 mt
= nv50_miptree(texture
);
88 view
->pipe
.reference
.count
= 1;
89 view
->pipe
.texture
= NULL
;
90 view
->pipe
.context
= pipe
;
94 pipe_resource_reference(&view
->pipe
.texture
, texture
);
98 desc
= util_format_description(view
->pipe
.format
);
99 tex_int
= util_format_is_pure_integer(view
->pipe
.format
);
101 fmt
= &nvc0_format_table
[view
->pipe
.format
];
102 swz
[0] = nv50_tic_swizzle(fmt
, view
->pipe
.swizzle_r
, tex_int
);
103 swz
[1] = nv50_tic_swizzle(fmt
, view
->pipe
.swizzle_g
, tex_int
);
104 swz
[2] = nv50_tic_swizzle(fmt
, view
->pipe
.swizzle_b
, tex_int
);
105 swz
[3] = nv50_tic_swizzle(fmt
, view
->pipe
.swizzle_a
, tex_int
);
107 tic
[0] = fmt
->tic
.format
<< GM107_TIC2_0_COMPONENTS_SIZES__SHIFT
;
108 tic
[0] |= fmt
->tic
.type_r
<< GM107_TIC2_0_R_DATA_TYPE__SHIFT
;
109 tic
[0] |= fmt
->tic
.type_g
<< GM107_TIC2_0_G_DATA_TYPE__SHIFT
;
110 tic
[0] |= fmt
->tic
.type_b
<< GM107_TIC2_0_B_DATA_TYPE__SHIFT
;
111 tic
[0] |= fmt
->tic
.type_a
<< GM107_TIC2_0_A_DATA_TYPE__SHIFT
;
112 tic
[0] |= swz
[0] << GM107_TIC2_0_X_SOURCE__SHIFT
;
113 tic
[0] |= swz
[1] << GM107_TIC2_0_Y_SOURCE__SHIFT
;
114 tic
[0] |= swz
[2] << GM107_TIC2_0_Z_SOURCE__SHIFT
;
115 tic
[0] |= swz
[3] << GM107_TIC2_0_W_SOURCE__SHIFT
;
117 address
= mt
->base
.address
;
119 tic
[3] = GM107_TIC2_3_LOD_ANISO_QUALITY_2
;
120 tic
[4] = GM107_TIC2_4_SECTOR_PROMOTION_PROMOTE_TO_2_V
;
121 tic
[4] |= GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR
;
123 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
124 tic
[4] |= GM107_TIC2_4_SRGB_CONVERSION
;
126 if (!(flags
& NV50_TEXVIEW_SCALED_COORDS
))
127 tic
[5] = GM107_TIC2_5_NORMALIZED_COORDS
;
131 /* check for linear storage type */
132 if (unlikely(!nouveau_bo_memtype(nv04_resource(texture
)->bo
))) {
133 if (texture
->target
== PIPE_BUFFER
) {
134 assert(!(tic
[5] & GM107_TIC2_5_NORMALIZED_COORDS
));
135 width
= view
->pipe
.u
.buf
.last_element
- view
->pipe
.u
.buf
.first_element
;
137 view
->pipe
.u
.buf
.first_element
* desc
->block
.bits
/ 8;
138 tic
[2] = GM107_TIC2_2_HEADER_VERSION_ONE_D_BUFFER
;
139 tic
[3] |= width
>> 16;
140 tic
[4] |= GM107_TIC2_4_TEXTURE_TYPE_ONE_D_BUFFER
;
141 tic
[4] |= width
& 0xffff;
143 assert(!(mt
->level
[0].pitch
& 0x1f));
144 /* must be 2D texture without mip maps */
145 tic
[2] = GM107_TIC2_2_HEADER_VERSION_PITCH
;
146 tic
[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP
;
147 tic
[3] |= mt
->level
[0].pitch
>> 5;
148 tic
[4] |= mt
->base
.base
.width0
- 1;
149 tic
[5] |= 0 << GM107_TIC2_5_DEPTH_MINUS_ONE__SHIFT
;
150 tic
[5] |= mt
->base
.base
.height0
- 1;
153 tic
[2] |= address
>> 32;
159 tic
[2] = GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR
;
161 ((mt
->level
[0].tile_mode
& 0x0f0) >> 4 << 3) |
162 ((mt
->level
[0].tile_mode
& 0xf00) >> 8 << 6);
164 depth
= MAX2(mt
->base
.base
.array_size
, mt
->base
.base
.depth0
);
166 if (mt
->base
.base
.array_size
> 1) {
167 /* there doesn't seem to be a base layer field in TIC */
168 address
+= view
->pipe
.u
.tex
.first_layer
* mt
->layer_stride
;
169 depth
= view
->pipe
.u
.tex
.last_layer
- view
->pipe
.u
.tex
.first_layer
+ 1;
172 tic
[2] |= address
>> 32;
175 case PIPE_TEXTURE_1D
:
176 tic
[4] |= GM107_TIC2_4_TEXTURE_TYPE_ONE_D
;
178 case PIPE_TEXTURE_2D
:
179 tic
[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D
;
181 case PIPE_TEXTURE_RECT
:
182 tic
[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D
;
184 case PIPE_TEXTURE_3D
:
185 tic
[4] |= GM107_TIC2_4_TEXTURE_TYPE_THREE_D
;
187 case PIPE_TEXTURE_CUBE
:
189 tic
[4] |= GM107_TIC2_4_TEXTURE_TYPE_CUBEMAP
;
191 case PIPE_TEXTURE_1D_ARRAY
:
192 tic
[4] |= GM107_TIC2_4_TEXTURE_TYPE_ONE_D_ARRAY
;
194 case PIPE_TEXTURE_2D_ARRAY
:
195 tic
[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D_ARRAY
;
197 case PIPE_TEXTURE_CUBE_ARRAY
:
199 tic
[4] |= GM107_TIC2_4_TEXTURE_TYPE_CUBE_ARRAY
;
202 unreachable("unexpected/invalid texture target");
205 tic
[3] |= (flags
& NV50_TEXVIEW_FILTER_MSAA8
) ?
206 GM107_TIC2_3_USE_HEADER_OPT_CONTROL
:
207 GM107_TIC2_3_LOD_ANISO_QUALITY_HIGH
|
208 GM107_TIC2_3_LOD_ISO_QUALITY_HIGH
;
210 if (flags
& NV50_TEXVIEW_ACCESS_RESOLVE
) {
211 width
= mt
->base
.base
.width0
<< mt
->ms_x
;
212 height
= mt
->base
.base
.height0
<< mt
->ms_y
;
214 width
= mt
->base
.base
.width0
;
215 height
= mt
->base
.base
.height0
;
220 tic
[5] |= (height
- 1) & 0xffff;
221 tic
[5] |= (depth
- 1) << GM107_TIC2_5_DEPTH_MINUS_ONE__SHIFT
;
222 tic
[3] |= mt
->base
.base
.last_level
<< GM107_TIC2_3_MAX_MIP_LEVEL__SHIFT
;
224 /* sampling points: (?) */
225 if ((flags
& NV50_TEXVIEW_ACCESS_RESOLVE
) && mt
->ms_x
> 1) {
226 tic
[6] = GM107_TIC2_6_ANISO_FINE_SPREAD_MODIFIER_CONST_TWO
;
227 tic
[6] |= GM107_TIC2_6_MAX_ANISOTROPY_2_TO_1
;
229 tic
[6] = GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_TWO
;
230 tic
[6] |= GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_ONE
;
233 tic
[7] = (view
->pipe
.u
.tex
.last_level
<< 4) | view
->pipe
.u
.tex
.first_level
;
234 tic
[7] |= mt
->ms_mode
<< GM107_TIC2_7_MULTI_SAMPLE_COUNT__SHIFT
;
239 static struct pipe_sampler_view
*
240 gf100_create_texture_view(struct pipe_context
*pipe
,
241 struct pipe_resource
*texture
,
242 const struct pipe_sampler_view
*templ
,
244 enum pipe_texture_target target
)
246 const struct util_format_description
*desc
;
247 const struct nvc0_format
*fmt
;
251 uint32_t width
, height
;
254 struct nv50_tic_entry
*view
;
255 struct nv50_miptree
*mt
;
258 view
= MALLOC_STRUCT(nv50_tic_entry
);
261 mt
= nv50_miptree(texture
);
264 view
->pipe
.reference
.count
= 1;
265 view
->pipe
.texture
= NULL
;
266 view
->pipe
.context
= pipe
;
270 pipe_resource_reference(&view
->pipe
.texture
, texture
);
274 desc
= util_format_description(view
->pipe
.format
);
276 fmt
= &nvc0_format_table
[view
->pipe
.format
];
278 tex_int
= util_format_is_pure_integer(view
->pipe
.format
);
279 tex_fmt
= fmt
->tic
.format
& 0x3f;
281 swz
[0] = nv50_tic_swizzle(fmt
, view
->pipe
.swizzle_r
, tex_int
);
282 swz
[1] = nv50_tic_swizzle(fmt
, view
->pipe
.swizzle_g
, tex_int
);
283 swz
[2] = nv50_tic_swizzle(fmt
, view
->pipe
.swizzle_b
, tex_int
);
284 swz
[3] = nv50_tic_swizzle(fmt
, view
->pipe
.swizzle_a
, tex_int
);
285 tic
[0] = (tex_fmt
<< G80_TIC_0_COMPONENTS_SIZES__SHIFT
) |
286 (fmt
->tic
.type_r
<< G80_TIC_0_R_DATA_TYPE__SHIFT
) |
287 (fmt
->tic
.type_g
<< G80_TIC_0_G_DATA_TYPE__SHIFT
) |
288 (fmt
->tic
.type_b
<< G80_TIC_0_B_DATA_TYPE__SHIFT
) |
289 (fmt
->tic
.type_a
<< G80_TIC_0_A_DATA_TYPE__SHIFT
) |
290 (swz
[0] << G80_TIC_0_X_SOURCE__SHIFT
) |
291 (swz
[1] << G80_TIC_0_Y_SOURCE__SHIFT
) |
292 (swz
[2] << G80_TIC_0_Z_SOURCE__SHIFT
) |
293 (swz
[3] << G80_TIC_0_W_SOURCE__SHIFT
) |
294 ((fmt
->tic
.format
& 0x40) << (GK20A_TIC_0_USE_COMPONENT_SIZES_EXTENDED__SHIFT
- 6));
296 address
= mt
->base
.address
;
298 tic
[2] = 0x10001000 | G80_TIC_2_BORDER_SOURCE_COLOR
;
300 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
301 tic
[2] |= G80_TIC_2_SRGB_CONVERSION
;
303 if (!(flags
& NV50_TEXVIEW_SCALED_COORDS
))
304 tic
[2] |= G80_TIC_2_NORMALIZED_COORDS
;
306 /* check for linear storage type */
307 if (unlikely(!nouveau_bo_memtype(nv04_resource(texture
)->bo
))) {
308 if (texture
->target
== PIPE_BUFFER
) {
309 assert(!(tic
[2] & G80_TIC_2_NORMALIZED_COORDS
));
311 view
->pipe
.u
.buf
.first_element
* desc
->block
.bits
/ 8;
312 tic
[2] |= G80_TIC_2_LAYOUT_PITCH
| G80_TIC_2_TEXTURE_TYPE_ONE_D_BUFFER
;
315 view
->pipe
.u
.buf
.last_element
- view
->pipe
.u
.buf
.first_element
+ 1;
318 /* must be 2D texture without mip maps */
319 tic
[2] |= G80_TIC_2_LAYOUT_PITCH
| G80_TIC_2_TEXTURE_TYPE_TWO_D_NO_MIPMAP
;
320 tic
[3] = mt
->level
[0].pitch
;
321 tic
[4] = mt
->base
.base
.width0
;
322 tic
[5] = (1 << 16) | mt
->base
.base
.height0
;
327 tic
[2] |= address
>> 32;
332 ((mt
->level
[0].tile_mode
& 0x0f0) << (22 - 4)) |
333 ((mt
->level
[0].tile_mode
& 0xf00) << (25 - 8));
335 depth
= MAX2(mt
->base
.base
.array_size
, mt
->base
.base
.depth0
);
337 if (mt
->base
.base
.array_size
> 1) {
338 /* there doesn't seem to be a base layer field in TIC */
339 address
+= view
->pipe
.u
.tex
.first_layer
* mt
->layer_stride
;
340 depth
= view
->pipe
.u
.tex
.last_layer
- view
->pipe
.u
.tex
.first_layer
+ 1;
343 tic
[2] |= address
>> 32;
346 case PIPE_TEXTURE_1D
:
347 tic
[2] |= G80_TIC_2_TEXTURE_TYPE_ONE_D
;
349 case PIPE_TEXTURE_2D
:
350 tic
[2] |= G80_TIC_2_TEXTURE_TYPE_TWO_D
;
352 case PIPE_TEXTURE_RECT
:
353 tic
[2] |= G80_TIC_2_TEXTURE_TYPE_TWO_D
;
355 case PIPE_TEXTURE_3D
:
356 tic
[2] |= G80_TIC_2_TEXTURE_TYPE_THREE_D
;
358 case PIPE_TEXTURE_CUBE
:
360 tic
[2] |= G80_TIC_2_TEXTURE_TYPE_CUBEMAP
;
362 case PIPE_TEXTURE_1D_ARRAY
:
363 tic
[2] |= G80_TIC_2_TEXTURE_TYPE_ONE_D_ARRAY
;
365 case PIPE_TEXTURE_2D_ARRAY
:
366 tic
[2] |= G80_TIC_2_TEXTURE_TYPE_TWO_D_ARRAY
;
368 case PIPE_TEXTURE_CUBE_ARRAY
:
370 tic
[2] |= G80_TIC_2_TEXTURE_TYPE_CUBE_ARRAY
;
373 unreachable("unexpected/invalid texture target");
376 tic
[3] = (flags
& NV50_TEXVIEW_FILTER_MSAA8
) ? 0x20000000 : 0x00300000;
378 if (flags
& NV50_TEXVIEW_ACCESS_RESOLVE
) {
379 width
= mt
->base
.base
.width0
<< mt
->ms_x
;
380 height
= mt
->base
.base
.height0
<< mt
->ms_y
;
382 width
= mt
->base
.base
.width0
;
383 height
= mt
->base
.base
.height0
;
386 tic
[4] = (1 << 31) | width
;
388 tic
[5] = height
& 0xffff;
389 tic
[5] |= depth
<< 16;
390 tic
[5] |= mt
->base
.base
.last_level
<< 28;
392 /* sampling points: (?) */
393 if (flags
& NV50_TEXVIEW_ACCESS_RESOLVE
)
394 tic
[6] = (mt
->ms_x
> 1) ? 0x88000000 : 0x03000000;
398 tic
[7] = (view
->pipe
.u
.tex
.last_level
<< 4) | view
->pipe
.u
.tex
.first_level
;
399 tic
[7] |= mt
->ms_mode
<< 12;
404 struct pipe_sampler_view
*
405 nvc0_create_texture_view(struct pipe_context
*pipe
,
406 struct pipe_resource
*texture
,
407 const struct pipe_sampler_view
*templ
,
409 enum pipe_texture_target target
)
411 if (nvc0_context(pipe
)->screen
->tic
.maxwell
)
412 return gm107_create_texture_view(pipe
, texture
, templ
, flags
, target
);
413 return gf100_create_texture_view(pipe
, texture
, templ
, flags
, target
);
417 nvc0_update_tic(struct nvc0_context
*nvc0
, struct nv50_tic_entry
*tic
,
418 struct nv04_resource
*res
)
420 uint64_t address
= res
->address
;
421 if (res
->base
.target
!= PIPE_BUFFER
)
423 address
+= tic
->pipe
.u
.buf
.first_element
*
424 util_format_get_blocksize(tic
->pipe
.format
);
425 if (tic
->tic
[1] == (uint32_t)address
&&
426 (tic
->tic
[2] & 0xff) == address
>> 32)
429 nvc0_screen_tic_unlock(nvc0
->screen
, tic
);
431 tic
->tic
[1] = address
;
432 tic
->tic
[2] &= 0xffffff00;
433 tic
->tic
[2] |= address
>> 32;
437 nvc0_validate_tic(struct nvc0_context
*nvc0
, int s
)
439 uint32_t commands
[32];
440 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
441 struct nouveau_bo
*txc
= nvc0
->screen
->txc
;
444 bool need_flush
= false;
446 for (i
= 0; i
< nvc0
->num_textures
[s
]; ++i
) {
447 struct nv50_tic_entry
*tic
= nv50_tic_entry(nvc0
->textures
[s
][i
]);
448 struct nv04_resource
*res
;
449 const bool dirty
= !!(nvc0
->textures_dirty
[s
] & (1 << i
));
453 commands
[n
++] = (i
<< 1) | 0;
456 res
= nv04_resource(tic
->pipe
.texture
);
457 nvc0_update_tic(nvc0
, tic
, res
);
460 tic
->id
= nvc0_screen_tic_alloc(nvc0
->screen
, tic
);
462 PUSH_SPACE(push
, 17);
463 BEGIN_NVC0(push
, NVC0_M2MF(OFFSET_OUT_HIGH
), 2);
464 PUSH_DATAh(push
, txc
->offset
+ (tic
->id
* 32));
465 PUSH_DATA (push
, txc
->offset
+ (tic
->id
* 32));
466 BEGIN_NVC0(push
, NVC0_M2MF(LINE_LENGTH_IN
), 2);
467 PUSH_DATA (push
, 32);
469 BEGIN_NVC0(push
, NVC0_M2MF(EXEC
), 1);
470 PUSH_DATA (push
, 0x100111);
471 BEGIN_NIC0(push
, NVC0_M2MF(DATA
), 8);
472 PUSH_DATAp(push
, &tic
->tic
[0], 8);
476 if (res
->status
& NOUVEAU_BUFFER_STATUS_GPU_WRITING
) {
477 if (unlikely(s
== 5))
478 BEGIN_NVC0(push
, NVC0_CP(TEX_CACHE_CTL
), 1);
480 BEGIN_NVC0(push
, NVC0_3D(TEX_CACHE_CTL
), 1);
481 PUSH_DATA (push
, (tic
->id
<< 4) | 1);
482 NOUVEAU_DRV_STAT(&nvc0
->screen
->base
, tex_cache_flush_count
, 1);
484 nvc0
->screen
->tic
.lock
[tic
->id
/ 32] |= 1 << (tic
->id
% 32);
486 res
->status
&= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING
;
487 res
->status
|= NOUVEAU_BUFFER_STATUS_GPU_READING
;
491 commands
[n
++] = (tic
->id
<< 9) | (i
<< 1) | 1;
493 if (unlikely(s
== 5))
494 BCTX_REFN(nvc0
->bufctx_cp
, CP_TEX(i
), res
, RD
);
496 BCTX_REFN(nvc0
->bufctx_3d
, 3D_TEX(s
, i
), res
, RD
);
498 for (; i
< nvc0
->state
.num_textures
[s
]; ++i
)
499 commands
[n
++] = (i
<< 1) | 0;
501 nvc0
->state
.num_textures
[s
] = nvc0
->num_textures
[s
];
504 if (unlikely(s
== 5))
505 BEGIN_NIC0(push
, NVC0_CP(BIND_TIC
), n
);
507 BEGIN_NIC0(push
, NVC0_3D(BIND_TIC(s
)), n
);
508 PUSH_DATAp(push
, commands
, n
);
510 nvc0
->textures_dirty
[s
] = 0;
516 nve4_validate_tic(struct nvc0_context
*nvc0
, unsigned s
)
518 struct nouveau_bo
*txc
= nvc0
->screen
->txc
;
519 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
521 bool need_flush
= false;
523 for (i
= 0; i
< nvc0
->num_textures
[s
]; ++i
) {
524 struct nv50_tic_entry
*tic
= nv50_tic_entry(nvc0
->textures
[s
][i
]);
525 struct nv04_resource
*res
;
526 const bool dirty
= !!(nvc0
->textures_dirty
[s
] & (1 << i
));
529 nvc0
->tex_handles
[s
][i
] |= NVE4_TIC_ENTRY_INVALID
;
532 res
= nv04_resource(tic
->pipe
.texture
);
533 nvc0_update_tic(nvc0
, tic
, res
);
536 tic
->id
= nvc0_screen_tic_alloc(nvc0
->screen
, tic
);
538 PUSH_SPACE(push
, 16);
539 BEGIN_NVC0(push
, NVE4_P2MF(UPLOAD_DST_ADDRESS_HIGH
), 2);
540 PUSH_DATAh(push
, txc
->offset
+ (tic
->id
* 32));
541 PUSH_DATA (push
, txc
->offset
+ (tic
->id
* 32));
542 BEGIN_NVC0(push
, NVE4_P2MF(UPLOAD_LINE_LENGTH_IN
), 2);
543 PUSH_DATA (push
, 32);
545 BEGIN_1IC0(push
, NVE4_P2MF(UPLOAD_EXEC
), 9);
546 PUSH_DATA (push
, 0x1001);
547 PUSH_DATAp(push
, &tic
->tic
[0], 8);
551 if (res
->status
& NOUVEAU_BUFFER_STATUS_GPU_WRITING
) {
552 BEGIN_NVC0(push
, NVC0_3D(TEX_CACHE_CTL
), 1);
553 PUSH_DATA (push
, (tic
->id
<< 4) | 1);
555 nvc0
->screen
->tic
.lock
[tic
->id
/ 32] |= 1 << (tic
->id
% 32);
557 res
->status
&= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING
;
558 res
->status
|= NOUVEAU_BUFFER_STATUS_GPU_READING
;
560 nvc0
->tex_handles
[s
][i
] &= ~NVE4_TIC_ENTRY_INVALID
;
561 nvc0
->tex_handles
[s
][i
] |= tic
->id
;
563 BCTX_REFN(nvc0
->bufctx_3d
, 3D_TEX(s
, i
), res
, RD
);
565 for (; i
< nvc0
->state
.num_textures
[s
]; ++i
) {
566 nvc0
->tex_handles
[s
][i
] |= NVE4_TIC_ENTRY_INVALID
;
567 nvc0
->textures_dirty
[s
] |= 1 << i
;
570 nvc0
->state
.num_textures
[s
] = nvc0
->num_textures
[s
];
575 void nvc0_validate_textures(struct nvc0_context
*nvc0
)
577 bool need_flush
= false;
580 for (i
= 0; i
< 5; i
++) {
581 if (nvc0
->screen
->base
.class_3d
>= NVE4_3D_CLASS
)
582 need_flush
|= nve4_validate_tic(nvc0
, i
);
584 need_flush
|= nvc0_validate_tic(nvc0
, i
);
588 BEGIN_NVC0(nvc0
->base
.pushbuf
, NVC0_3D(TIC_FLUSH
), 1);
589 PUSH_DATA (nvc0
->base
.pushbuf
, 0);
592 if (nvc0
->screen
->base
.class_3d
< NVE4_3D_CLASS
) {
593 /* Invalidate all CP textures because they are aliased. */
594 for (int i
= 0; i
< nvc0
->num_textures
[5]; i
++)
595 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_CP_TEX(i
));
596 nvc0
->textures_dirty
[5] = ~0;
597 nvc0
->dirty_cp
|= NVC0_NEW_CP_TEXTURES
;
602 nvc0_validate_tsc(struct nvc0_context
*nvc0
, int s
)
604 uint32_t commands
[16];
605 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
608 bool need_flush
= false;
610 for (i
= 0; i
< nvc0
->num_samplers
[s
]; ++i
) {
611 struct nv50_tsc_entry
*tsc
= nv50_tsc_entry(nvc0
->samplers
[s
][i
]);
613 if (!(nvc0
->samplers_dirty
[s
] & (1 << i
)))
616 commands
[n
++] = (i
<< 4) | 0;
619 nvc0
->seamless_cube_map
= tsc
->seamless_cube_map
;
621 tsc
->id
= nvc0_screen_tsc_alloc(nvc0
->screen
, tsc
);
623 nvc0_m2mf_push_linear(&nvc0
->base
, nvc0
->screen
->txc
,
624 65536 + tsc
->id
* 32, NV_VRAM_DOMAIN(&nvc0
->screen
->base
),
628 nvc0
->screen
->tsc
.lock
[tsc
->id
/ 32] |= 1 << (tsc
->id
% 32);
630 commands
[n
++] = (tsc
->id
<< 12) | (i
<< 4) | 1;
632 for (; i
< nvc0
->state
.num_samplers
[s
]; ++i
)
633 commands
[n
++] = (i
<< 4) | 0;
635 nvc0
->state
.num_samplers
[s
] = nvc0
->num_samplers
[s
];
638 if (unlikely(s
== 5))
639 BEGIN_NIC0(push
, NVC0_CP(BIND_TSC
), n
);
641 BEGIN_NIC0(push
, NVC0_3D(BIND_TSC(s
)), n
);
642 PUSH_DATAp(push
, commands
, n
);
644 nvc0
->samplers_dirty
[s
] = 0;
650 nve4_validate_tsc(struct nvc0_context
*nvc0
, int s
)
652 struct nouveau_bo
*txc
= nvc0
->screen
->txc
;
653 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
655 bool need_flush
= false;
657 for (i
= 0; i
< nvc0
->num_samplers
[s
]; ++i
) {
658 struct nv50_tsc_entry
*tsc
= nv50_tsc_entry(nvc0
->samplers
[s
][i
]);
661 nvc0
->tex_handles
[s
][i
] |= NVE4_TSC_ENTRY_INVALID
;
665 tsc
->id
= nvc0_screen_tsc_alloc(nvc0
->screen
, tsc
);
667 PUSH_SPACE(push
, 16);
668 BEGIN_NVC0(push
, NVE4_P2MF(UPLOAD_DST_ADDRESS_HIGH
), 2);
669 PUSH_DATAh(push
, txc
->offset
+ 65536 + (tsc
->id
* 32));
670 PUSH_DATA (push
, txc
->offset
+ 65536 + (tsc
->id
* 32));
671 BEGIN_NVC0(push
, NVE4_P2MF(UPLOAD_LINE_LENGTH_IN
), 2);
672 PUSH_DATA (push
, 32);
674 BEGIN_1IC0(push
, NVE4_P2MF(UPLOAD_EXEC
), 9);
675 PUSH_DATA (push
, 0x1001);
676 PUSH_DATAp(push
, &tsc
->tsc
[0], 8);
680 nvc0
->screen
->tsc
.lock
[tsc
->id
/ 32] |= 1 << (tsc
->id
% 32);
682 nvc0
->tex_handles
[s
][i
] &= ~NVE4_TSC_ENTRY_INVALID
;
683 nvc0
->tex_handles
[s
][i
] |= tsc
->id
<< 20;
685 for (; i
< nvc0
->state
.num_samplers
[s
]; ++i
) {
686 nvc0
->tex_handles
[s
][i
] |= NVE4_TSC_ENTRY_INVALID
;
687 nvc0
->samplers_dirty
[s
] |= 1 << i
;
690 nvc0
->state
.num_samplers
[s
] = nvc0
->num_samplers
[s
];
695 void nvc0_validate_samplers(struct nvc0_context
*nvc0
)
697 bool need_flush
= false;
700 for (i
= 0; i
< 5; i
++) {
701 if (nvc0
->screen
->base
.class_3d
>= NVE4_3D_CLASS
)
702 need_flush
|= nve4_validate_tsc(nvc0
, i
);
704 need_flush
|= nvc0_validate_tsc(nvc0
, i
);
708 BEGIN_NVC0(nvc0
->base
.pushbuf
, NVC0_3D(TSC_FLUSH
), 1);
709 PUSH_DATA (nvc0
->base
.pushbuf
, 0);
712 if (nvc0
->screen
->base
.class_3d
< NVE4_3D_CLASS
) {
713 /* Invalidate all CP samplers because they are aliased. */
714 nvc0
->samplers_dirty
[5] = ~0;
715 nvc0
->dirty_cp
|= NVC0_NEW_CP_SAMPLERS
;
719 /* Upload the "diagonal" entries for the possible texture sources ($t == $s).
720 * At some point we might want to get a list of the combinations used by a
721 * shader and fill in those entries instead of having it extract the handles.
724 nve4_set_tex_handles(struct nvc0_context
*nvc0
)
726 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
727 struct nvc0_screen
*screen
= nvc0
->screen
;
730 if (nvc0
->screen
->base
.class_3d
< NVE4_3D_CLASS
)
733 for (s
= 0; s
< 5; ++s
) {
734 uint32_t dirty
= nvc0
->textures_dirty
[s
] | nvc0
->samplers_dirty
[s
];
737 BEGIN_NVC0(push
, NVC0_3D(CB_SIZE
), 3);
738 PUSH_DATA (push
, 2048);
739 PUSH_DATAh(push
, screen
->uniform_bo
->offset
+ NVC0_CB_AUX_INFO(s
));
740 PUSH_DATA (push
, screen
->uniform_bo
->offset
+ NVC0_CB_AUX_INFO(s
));
742 int i
= ffs(dirty
) - 1;
745 BEGIN_NVC0(push
, NVC0_3D(CB_POS
), 2);
746 PUSH_DATA (push
, (8 + i
) * 4);
747 PUSH_DATA (push
, nvc0
->tex_handles
[s
][i
]);
750 nvc0
->textures_dirty
[s
] = 0;
751 nvc0
->samplers_dirty
[s
] = 0;
756 static const uint8_t nve4_su_format_map
[PIPE_FORMAT_COUNT
];
757 static const uint16_t nve4_su_format_aux_map
[PIPE_FORMAT_COUNT
];
758 static const uint16_t nve4_suldp_lib_offset
[PIPE_FORMAT_COUNT
];
761 nvc0_get_surface_dims(struct pipe_image_view
*view
, int *width
, int *height
,
764 struct nv04_resource
*res
= nv04_resource(view
->resource
);
767 *width
= *height
= *depth
= 1;
768 if (res
->base
.target
== PIPE_BUFFER
) {
769 *width
= view
->u
.buf
.last_element
- view
->u
.buf
.first_element
+ 1;
773 level
= view
->u
.tex
.level
;
774 *width
= u_minify(view
->resource
->width0
, level
);
775 *height
= u_minify(view
->resource
->height0
, level
);
776 *depth
= u_minify(view
->resource
->depth0
, level
);
778 switch (res
->base
.target
) {
779 case PIPE_TEXTURE_1D_ARRAY
:
780 case PIPE_TEXTURE_2D_ARRAY
:
781 case PIPE_TEXTURE_CUBE
:
782 case PIPE_TEXTURE_CUBE_ARRAY
:
783 *depth
= view
->u
.tex
.last_layer
- view
->u
.tex
.first_layer
+ 1;
785 case PIPE_TEXTURE_1D
:
786 case PIPE_TEXTURE_2D
:
787 case PIPE_TEXTURE_RECT
:
788 case PIPE_TEXTURE_3D
:
791 assert(!"unexpected texture target");
797 nvc0_mark_image_range_valid(const struct pipe_image_view
*view
)
799 struct nv04_resource
*res
= (struct nv04_resource
*)view
->resource
;
800 const struct util_format_description
*desc
;
803 assert(view
->resource
->target
== PIPE_BUFFER
);
805 desc
= util_format_description(view
->format
);
806 stride
= desc
->block
.bits
/ 8;
808 util_range_add(&res
->valid_buffer_range
,
809 stride
* (view
->u
.buf
.first_element
),
810 stride
* (view
->u
.buf
.last_element
+ 1));
814 nve4_set_surface_info(struct nouveau_pushbuf
*push
,
815 struct pipe_image_view
*view
,
816 struct nvc0_context
*nvc0
)
818 struct nvc0_screen
*screen
= nvc0
->screen
;
819 struct nv04_resource
*res
;
821 uint32_t *const info
= push
->cur
;
822 int width
, height
, depth
;
825 if (view
&& !nve4_su_format_map
[view
->format
])
826 NOUVEAU_ERR("unsupported surface format, try is_format_supported() !\n");
830 if (!view
|| !nve4_su_format_map
[view
->format
]) {
831 memset(info
, 0, 16 * sizeof(*info
));
833 info
[0] = 0xbadf0000;
834 info
[1] = 0x80004000;
835 info
[12] = nve4_suldp_lib_offset
[PIPE_FORMAT_R32G32B32A32_UINT
] +
836 screen
->lib_code
->start
;
839 res
= nv04_resource(view
->resource
);
841 address
= res
->address
;
843 /* get surface dimensions based on the target. */
844 nvc0_get_surface_dims(view
, &width
, &height
, &depth
);
849 switch (res
->base
.target
) {
850 case PIPE_TEXTURE_1D_ARRAY
:
853 case PIPE_TEXTURE_2D
:
854 case PIPE_TEXTURE_RECT
:
857 case PIPE_TEXTURE_3D
:
860 case PIPE_TEXTURE_2D_ARRAY
:
861 case PIPE_TEXTURE_CUBE
:
862 case PIPE_TEXTURE_CUBE_ARRAY
:
869 log2cpp
= (0xf000 & nve4_su_format_aux_map
[view
->format
]) >> 12;
871 /* Stick the blockwidth (ie. number of bytes per pixel) to check if the
872 * format doesn't mismatch. */
873 info
[12] = util_format_get_blocksize(view
->format
);
875 /* limit in bytes for raw access */
876 info
[13] = (0x06 << 22) | ((width
<< log2cpp
) - 1);
878 info
[1] = nve4_su_format_map
[view
->format
];
881 switch (util_format_get_blocksizebits(view
->format
)) {
882 case 16: info
[1] |= 1 << 16; break;
883 case 32: info
[1] |= 2 << 16; break;
884 case 64: info
[1] |= 3 << 16; break;
885 case 128: info
[1] |= 4 << 16; break;
890 info
[1] |= log2cpp
<< 16;
892 info
[1] |= (0x0f00 & nve4_su_format_aux_map
[view
->format
]);
895 if (res
->base
.target
== PIPE_BUFFER
) {
896 unsigned blocksize
= util_format_get_blocksize(view
->format
);
898 address
+= view
->u
.buf
.first_element
* blocksize
;
900 info
[0] = address
>> 8;
902 info
[2] |= (0xff & nve4_su_format_aux_map
[view
->format
]) << 22;
911 struct nv50_miptree
*mt
= nv50_miptree(&res
->base
);
912 struct nv50_miptree_level
*lvl
= &mt
->level
[view
->u
.tex
.level
];
913 const unsigned z
= view
->u
.tex
.first_layer
;
917 address
+= nvc0_mt_zslice_offset(mt
, view
->u
.tex
.level
, z
);
918 /* doesn't work if z passes z-tile boundary */
920 pipe_debug_message(&nvc0
->base
.debug
, CONFORMANCE
,
921 "3D images are not really supported!");
922 debug_printf("3D images are not really supported!\n");
925 address
+= mt
->layer_stride
* z
;
928 address
+= lvl
->offset
;
930 info
[0] = address
>> 8;
932 /* NOTE: this is really important: */
933 info
[2] |= (0xff & nve4_su_format_aux_map
[view
->format
]) << 22;
934 info
[3] = (0x88 << 24) | (lvl
->pitch
/ 64);
935 info
[4] = height
- 1;
936 info
[4] |= (lvl
->tile_mode
& 0x0f0) << 25;
937 info
[4] |= NVC0_TILE_SHIFT_Y(lvl
->tile_mode
) << 22;
938 info
[5] = mt
->layer_stride
>> 8;
940 info
[6] |= (lvl
->tile_mode
& 0xf00) << 21;
941 info
[6] |= NVC0_TILE_SHIFT_Z(lvl
->tile_mode
) << 22;
949 nvc0_set_surface_info(struct nouveau_pushbuf
*push
,
950 struct pipe_image_view
*view
, uint64_t address
,
951 int width
, int height
, int depth
)
953 struct nv04_resource
*res
;
954 uint32_t *const info
= push
->cur
;
958 /* Make sure to always initialize the surface information area because it's
959 * used to check if the given image is bound or not. */
960 memset(info
, 0, 16 * sizeof(*info
));
962 if (!view
|| !view
->resource
)
964 res
= nv04_resource(view
->resource
);
966 /* Stick the image dimensions for the imageSize() builtin. */
971 /* Stick the blockwidth (ie. number of bytes per pixel) to calculate pixel
972 * offset and to check if the format doesn't mismatch. */
973 info
[12] = util_format_get_blocksize(view
->format
);
975 if (res
->base
.target
== PIPE_BUFFER
) {
976 info
[0] = address
>> 8;
979 struct nv50_miptree
*mt
= nv50_miptree(&res
->base
);
981 info
[0] = address
>> 8;
984 info
[5] = mt
->layer_stride
>> 8;
992 nvc0_validate_suf(struct nvc0_context
*nvc0
, int s
)
994 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
995 struct nvc0_screen
*screen
= nvc0
->screen
;
997 for (int i
= 0; i
< NVC0_MAX_IMAGES
; ++i
) {
998 struct pipe_image_view
*view
= &nvc0
->images
[s
][i
];
999 int width
, height
, depth
;
1000 uint64_t address
= 0;
1003 BEGIN_NVC0(push
, NVC0_CP(IMAGE(i
)), 6);
1005 BEGIN_NVC0(push
, NVC0_3D(IMAGE(i
)), 6);
1007 if (view
->resource
) {
1008 struct nv04_resource
*res
= nv04_resource(view
->resource
);
1009 unsigned rt
= nvc0_format_table
[view
->format
].rt
;
1011 if (util_format_is_depth_or_stencil(view
->format
))
1014 rt
= (rt
<< 4) | (0x14 << 12);
1016 /* get surface dimensions based on the target. */
1017 nvc0_get_surface_dims(view
, &width
, &height
, &depth
);
1019 address
= res
->address
;
1020 if (res
->base
.target
== PIPE_BUFFER
) {
1021 unsigned blocksize
= util_format_get_blocksize(view
->format
);
1023 address
+= view
->u
.buf
.first_element
* blocksize
;
1024 assert(!(address
& 0xff));
1026 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
1027 nvc0_mark_image_range_valid(view
);
1029 PUSH_DATAh(push
, address
);
1030 PUSH_DATA (push
, address
);
1031 PUSH_DATA (push
, align(width
* blocksize
, 0x100));
1032 PUSH_DATA (push
, NVC0_3D_IMAGE_HEIGHT_LINEAR
| 1);
1033 PUSH_DATA (push
, rt
);
1034 PUSH_DATA (push
, 0);
1036 struct nv50_miptree
*mt
= nv50_miptree(view
->resource
);
1037 struct nv50_miptree_level
*lvl
= &mt
->level
[view
->u
.tex
.level
];
1038 const unsigned z
= view
->u
.tex
.first_layer
;
1040 if (mt
->layout_3d
) {
1041 address
+= nvc0_mt_zslice_offset(mt
, view
->u
.tex
.level
, z
);
1043 pipe_debug_message(&nvc0
->base
.debug
, CONFORMANCE
,
1044 "3D images are not supported!");
1045 debug_printf("3D images are not supported!\n");
1048 address
+= mt
->layer_stride
* z
;
1050 address
+= lvl
->offset
;
1052 PUSH_DATAh(push
, address
);
1053 PUSH_DATA (push
, address
);
1054 PUSH_DATA (push
, width
);
1055 PUSH_DATA (push
, height
);
1056 PUSH_DATA (push
, rt
);
1057 PUSH_DATA (push
, lvl
->tile_mode
& 0xff); /* mask out z-tiling */
1061 BCTX_REFN(nvc0
->bufctx_cp
, CP_SUF
, res
, RDWR
);
1063 BCTX_REFN(nvc0
->bufctx_3d
, 3D_SUF
, res
, RDWR
);
1069 PUSH_DATA(push
, 0x14000);
1073 /* stick surface information into the driver constant buffer */
1075 BEGIN_NVC0(push
, NVC0_CP(CB_SIZE
), 3);
1077 BEGIN_NVC0(push
, NVC0_3D(CB_SIZE
), 3);
1078 PUSH_DATA (push
, 2048);
1079 PUSH_DATAh(push
, screen
->uniform_bo
->offset
+ NVC0_CB_AUX_INFO(s
));
1080 PUSH_DATA (push
, screen
->uniform_bo
->offset
+ NVC0_CB_AUX_INFO(s
));
1082 BEGIN_1IC0(push
, NVC0_CP(CB_POS
), 1 + 16);
1084 BEGIN_1IC0(push
, NVC0_3D(CB_POS
), 1 + 16);
1085 PUSH_DATA (push
, NVC0_CB_AUX_SU_INFO(i
));
1087 nvc0_set_surface_info(push
, view
, address
, width
, height
, depth
);
1092 nvc0_update_surface_bindings(struct nvc0_context
*nvc0
)
1094 nvc0_validate_suf(nvc0
, 4);
1096 /* Invalidate all COMPUTE images because they are aliased with FRAGMENT. */
1097 nouveau_bufctx_reset(nvc0
->bufctx_cp
, NVC0_BIND_CP_SUF
);
1098 nvc0
->dirty_cp
|= NVC0_NEW_CP_SURFACES
;
1099 nvc0
->images_dirty
[5] |= nvc0
->images_valid
[5];
1103 nve4_update_surface_bindings(struct nvc0_context
*nvc0
)
1105 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
1106 struct nvc0_screen
*screen
= nvc0
->screen
;
1109 for (s
= 0; s
< 5; s
++) {
1110 if (!nvc0
->images_dirty
[s
])
1113 BEGIN_NVC0(push
, NVC0_3D(CB_SIZE
), 3);
1114 PUSH_DATA (push
, 2048);
1115 PUSH_DATAh(push
, screen
->uniform_bo
->offset
+ NVC0_CB_AUX_INFO(s
));
1116 PUSH_DATA (push
, screen
->uniform_bo
->offset
+ NVC0_CB_AUX_INFO(s
));
1117 BEGIN_1IC0(push
, NVC0_3D(CB_POS
), 1 + 16 * NVC0_MAX_IMAGES
);
1118 PUSH_DATA (push
, NVC0_CB_AUX_SU_INFO(0));
1120 for (i
= 0; i
< NVC0_MAX_IMAGES
; ++i
) {
1121 struct pipe_image_view
*view
= &nvc0
->images
[s
][i
];
1122 if (view
->resource
) {
1123 struct nv04_resource
*res
= nv04_resource(view
->resource
);
1125 if (res
->base
.target
== PIPE_BUFFER
) {
1126 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
1127 nvc0_mark_image_range_valid(view
);
1130 nve4_set_surface_info(push
, view
, nvc0
);
1131 BCTX_REFN(nvc0
->bufctx_3d
, 3D_SUF
, res
, RDWR
);
1133 for (j
= 0; j
< 16; j
++)
1141 nvc0_validate_surfaces(struct nvc0_context
*nvc0
)
1143 if (nvc0
->screen
->base
.class_3d
>= NVE4_3D_CLASS
) {
1144 nve4_update_surface_bindings(nvc0
);
1146 nvc0_update_surface_bindings(nvc0
);
1151 static const uint8_t nve4_su_format_map
[PIPE_FORMAT_COUNT
] =
1153 [PIPE_FORMAT_R32G32B32A32_FLOAT
] = GK104_IMAGE_FORMAT_RGBA32_FLOAT
,
1154 [PIPE_FORMAT_R32G32B32A32_SINT
] = GK104_IMAGE_FORMAT_RGBA32_SINT
,
1155 [PIPE_FORMAT_R32G32B32A32_UINT
] = GK104_IMAGE_FORMAT_RGBA32_UINT
,
1156 [PIPE_FORMAT_R16G16B16A16_FLOAT
] = GK104_IMAGE_FORMAT_RGBA16_FLOAT
,
1157 [PIPE_FORMAT_R16G16B16A16_UNORM
] = GK104_IMAGE_FORMAT_RGBA16_UNORM
,
1158 [PIPE_FORMAT_R16G16B16A16_SNORM
] = GK104_IMAGE_FORMAT_RGBA16_SNORM
,
1159 [PIPE_FORMAT_R16G16B16A16_SINT
] = GK104_IMAGE_FORMAT_RGBA16_SINT
,
1160 [PIPE_FORMAT_R16G16B16A16_UINT
] = GK104_IMAGE_FORMAT_RGBA16_UINT
,
1161 [PIPE_FORMAT_R8G8B8A8_UNORM
] = GK104_IMAGE_FORMAT_RGBA8_UNORM
,
1162 [PIPE_FORMAT_R8G8B8A8_SNORM
] = GK104_IMAGE_FORMAT_RGBA8_SNORM
,
1163 [PIPE_FORMAT_R8G8B8A8_SINT
] = GK104_IMAGE_FORMAT_RGBA8_SINT
,
1164 [PIPE_FORMAT_R8G8B8A8_UINT
] = GK104_IMAGE_FORMAT_RGBA8_UINT
,
1165 [PIPE_FORMAT_R11G11B10_FLOAT
] = GK104_IMAGE_FORMAT_R11G11B10_FLOAT
,
1166 [PIPE_FORMAT_R10G10B10A2_UNORM
] = GK104_IMAGE_FORMAT_RGB10_A2_UNORM
,
1167 [PIPE_FORMAT_R10G10B10A2_UINT
] = GK104_IMAGE_FORMAT_RGB10_A2_UINT
,
1168 [PIPE_FORMAT_R32G32_FLOAT
] = GK104_IMAGE_FORMAT_RG32_FLOAT
,
1169 [PIPE_FORMAT_R32G32_SINT
] = GK104_IMAGE_FORMAT_RG32_SINT
,
1170 [PIPE_FORMAT_R32G32_UINT
] = GK104_IMAGE_FORMAT_RG32_UINT
,
1171 [PIPE_FORMAT_R16G16_FLOAT
] = GK104_IMAGE_FORMAT_RG16_FLOAT
,
1172 [PIPE_FORMAT_R16G16_UNORM
] = GK104_IMAGE_FORMAT_RG16_UNORM
,
1173 [PIPE_FORMAT_R16G16_SNORM
] = GK104_IMAGE_FORMAT_RG16_SNORM
,
1174 [PIPE_FORMAT_R16G16_SINT
] = GK104_IMAGE_FORMAT_RG16_SINT
,
1175 [PIPE_FORMAT_R16G16_UINT
] = GK104_IMAGE_FORMAT_RG16_UINT
,
1176 [PIPE_FORMAT_R8G8_UNORM
] = GK104_IMAGE_FORMAT_RG8_UNORM
,
1177 [PIPE_FORMAT_R8G8_SNORM
] = GK104_IMAGE_FORMAT_RG8_SNORM
,
1178 [PIPE_FORMAT_R8G8_SINT
] = GK104_IMAGE_FORMAT_RG8_SINT
,
1179 [PIPE_FORMAT_R8G8_UINT
] = GK104_IMAGE_FORMAT_RG8_UINT
,
1180 [PIPE_FORMAT_R32_FLOAT
] = GK104_IMAGE_FORMAT_R32_FLOAT
,
1181 [PIPE_FORMAT_R32_SINT
] = GK104_IMAGE_FORMAT_R32_SINT
,
1182 [PIPE_FORMAT_R32_UINT
] = GK104_IMAGE_FORMAT_R32_UINT
,
1183 [PIPE_FORMAT_R16_FLOAT
] = GK104_IMAGE_FORMAT_R16_FLOAT
,
1184 [PIPE_FORMAT_R16_UNORM
] = GK104_IMAGE_FORMAT_R16_UNORM
,
1185 [PIPE_FORMAT_R16_SNORM
] = GK104_IMAGE_FORMAT_R16_SNORM
,
1186 [PIPE_FORMAT_R16_SINT
] = GK104_IMAGE_FORMAT_R16_SINT
,
1187 [PIPE_FORMAT_R16_UINT
] = GK104_IMAGE_FORMAT_R16_UINT
,
1188 [PIPE_FORMAT_R8_UNORM
] = GK104_IMAGE_FORMAT_R8_UNORM
,
1189 [PIPE_FORMAT_R8_SNORM
] = GK104_IMAGE_FORMAT_R8_SNORM
,
1190 [PIPE_FORMAT_R8_SINT
] = GK104_IMAGE_FORMAT_R8_SINT
,
1191 [PIPE_FORMAT_R8_UINT
] = GK104_IMAGE_FORMAT_R8_UINT
,
1194 /* Auxiliary format description values for surface instructions.
1195 * (log2(bytes per pixel) << 12) | (unk8 << 8) | unk22
1197 static const uint16_t nve4_su_format_aux_map
[PIPE_FORMAT_COUNT
] =
1199 [PIPE_FORMAT_R32G32B32A32_FLOAT
] = 0x4842,
1200 [PIPE_FORMAT_R32G32B32A32_SINT
] = 0x4842,
1201 [PIPE_FORMAT_R32G32B32A32_UINT
] = 0x4842,
1203 [PIPE_FORMAT_R16G16B16A16_UNORM
] = 0x3933,
1204 [PIPE_FORMAT_R16G16B16A16_SNORM
] = 0x3933,
1205 [PIPE_FORMAT_R16G16B16A16_SINT
] = 0x3933,
1206 [PIPE_FORMAT_R16G16B16A16_UINT
] = 0x3933,
1207 [PIPE_FORMAT_R16G16B16A16_FLOAT
] = 0x3933,
1209 [PIPE_FORMAT_R32G32_FLOAT
] = 0x3433,
1210 [PIPE_FORMAT_R32G32_SINT
] = 0x3433,
1211 [PIPE_FORMAT_R32G32_UINT
] = 0x3433,
1213 [PIPE_FORMAT_R10G10B10A2_UNORM
] = 0x2a24,
1214 [PIPE_FORMAT_R10G10B10A2_UINT
] = 0x2a24,
1215 [PIPE_FORMAT_R8G8B8A8_UNORM
] = 0x2a24,
1216 [PIPE_FORMAT_R8G8B8A8_SNORM
] = 0x2a24,
1217 [PIPE_FORMAT_R8G8B8A8_SINT
] = 0x2a24,
1218 [PIPE_FORMAT_R8G8B8A8_UINT
] = 0x2a24,
1219 [PIPE_FORMAT_R11G11B10_FLOAT
] = 0x2a24,
1221 [PIPE_FORMAT_R16G16_UNORM
] = 0x2524,
1222 [PIPE_FORMAT_R16G16_SNORM
] = 0x2524,
1223 [PIPE_FORMAT_R16G16_SINT
] = 0x2524,
1224 [PIPE_FORMAT_R16G16_UINT
] = 0x2524,
1225 [PIPE_FORMAT_R16G16_FLOAT
] = 0x2524,
1227 [PIPE_FORMAT_R32_SINT
] = 0x2024,
1228 [PIPE_FORMAT_R32_UINT
] = 0x2024,
1229 [PIPE_FORMAT_R32_FLOAT
] = 0x2024,
1231 [PIPE_FORMAT_R8G8_UNORM
] = 0x1615,
1232 [PIPE_FORMAT_R8G8_SNORM
] = 0x1615,
1233 [PIPE_FORMAT_R8G8_SINT
] = 0x1615,
1234 [PIPE_FORMAT_R8G8_UINT
] = 0x1615,
1236 [PIPE_FORMAT_R16_UNORM
] = 0x1115,
1237 [PIPE_FORMAT_R16_SNORM
] = 0x1115,
1238 [PIPE_FORMAT_R16_SINT
] = 0x1115,
1239 [PIPE_FORMAT_R16_UINT
] = 0x1115,
1240 [PIPE_FORMAT_R16_FLOAT
] = 0x1115,
1242 [PIPE_FORMAT_R8_UNORM
] = 0x0206,
1243 [PIPE_FORMAT_R8_SNORM
] = 0x0206,
1244 [PIPE_FORMAT_R8_SINT
] = 0x0206,
1245 [PIPE_FORMAT_R8_UINT
] = 0x0206
1248 /* NOTE: These are hardcoded offsets for the shader library.
1249 * TODO: Automate them.
1251 static const uint16_t nve4_suldp_lib_offset
[PIPE_FORMAT_COUNT
] =
1253 [PIPE_FORMAT_R32G32B32A32_FLOAT
] = 0x218,
1254 [PIPE_FORMAT_R32G32B32A32_SINT
] = 0x218,
1255 [PIPE_FORMAT_R32G32B32A32_UINT
] = 0x218,
1256 [PIPE_FORMAT_R16G16B16A16_UNORM
] = 0x248,
1257 [PIPE_FORMAT_R16G16B16A16_SNORM
] = 0x2b8,
1258 [PIPE_FORMAT_R16G16B16A16_SINT
] = 0x330,
1259 [PIPE_FORMAT_R16G16B16A16_UINT
] = 0x388,
1260 [PIPE_FORMAT_R16G16B16A16_FLOAT
] = 0x3d8,
1261 [PIPE_FORMAT_R32G32_FLOAT
] = 0x428,
1262 [PIPE_FORMAT_R32G32_SINT
] = 0x468,
1263 [PIPE_FORMAT_R32G32_UINT
] = 0x468,
1264 [PIPE_FORMAT_R10G10B10A2_UNORM
] = 0x4a8,
1265 [PIPE_FORMAT_R10G10B10A2_UINT
] = 0x530,
1266 [PIPE_FORMAT_R8G8B8A8_UNORM
] = 0x588,
1267 [PIPE_FORMAT_R8G8B8A8_SNORM
] = 0x5f8,
1268 [PIPE_FORMAT_R8G8B8A8_SINT
] = 0x670,
1269 [PIPE_FORMAT_R8G8B8A8_UINT
] = 0x6c8,
1270 [PIPE_FORMAT_B5G6R5_UNORM
] = 0x718,
1271 [PIPE_FORMAT_B5G5R5X1_UNORM
] = 0x7a0,
1272 [PIPE_FORMAT_R16G16_UNORM
] = 0x828,
1273 [PIPE_FORMAT_R16G16_SNORM
] = 0x890,
1274 [PIPE_FORMAT_R16G16_SINT
] = 0x8f0,
1275 [PIPE_FORMAT_R16G16_UINT
] = 0x948,
1276 [PIPE_FORMAT_R16G16_FLOAT
] = 0x998,
1277 [PIPE_FORMAT_R32_FLOAT
] = 0x9e8,
1278 [PIPE_FORMAT_R32_SINT
] = 0xa30,
1279 [PIPE_FORMAT_R32_UINT
] = 0xa30,
1280 [PIPE_FORMAT_R8G8_UNORM
] = 0xa78,
1281 [PIPE_FORMAT_R8G8_SNORM
] = 0xae0,
1282 [PIPE_FORMAT_R8G8_UINT
] = 0xb48,
1283 [PIPE_FORMAT_R8G8_SINT
] = 0xb98,
1284 [PIPE_FORMAT_R16_UNORM
] = 0xbe8,
1285 [PIPE_FORMAT_R16_SNORM
] = 0xc48,
1286 [PIPE_FORMAT_R16_SINT
] = 0xca0,
1287 [PIPE_FORMAT_R16_UINT
] = 0xce8,
1288 [PIPE_FORMAT_R16_FLOAT
] = 0xd30,
1289 [PIPE_FORMAT_R8_UNORM
] = 0xd88,
1290 [PIPE_FORMAT_R8_SNORM
] = 0xde0,
1291 [PIPE_FORMAT_R8_SINT
] = 0xe38,
1292 [PIPE_FORMAT_R8_UINT
] = 0xe88,
1293 [PIPE_FORMAT_R11G11B10_FLOAT
] = 0xed0