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df10a74218609d3ccd853141998a36ba400aee86
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_tex.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "nvc0/nvc0_context.h"
24 #include "nvc0/nvc0_resource.h"
25 #include "nvc0/gm107_texture.xml.h"
26 #include "nvc0/nvc0_compute.xml.h"
27 #include "nv50/g80_texture.xml.h"
28 #include "nv50/g80_defs.xml.h"
29
30 #include "util/u_format.h"
31
32 #define NVE4_TIC_ENTRY_INVALID 0x000fffff
33 #define NVE4_TSC_ENTRY_INVALID 0xfff00000
34
35 static inline uint32_t
36 nv50_tic_swizzle(const struct nvc0_format *fmt, unsigned swz, bool tex_int)
37 {
38 switch (swz) {
39 case PIPE_SWIZZLE_RED : return fmt->tic.src_x;
40 case PIPE_SWIZZLE_GREEN: return fmt->tic.src_y;
41 case PIPE_SWIZZLE_BLUE : return fmt->tic.src_z;
42 case PIPE_SWIZZLE_ALPHA: return fmt->tic.src_w;
43 case PIPE_SWIZZLE_ONE:
44 return tex_int ? G80_TIC_SOURCE_ONE_INT : G80_TIC_SOURCE_ONE_FLOAT;
45 case PIPE_SWIZZLE_ZERO:
46 default:
47 return G80_TIC_SOURCE_ZERO;
48 }
49 }
50
51 struct pipe_sampler_view *
52 nvc0_create_sampler_view(struct pipe_context *pipe,
53 struct pipe_resource *res,
54 const struct pipe_sampler_view *templ)
55 {
56 uint32_t flags = 0;
57
58 if (templ->target == PIPE_TEXTURE_RECT || templ->target == PIPE_BUFFER)
59 flags |= NV50_TEXVIEW_SCALED_COORDS;
60
61 return nvc0_create_texture_view(pipe, res, templ, flags, templ->target);
62 }
63
64 static struct pipe_sampler_view *
65 gm107_create_texture_view(struct pipe_context *pipe,
66 struct pipe_resource *texture,
67 const struct pipe_sampler_view *templ,
68 uint32_t flags,
69 enum pipe_texture_target target)
70 {
71 const struct util_format_description *desc;
72 const struct nvc0_format *fmt;
73 uint64_t address;
74 uint32_t *tic;
75 uint32_t swz[4];
76 uint32_t width, height;
77 uint32_t depth;
78 struct nv50_tic_entry *view;
79 struct nv50_miptree *mt;
80 bool tex_int;
81
82 view = MALLOC_STRUCT(nv50_tic_entry);
83 if (!view)
84 return NULL;
85 mt = nv50_miptree(texture);
86
87 view->pipe = *templ;
88 view->pipe.reference.count = 1;
89 view->pipe.texture = NULL;
90 view->pipe.context = pipe;
91
92 view->id = -1;
93
94 pipe_resource_reference(&view->pipe.texture, texture);
95
96 tic = &view->tic[0];
97
98 desc = util_format_description(view->pipe.format);
99 tex_int = util_format_is_pure_integer(view->pipe.format);
100
101 fmt = &nvc0_format_table[view->pipe.format];
102 swz[0] = nv50_tic_swizzle(fmt, view->pipe.swizzle_r, tex_int);
103 swz[1] = nv50_tic_swizzle(fmt, view->pipe.swizzle_g, tex_int);
104 swz[2] = nv50_tic_swizzle(fmt, view->pipe.swizzle_b, tex_int);
105 swz[3] = nv50_tic_swizzle(fmt, view->pipe.swizzle_a, tex_int);
106
107 tic[0] = fmt->tic.format << GM107_TIC2_0_COMPONENTS_SIZES__SHIFT;
108 tic[0] |= fmt->tic.type_r << GM107_TIC2_0_R_DATA_TYPE__SHIFT;
109 tic[0] |= fmt->tic.type_g << GM107_TIC2_0_G_DATA_TYPE__SHIFT;
110 tic[0] |= fmt->tic.type_b << GM107_TIC2_0_B_DATA_TYPE__SHIFT;
111 tic[0] |= fmt->tic.type_a << GM107_TIC2_0_A_DATA_TYPE__SHIFT;
112 tic[0] |= swz[0] << GM107_TIC2_0_X_SOURCE__SHIFT;
113 tic[0] |= swz[1] << GM107_TIC2_0_Y_SOURCE__SHIFT;
114 tic[0] |= swz[2] << GM107_TIC2_0_Z_SOURCE__SHIFT;
115 tic[0] |= swz[3] << GM107_TIC2_0_W_SOURCE__SHIFT;
116
117 address = mt->base.address;
118
119 tic[3] = GM107_TIC2_3_LOD_ANISO_QUALITY_2;
120 tic[4] = GM107_TIC2_4_SECTOR_PROMOTION_PROMOTE_TO_2_V;
121 tic[4] |= GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR;
122
123 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
124 tic[4] |= GM107_TIC2_4_SRGB_CONVERSION;
125
126 if (!(flags & NV50_TEXVIEW_SCALED_COORDS))
127 tic[5] = GM107_TIC2_5_NORMALIZED_COORDS;
128 else
129 tic[5] = 0;
130
131 /* check for linear storage type */
132 if (unlikely(!nouveau_bo_memtype(nv04_resource(texture)->bo))) {
133 if (texture->target == PIPE_BUFFER) {
134 assert(!(tic[5] & GM107_TIC2_5_NORMALIZED_COORDS));
135 width = view->pipe.u.buf.last_element - view->pipe.u.buf.first_element;
136 address +=
137 view->pipe.u.buf.first_element * desc->block.bits / 8;
138 tic[2] = GM107_TIC2_2_HEADER_VERSION_ONE_D_BUFFER;
139 tic[3] |= width >> 16;
140 tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_ONE_D_BUFFER;
141 tic[4] |= width & 0xffff;
142 } else {
143 assert(!(mt->level[0].pitch & 0x1f));
144 /* must be 2D texture without mip maps */
145 tic[2] = GM107_TIC2_2_HEADER_VERSION_PITCH;
146 tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP;
147 tic[3] |= mt->level[0].pitch >> 5;
148 tic[4] |= mt->base.base.width0 - 1;
149 tic[5] |= 0 << GM107_TIC2_5_DEPTH_MINUS_ONE__SHIFT;
150 tic[5] |= mt->base.base.height0 - 1;
151 }
152 tic[1] = address;
153 tic[2] |= address >> 32;
154 tic[6] = 0;
155 tic[7] = 0;
156 return &view->pipe;
157 }
158
159 tic[2] = GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR;
160 tic[3] |=
161 ((mt->level[0].tile_mode & 0x0f0) >> 4 << 3) |
162 ((mt->level[0].tile_mode & 0xf00) >> 8 << 6);
163
164 depth = MAX2(mt->base.base.array_size, mt->base.base.depth0);
165
166 if (mt->base.base.array_size > 1) {
167 /* there doesn't seem to be a base layer field in TIC */
168 address += view->pipe.u.tex.first_layer * mt->layer_stride;
169 depth = view->pipe.u.tex.last_layer - view->pipe.u.tex.first_layer + 1;
170 }
171 tic[1] = address;
172 tic[2] |= address >> 32;
173
174 switch (target) {
175 case PIPE_TEXTURE_1D:
176 tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_ONE_D;
177 break;
178 case PIPE_TEXTURE_2D:
179 tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D;
180 break;
181 case PIPE_TEXTURE_RECT:
182 tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D;
183 break;
184 case PIPE_TEXTURE_3D:
185 tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_THREE_D;
186 break;
187 case PIPE_TEXTURE_CUBE:
188 depth /= 6;
189 tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_CUBEMAP;
190 break;
191 case PIPE_TEXTURE_1D_ARRAY:
192 tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_ONE_D_ARRAY;
193 break;
194 case PIPE_TEXTURE_2D_ARRAY:
195 tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D_ARRAY;
196 break;
197 case PIPE_TEXTURE_CUBE_ARRAY:
198 depth /= 6;
199 tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_CUBE_ARRAY;
200 break;
201 default:
202 unreachable("unexpected/invalid texture target");
203 }
204
205 tic[3] |= (flags & NV50_TEXVIEW_FILTER_MSAA8) ?
206 GM107_TIC2_3_USE_HEADER_OPT_CONTROL :
207 GM107_TIC2_3_LOD_ANISO_QUALITY_HIGH |
208 GM107_TIC2_3_LOD_ISO_QUALITY_HIGH;
209
210 if (flags & NV50_TEXVIEW_ACCESS_RESOLVE) {
211 width = mt->base.base.width0 << mt->ms_x;
212 height = mt->base.base.height0 << mt->ms_y;
213 } else {
214 width = mt->base.base.width0;
215 height = mt->base.base.height0;
216 }
217
218 tic[4] |= width - 1;
219
220 tic[5] |= (height - 1) & 0xffff;
221 tic[5] |= (depth - 1) << GM107_TIC2_5_DEPTH_MINUS_ONE__SHIFT;
222 tic[3] |= mt->base.base.last_level << GM107_TIC2_3_MAX_MIP_LEVEL__SHIFT;
223
224 /* sampling points: (?) */
225 if ((flags & NV50_TEXVIEW_ACCESS_RESOLVE) && mt->ms_x > 1) {
226 tic[6] = GM107_TIC2_6_ANISO_FINE_SPREAD_MODIFIER_CONST_TWO;
227 tic[6] |= GM107_TIC2_6_MAX_ANISOTROPY_2_TO_1;
228 } else {
229 tic[6] = GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_TWO;
230 tic[6] |= GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_ONE;
231 }
232
233 tic[7] = (view->pipe.u.tex.last_level << 4) | view->pipe.u.tex.first_level;
234 tic[7] |= mt->ms_mode << GM107_TIC2_7_MULTI_SAMPLE_COUNT__SHIFT;
235
236 return &view->pipe;
237 }
238
239 static struct pipe_sampler_view *
240 gf100_create_texture_view(struct pipe_context *pipe,
241 struct pipe_resource *texture,
242 const struct pipe_sampler_view *templ,
243 uint32_t flags,
244 enum pipe_texture_target target)
245 {
246 const struct util_format_description *desc;
247 const struct nvc0_format *fmt;
248 uint64_t address;
249 uint32_t *tic;
250 uint32_t swz[4];
251 uint32_t width, height;
252 uint32_t depth;
253 struct nv50_tic_entry *view;
254 struct nv50_miptree *mt;
255 bool tex_int;
256
257 view = MALLOC_STRUCT(nv50_tic_entry);
258 if (!view)
259 return NULL;
260 mt = nv50_miptree(texture);
261
262 view->pipe = *templ;
263 view->pipe.reference.count = 1;
264 view->pipe.texture = NULL;
265 view->pipe.context = pipe;
266
267 view->id = -1;
268
269 pipe_resource_reference(&view->pipe.texture, texture);
270
271 tic = &view->tic[0];
272
273 desc = util_format_description(view->pipe.format);
274
275 fmt = &nvc0_format_table[view->pipe.format];
276
277 tex_int = util_format_is_pure_integer(view->pipe.format);
278
279 swz[0] = nv50_tic_swizzle(fmt, view->pipe.swizzle_r, tex_int);
280 swz[1] = nv50_tic_swizzle(fmt, view->pipe.swizzle_g, tex_int);
281 swz[2] = nv50_tic_swizzle(fmt, view->pipe.swizzle_b, tex_int);
282 swz[3] = nv50_tic_swizzle(fmt, view->pipe.swizzle_a, tex_int);
283 tic[0] = (fmt->tic.format << G80_TIC_0_COMPONENTS_SIZES__SHIFT) |
284 (fmt->tic.type_r << G80_TIC_0_R_DATA_TYPE__SHIFT) |
285 (fmt->tic.type_g << G80_TIC_0_G_DATA_TYPE__SHIFT) |
286 (fmt->tic.type_b << G80_TIC_0_B_DATA_TYPE__SHIFT) |
287 (fmt->tic.type_a << G80_TIC_0_A_DATA_TYPE__SHIFT) |
288 (swz[0] << G80_TIC_0_X_SOURCE__SHIFT) |
289 (swz[1] << G80_TIC_0_Y_SOURCE__SHIFT) |
290 (swz[2] << G80_TIC_0_Z_SOURCE__SHIFT) |
291 (swz[3] << G80_TIC_0_W_SOURCE__SHIFT);
292
293 address = mt->base.address;
294
295 tic[2] = 0x10001000 | G80_TIC_2_BORDER_SOURCE_COLOR;
296
297 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
298 tic[2] |= G80_TIC_2_SRGB_CONVERSION;
299
300 if (!(flags & NV50_TEXVIEW_SCALED_COORDS))
301 tic[2] |= G80_TIC_2_NORMALIZED_COORDS;
302
303 /* check for linear storage type */
304 if (unlikely(!nouveau_bo_memtype(nv04_resource(texture)->bo))) {
305 if (texture->target == PIPE_BUFFER) {
306 assert(!(tic[2] & G80_TIC_2_NORMALIZED_COORDS));
307 address +=
308 view->pipe.u.buf.first_element * desc->block.bits / 8;
309 tic[2] |= G80_TIC_2_LAYOUT_PITCH | G80_TIC_2_TEXTURE_TYPE_ONE_D_BUFFER;
310 tic[3] = 0;
311 tic[4] = /* width */
312 view->pipe.u.buf.last_element - view->pipe.u.buf.first_element + 1;
313 tic[5] = 0;
314 } else {
315 /* must be 2D texture without mip maps */
316 tic[2] |= G80_TIC_2_LAYOUT_PITCH | G80_TIC_2_TEXTURE_TYPE_TWO_D_NO_MIPMAP;
317 tic[3] = mt->level[0].pitch;
318 tic[4] = mt->base.base.width0;
319 tic[5] = (1 << 16) | mt->base.base.height0;
320 }
321 tic[6] =
322 tic[7] = 0;
323 tic[1] = address;
324 tic[2] |= address >> 32;
325 return &view->pipe;
326 }
327
328 tic[2] |=
329 ((mt->level[0].tile_mode & 0x0f0) << (22 - 4)) |
330 ((mt->level[0].tile_mode & 0xf00) << (25 - 8));
331
332 depth = MAX2(mt->base.base.array_size, mt->base.base.depth0);
333
334 if (mt->base.base.array_size > 1) {
335 /* there doesn't seem to be a base layer field in TIC */
336 address += view->pipe.u.tex.first_layer * mt->layer_stride;
337 depth = view->pipe.u.tex.last_layer - view->pipe.u.tex.first_layer + 1;
338 }
339 tic[1] = address;
340 tic[2] |= address >> 32;
341
342 switch (target) {
343 case PIPE_TEXTURE_1D:
344 tic[2] |= G80_TIC_2_TEXTURE_TYPE_ONE_D;
345 break;
346 case PIPE_TEXTURE_2D:
347 tic[2] |= G80_TIC_2_TEXTURE_TYPE_TWO_D;
348 break;
349 case PIPE_TEXTURE_RECT:
350 tic[2] |= G80_TIC_2_TEXTURE_TYPE_TWO_D;
351 break;
352 case PIPE_TEXTURE_3D:
353 tic[2] |= G80_TIC_2_TEXTURE_TYPE_THREE_D;
354 break;
355 case PIPE_TEXTURE_CUBE:
356 depth /= 6;
357 tic[2] |= G80_TIC_2_TEXTURE_TYPE_CUBEMAP;
358 break;
359 case PIPE_TEXTURE_1D_ARRAY:
360 tic[2] |= G80_TIC_2_TEXTURE_TYPE_ONE_D_ARRAY;
361 break;
362 case PIPE_TEXTURE_2D_ARRAY:
363 tic[2] |= G80_TIC_2_TEXTURE_TYPE_TWO_D_ARRAY;
364 break;
365 case PIPE_TEXTURE_CUBE_ARRAY:
366 depth /= 6;
367 tic[2] |= G80_TIC_2_TEXTURE_TYPE_CUBE_ARRAY;
368 break;
369 default:
370 unreachable("unexpected/invalid texture target");
371 }
372
373 tic[3] = (flags & NV50_TEXVIEW_FILTER_MSAA8) ? 0x20000000 : 0x00300000;
374
375 if (flags & NV50_TEXVIEW_ACCESS_RESOLVE) {
376 width = mt->base.base.width0 << mt->ms_x;
377 height = mt->base.base.height0 << mt->ms_y;
378 } else {
379 width = mt->base.base.width0;
380 height = mt->base.base.height0;
381 }
382
383 tic[4] = (1 << 31) | width;
384
385 tic[5] = height & 0xffff;
386 tic[5] |= depth << 16;
387 tic[5] |= mt->base.base.last_level << 28;
388
389 /* sampling points: (?) */
390 if (flags & NV50_TEXVIEW_ACCESS_RESOLVE)
391 tic[6] = (mt->ms_x > 1) ? 0x88000000 : 0x03000000;
392 else
393 tic[6] = 0x03000000;
394
395 tic[7] = (view->pipe.u.tex.last_level << 4) | view->pipe.u.tex.first_level;
396 tic[7] |= mt->ms_mode << 12;
397
398 return &view->pipe;
399 }
400
401 struct pipe_sampler_view *
402 nvc0_create_texture_view(struct pipe_context *pipe,
403 struct pipe_resource *texture,
404 const struct pipe_sampler_view *templ,
405 uint32_t flags,
406 enum pipe_texture_target target)
407 {
408 if (nvc0_context(pipe)->screen->tic.maxwell)
409 return gm107_create_texture_view(pipe, texture, templ, flags, target);
410 return gf100_create_texture_view(pipe, texture, templ, flags, target);
411 }
412
413 static void
414 nvc0_update_tic(struct nvc0_context *nvc0, struct nv50_tic_entry *tic,
415 struct nv04_resource *res)
416 {
417 uint64_t address = res->address;
418 if (res->base.target != PIPE_BUFFER)
419 return;
420 address += tic->pipe.u.buf.first_element *
421 util_format_get_blocksize(tic->pipe.format);
422 if (tic->tic[1] == (uint32_t)address &&
423 (tic->tic[2] & 0xff) == address >> 32)
424 return;
425
426 nvc0_screen_tic_unlock(nvc0->screen, tic);
427 tic->id = -1;
428 tic->tic[1] = address;
429 tic->tic[2] &= 0xffffff00;
430 tic->tic[2] |= address >> 32;
431 }
432
433 bool
434 nvc0_validate_tic(struct nvc0_context *nvc0, int s)
435 {
436 uint32_t commands[32];
437 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
438 struct nouveau_bo *txc = nvc0->screen->txc;
439 unsigned i;
440 unsigned n = 0;
441 bool need_flush = false;
442
443 for (i = 0; i < nvc0->num_textures[s]; ++i) {
444 struct nv50_tic_entry *tic = nv50_tic_entry(nvc0->textures[s][i]);
445 struct nv04_resource *res;
446 const bool dirty = !!(nvc0->textures_dirty[s] & (1 << i));
447
448 if (!tic) {
449 if (dirty)
450 commands[n++] = (i << 1) | 0;
451 continue;
452 }
453 res = nv04_resource(tic->pipe.texture);
454 nvc0_update_tic(nvc0, tic, res);
455
456 if (tic->id < 0) {
457 tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
458
459 PUSH_SPACE(push, 17);
460 BEGIN_NVC0(push, NVC0_M2MF(OFFSET_OUT_HIGH), 2);
461 PUSH_DATAh(push, txc->offset + (tic->id * 32));
462 PUSH_DATA (push, txc->offset + (tic->id * 32));
463 BEGIN_NVC0(push, NVC0_M2MF(LINE_LENGTH_IN), 2);
464 PUSH_DATA (push, 32);
465 PUSH_DATA (push, 1);
466 BEGIN_NVC0(push, NVC0_M2MF(EXEC), 1);
467 PUSH_DATA (push, 0x100111);
468 BEGIN_NIC0(push, NVC0_M2MF(DATA), 8);
469 PUSH_DATAp(push, &tic->tic[0], 8);
470
471 need_flush = true;
472 } else
473 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
474 if (unlikely(s == 5))
475 BEGIN_NVC0(push, NVC0_COMPUTE(TEX_CACHE_CTL), 1);
476 else
477 BEGIN_NVC0(push, NVC0_3D(TEX_CACHE_CTL), 1);
478 PUSH_DATA (push, (tic->id << 4) | 1);
479 NOUVEAU_DRV_STAT(&nvc0->screen->base, tex_cache_flush_count, 1);
480 }
481 nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
482
483 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
484 res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
485
486 if (!dirty)
487 continue;
488 commands[n++] = (tic->id << 9) | (i << 1) | 1;
489
490 if (unlikely(s == 5))
491 BCTX_REFN(nvc0->bufctx_cp, CP_TEX(i), res, RD);
492 else
493 BCTX_REFN(nvc0->bufctx_3d, TEX(s, i), res, RD);
494 }
495 for (; i < nvc0->state.num_textures[s]; ++i)
496 commands[n++] = (i << 1) | 0;
497
498 nvc0->state.num_textures[s] = nvc0->num_textures[s];
499
500 if (n) {
501 if (unlikely(s == 5))
502 BEGIN_NIC0(push, NVC0_COMPUTE(BIND_TIC), n);
503 else
504 BEGIN_NIC0(push, NVC0_3D(BIND_TIC(s)), n);
505 PUSH_DATAp(push, commands, n);
506 }
507 nvc0->textures_dirty[s] = 0;
508
509 return need_flush;
510 }
511
512 static bool
513 nve4_validate_tic(struct nvc0_context *nvc0, unsigned s)
514 {
515 struct nouveau_bo *txc = nvc0->screen->txc;
516 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
517 unsigned i;
518 bool need_flush = false;
519
520 for (i = 0; i < nvc0->num_textures[s]; ++i) {
521 struct nv50_tic_entry *tic = nv50_tic_entry(nvc0->textures[s][i]);
522 struct nv04_resource *res;
523 const bool dirty = !!(nvc0->textures_dirty[s] & (1 << i));
524
525 if (!tic) {
526 nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID;
527 continue;
528 }
529 res = nv04_resource(tic->pipe.texture);
530 nvc0_update_tic(nvc0, tic, res);
531
532 if (tic->id < 0) {
533 tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
534
535 PUSH_SPACE(push, 16);
536 BEGIN_NVC0(push, NVE4_P2MF(UPLOAD_DST_ADDRESS_HIGH), 2);
537 PUSH_DATAh(push, txc->offset + (tic->id * 32));
538 PUSH_DATA (push, txc->offset + (tic->id * 32));
539 BEGIN_NVC0(push, NVE4_P2MF(UPLOAD_LINE_LENGTH_IN), 2);
540 PUSH_DATA (push, 32);
541 PUSH_DATA (push, 1);
542 BEGIN_1IC0(push, NVE4_P2MF(UPLOAD_EXEC), 9);
543 PUSH_DATA (push, 0x1001);
544 PUSH_DATAp(push, &tic->tic[0], 8);
545
546 need_flush = true;
547 } else
548 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
549 BEGIN_NVC0(push, NVC0_3D(TEX_CACHE_CTL), 1);
550 PUSH_DATA (push, (tic->id << 4) | 1);
551 }
552 nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
553
554 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
555 res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
556
557 nvc0->tex_handles[s][i] &= ~NVE4_TIC_ENTRY_INVALID;
558 nvc0->tex_handles[s][i] |= tic->id;
559 if (dirty)
560 BCTX_REFN(nvc0->bufctx_3d, TEX(s, i), res, RD);
561 }
562 for (; i < nvc0->state.num_textures[s]; ++i) {
563 nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID;
564 nvc0->textures_dirty[s] |= 1 << i;
565 }
566
567 nvc0->state.num_textures[s] = nvc0->num_textures[s];
568
569 return need_flush;
570 }
571
572 void nvc0_validate_textures(struct nvc0_context *nvc0)
573 {
574 bool need_flush = false;
575 int i;
576
577 for (i = 0; i < 5; i++) {
578 if (nvc0->screen->base.class_3d >= NVE4_3D_CLASS)
579 need_flush |= nve4_validate_tic(nvc0, i);
580 else
581 need_flush |= nvc0_validate_tic(nvc0, i);
582 }
583
584 if (need_flush) {
585 BEGIN_NVC0(nvc0->base.pushbuf, NVC0_3D(TIC_FLUSH), 1);
586 PUSH_DATA (nvc0->base.pushbuf, 0);
587 }
588 }
589
590 bool
591 nvc0_validate_tsc(struct nvc0_context *nvc0, int s)
592 {
593 uint32_t commands[16];
594 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
595 unsigned i;
596 unsigned n = 0;
597 bool need_flush = false;
598
599 for (i = 0; i < nvc0->num_samplers[s]; ++i) {
600 struct nv50_tsc_entry *tsc = nv50_tsc_entry(nvc0->samplers[s][i]);
601
602 if (!(nvc0->samplers_dirty[s] & (1 << i)))
603 continue;
604 if (!tsc) {
605 commands[n++] = (i << 4) | 0;
606 continue;
607 }
608 nvc0->seamless_cube_map = tsc->seamless_cube_map;
609 if (tsc->id < 0) {
610 tsc->id = nvc0_screen_tsc_alloc(nvc0->screen, tsc);
611
612 nvc0_m2mf_push_linear(&nvc0->base, nvc0->screen->txc,
613 65536 + tsc->id * 32, NV_VRAM_DOMAIN(&nvc0->screen->base),
614 32, tsc->tsc);
615 need_flush = true;
616 }
617 nvc0->screen->tsc.lock[tsc->id / 32] |= 1 << (tsc->id % 32);
618
619 commands[n++] = (tsc->id << 12) | (i << 4) | 1;
620 }
621 for (; i < nvc0->state.num_samplers[s]; ++i)
622 commands[n++] = (i << 4) | 0;
623
624 nvc0->state.num_samplers[s] = nvc0->num_samplers[s];
625
626 if (n) {
627 if (unlikely(s == 5))
628 BEGIN_NIC0(push, NVC0_COMPUTE(BIND_TSC), n);
629 else
630 BEGIN_NIC0(push, NVC0_3D(BIND_TSC(s)), n);
631 PUSH_DATAp(push, commands, n);
632 }
633 nvc0->samplers_dirty[s] = 0;
634
635 return need_flush;
636 }
637
638 bool
639 nve4_validate_tsc(struct nvc0_context *nvc0, int s)
640 {
641 struct nouveau_bo *txc = nvc0->screen->txc;
642 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
643 unsigned i;
644 bool need_flush = false;
645
646 for (i = 0; i < nvc0->num_samplers[s]; ++i) {
647 struct nv50_tsc_entry *tsc = nv50_tsc_entry(nvc0->samplers[s][i]);
648
649 if (!tsc) {
650 nvc0->tex_handles[s][i] |= NVE4_TSC_ENTRY_INVALID;
651 continue;
652 }
653 if (tsc->id < 0) {
654 tsc->id = nvc0_screen_tsc_alloc(nvc0->screen, tsc);
655
656 PUSH_SPACE(push, 16);
657 BEGIN_NVC0(push, NVE4_P2MF(UPLOAD_DST_ADDRESS_HIGH), 2);
658 PUSH_DATAh(push, txc->offset + 65536 + (tsc->id * 32));
659 PUSH_DATA (push, txc->offset + 65536 + (tsc->id * 32));
660 BEGIN_NVC0(push, NVE4_P2MF(UPLOAD_LINE_LENGTH_IN), 2);
661 PUSH_DATA (push, 32);
662 PUSH_DATA (push, 1);
663 BEGIN_1IC0(push, NVE4_P2MF(UPLOAD_EXEC), 9);
664 PUSH_DATA (push, 0x1001);
665 PUSH_DATAp(push, &tsc->tsc[0], 8);
666
667 need_flush = true;
668 }
669 nvc0->screen->tsc.lock[tsc->id / 32] |= 1 << (tsc->id % 32);
670
671 nvc0->tex_handles[s][i] &= ~NVE4_TSC_ENTRY_INVALID;
672 nvc0->tex_handles[s][i] |= tsc->id << 20;
673 }
674 for (; i < nvc0->state.num_samplers[s]; ++i) {
675 nvc0->tex_handles[s][i] |= NVE4_TSC_ENTRY_INVALID;
676 nvc0->samplers_dirty[s] |= 1 << i;
677 }
678
679 nvc0->state.num_samplers[s] = nvc0->num_samplers[s];
680
681 return need_flush;
682 }
683
684 void nvc0_validate_samplers(struct nvc0_context *nvc0)
685 {
686 bool need_flush = false;
687 int i;
688
689 for (i = 0; i < 5; i++) {
690 if (nvc0->screen->base.class_3d >= NVE4_3D_CLASS)
691 need_flush |= nve4_validate_tsc(nvc0, i);
692 else
693 need_flush |= nvc0_validate_tsc(nvc0, i);
694 }
695
696 if (need_flush) {
697 BEGIN_NVC0(nvc0->base.pushbuf, NVC0_3D(TSC_FLUSH), 1);
698 PUSH_DATA (nvc0->base.pushbuf, 0);
699 }
700 }
701
702 /* Upload the "diagonal" entries for the possible texture sources ($t == $s).
703 * At some point we might want to get a list of the combinations used by a
704 * shader and fill in those entries instead of having it extract the handles.
705 */
706 void
707 nve4_set_tex_handles(struct nvc0_context *nvc0)
708 {
709 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
710 uint64_t address;
711 unsigned s;
712
713 if (nvc0->screen->base.class_3d < NVE4_3D_CLASS)
714 return;
715 address = nvc0->screen->uniform_bo->offset + (6 << 16);
716
717 for (s = 0; s < 5; ++s, address += (1 << 10)) {
718 uint32_t dirty = nvc0->textures_dirty[s] | nvc0->samplers_dirty[s];
719 if (!dirty)
720 continue;
721 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
722 PUSH_DATA (push, 1024);
723 PUSH_DATAh(push, address);
724 PUSH_DATA (push, address);
725 do {
726 int i = ffs(dirty) - 1;
727 dirty &= ~(1 << i);
728
729 BEGIN_NVC0(push, NVC0_3D(CB_POS), 2);
730 PUSH_DATA (push, (8 + i) * 4);
731 PUSH_DATA (push, nvc0->tex_handles[s][i]);
732 } while (dirty);
733
734 nvc0->textures_dirty[s] = 0;
735 nvc0->samplers_dirty[s] = 0;
736 }
737 }
738
739
740 static const uint8_t nve4_su_format_map[PIPE_FORMAT_COUNT];
741 static const uint16_t nve4_su_format_aux_map[PIPE_FORMAT_COUNT];
742 static const uint16_t nve4_suldp_lib_offset[PIPE_FORMAT_COUNT];
743
744 void
745 nve4_set_surface_info(struct nouveau_pushbuf *push,
746 struct pipe_surface *psf,
747 struct nvc0_screen *screen)
748 {
749 struct nv50_surface *sf = nv50_surface(psf);
750 struct nv04_resource *res;
751 uint64_t address;
752 uint32_t *const info = push->cur;
753 uint8_t log2cpp;
754
755 if (psf && !nve4_su_format_map[psf->format])
756 NOUVEAU_ERR("unsupported surface format, try is_format_supported() !\n");
757
758 push->cur += 16;
759
760 if (!psf || !nve4_su_format_map[psf->format]) {
761 memset(info, 0, 16 * sizeof(*info));
762
763 info[0] = 0xbadf0000;
764 info[1] = 0x80004000;
765 info[12] = nve4_suldp_lib_offset[PIPE_FORMAT_R32G32B32A32_UINT] +
766 screen->lib_code->start;
767 return;
768 }
769 res = nv04_resource(sf->base.texture);
770
771 address = res->address + sf->offset;
772
773 info[8] = sf->width;
774 info[9] = sf->height;
775 info[10] = sf->depth;
776 switch (res->base.target) {
777 case PIPE_TEXTURE_1D_ARRAY:
778 info[11] = 1;
779 break;
780 case PIPE_TEXTURE_2D:
781 case PIPE_TEXTURE_RECT:
782 info[11] = 2;
783 break;
784 case PIPE_TEXTURE_3D:
785 info[11] = 3;
786 break;
787 case PIPE_TEXTURE_2D_ARRAY:
788 case PIPE_TEXTURE_CUBE:
789 case PIPE_TEXTURE_CUBE_ARRAY:
790 info[11] = 4;
791 break;
792 default:
793 info[11] = 0;
794 break;
795 }
796 log2cpp = (0xf000 & nve4_su_format_aux_map[sf->base.format]) >> 12;
797
798 info[12] = nve4_suldp_lib_offset[sf->base.format] + screen->lib_code->start;
799
800 /* limit in bytes for raw access */
801 info[13] = (0x06 << 22) | ((sf->width << log2cpp) - 1);
802
803 info[1] = nve4_su_format_map[sf->base.format];
804
805 #if 0
806 switch (util_format_get_blocksizebits(sf->base.format)) {
807 case 16: info[1] |= 1 << 16; break;
808 case 32: info[1] |= 2 << 16; break;
809 case 64: info[1] |= 3 << 16; break;
810 case 128: info[1] |= 4 << 16; break;
811 default:
812 break;
813 }
814 #else
815 info[1] |= log2cpp << 16;
816 info[1] |= 0x4000;
817 info[1] |= (0x0f00 & nve4_su_format_aux_map[sf->base.format]);
818 #endif
819
820 if (res->base.target == PIPE_BUFFER) {
821 info[0] = address >> 8;
822 info[2] = sf->width - 1;
823 info[2] |= (0xff & nve4_su_format_aux_map[sf->base.format]) << 22;
824 info[3] = 0;
825 info[4] = 0;
826 info[5] = 0;
827 info[6] = 0;
828 info[7] = 0;
829 info[14] = 0;
830 info[15] = 0;
831 } else {
832 struct nv50_miptree *mt = nv50_miptree(&res->base);
833 struct nv50_miptree_level *lvl = &mt->level[sf->base.u.tex.level];
834 const unsigned z = sf->base.u.tex.first_layer;
835
836 if (z) {
837 if (mt->layout_3d) {
838 address += nvc0_mt_zslice_offset(mt, psf->u.tex.level, z);
839 /* doesn't work if z passes z-tile boundary */
840 assert(sf->depth == 1);
841 } else {
842 address += mt->layer_stride * z;
843 }
844 }
845 info[0] = address >> 8;
846 info[2] = sf->width - 1;
847 /* NOTE: this is really important: */
848 info[2] |= (0xff & nve4_su_format_aux_map[sf->base.format]) << 22;
849 info[3] = (0x88 << 24) | (lvl->pitch / 64);
850 info[4] = sf->height - 1;
851 info[4] |= (lvl->tile_mode & 0x0f0) << 25;
852 info[4] |= NVC0_TILE_SHIFT_Y(lvl->tile_mode) << 22;
853 info[5] = mt->layer_stride >> 8;
854 info[6] = sf->depth - 1;
855 info[6] |= (lvl->tile_mode & 0xf00) << 21;
856 info[6] |= NVC0_TILE_SHIFT_Z(lvl->tile_mode) << 22;
857 info[7] = 0;
858 info[14] = mt->ms_x;
859 info[15] = mt->ms_y;
860 }
861 }
862
863 static inline void
864 nvc0_update_surface_bindings(struct nvc0_context *nvc0)
865 {
866 /* TODO */
867 }
868
869 static inline void
870 nve4_update_surface_bindings(struct nvc0_context *nvc0)
871 {
872 /* TODO */
873 }
874
875 void
876 nvc0_validate_surfaces(struct nvc0_context *nvc0)
877 {
878 if (nvc0->screen->base.class_3d >= NVE4_3D_CLASS) {
879 nve4_update_surface_bindings(nvc0);
880 } else {
881 nvc0_update_surface_bindings(nvc0);
882 }
883 }
884
885
886 static const uint8_t nve4_su_format_map[PIPE_FORMAT_COUNT] =
887 {
888 [PIPE_FORMAT_R32G32B32A32_FLOAT] = GK104_IMAGE_FORMAT_RGBA32_FLOAT,
889 [PIPE_FORMAT_R32G32B32A32_SINT] = GK104_IMAGE_FORMAT_RGBA32_SINT,
890 [PIPE_FORMAT_R32G32B32A32_UINT] = GK104_IMAGE_FORMAT_RGBA32_UINT,
891 [PIPE_FORMAT_R16G16B16A16_FLOAT] = GK104_IMAGE_FORMAT_RGBA16_FLOAT,
892 [PIPE_FORMAT_R16G16B16A16_UNORM] = GK104_IMAGE_FORMAT_RGBA16_UNORM,
893 [PIPE_FORMAT_R16G16B16A16_SNORM] = GK104_IMAGE_FORMAT_RGBA16_SNORM,
894 [PIPE_FORMAT_R16G16B16A16_SINT] = GK104_IMAGE_FORMAT_RGBA16_SINT,
895 [PIPE_FORMAT_R16G16B16A16_UINT] = GK104_IMAGE_FORMAT_RGBA16_UINT,
896 [PIPE_FORMAT_R8G8B8A8_UNORM] = GK104_IMAGE_FORMAT_RGBA8_UNORM,
897 [PIPE_FORMAT_R8G8B8A8_SNORM] = GK104_IMAGE_FORMAT_RGBA8_SNORM,
898 [PIPE_FORMAT_R8G8B8A8_SINT] = GK104_IMAGE_FORMAT_RGBA8_SINT,
899 [PIPE_FORMAT_R8G8B8A8_UINT] = GK104_IMAGE_FORMAT_RGBA8_UINT,
900 [PIPE_FORMAT_R11G11B10_FLOAT] = GK104_IMAGE_FORMAT_R11G11B10_FLOAT,
901 [PIPE_FORMAT_R10G10B10A2_UNORM] = GK104_IMAGE_FORMAT_RGB10_A2_UNORM,
902 /* [PIPE_FORMAT_R10G10B10A2_UINT] = GK104_IMAGE_FORMAT_RGB10_A2_UINT, */
903 [PIPE_FORMAT_R32G32_FLOAT] = GK104_IMAGE_FORMAT_RG32_FLOAT,
904 [PIPE_FORMAT_R32G32_SINT] = GK104_IMAGE_FORMAT_RG32_SINT,
905 [PIPE_FORMAT_R32G32_UINT] = GK104_IMAGE_FORMAT_RG32_UINT,
906 [PIPE_FORMAT_R16G16_FLOAT] = GK104_IMAGE_FORMAT_RG16_FLOAT,
907 [PIPE_FORMAT_R16G16_UNORM] = GK104_IMAGE_FORMAT_RG16_UNORM,
908 [PIPE_FORMAT_R16G16_SNORM] = GK104_IMAGE_FORMAT_RG16_SNORM,
909 [PIPE_FORMAT_R16G16_SINT] = GK104_IMAGE_FORMAT_RG16_SINT,
910 [PIPE_FORMAT_R16G16_UINT] = GK104_IMAGE_FORMAT_RG16_UINT,
911 [PIPE_FORMAT_R8G8_UNORM] = GK104_IMAGE_FORMAT_RG8_UNORM,
912 [PIPE_FORMAT_R8G8_SNORM] = GK104_IMAGE_FORMAT_RG8_SNORM,
913 [PIPE_FORMAT_R8G8_SINT] = GK104_IMAGE_FORMAT_RG8_SINT,
914 [PIPE_FORMAT_R8G8_UINT] = GK104_IMAGE_FORMAT_RG8_UINT,
915 [PIPE_FORMAT_R32_FLOAT] = GK104_IMAGE_FORMAT_R32_FLOAT,
916 [PIPE_FORMAT_R32_SINT] = GK104_IMAGE_FORMAT_R32_SINT,
917 [PIPE_FORMAT_R32_UINT] = GK104_IMAGE_FORMAT_R32_UINT,
918 [PIPE_FORMAT_R16_FLOAT] = GK104_IMAGE_FORMAT_R16_FLOAT,
919 [PIPE_FORMAT_R16_UNORM] = GK104_IMAGE_FORMAT_R16_UNORM,
920 [PIPE_FORMAT_R16_SNORM] = GK104_IMAGE_FORMAT_R16_SNORM,
921 [PIPE_FORMAT_R16_SINT] = GK104_IMAGE_FORMAT_R16_SINT,
922 [PIPE_FORMAT_R16_UINT] = GK104_IMAGE_FORMAT_R16_UINT,
923 [PIPE_FORMAT_R8_UNORM] = GK104_IMAGE_FORMAT_R8_UNORM,
924 [PIPE_FORMAT_R8_SNORM] = GK104_IMAGE_FORMAT_R8_SNORM,
925 [PIPE_FORMAT_R8_SINT] = GK104_IMAGE_FORMAT_R8_SINT,
926 [PIPE_FORMAT_R8_UINT] = GK104_IMAGE_FORMAT_R8_UINT,
927 };
928
929 /* Auxiliary format description values for surface instructions.
930 * (log2(bytes per pixel) << 12) | (unk8 << 8) | unk22
931 */
932 static const uint16_t nve4_su_format_aux_map[PIPE_FORMAT_COUNT] =
933 {
934 [PIPE_FORMAT_R32G32B32A32_FLOAT] = 0x4842,
935 [PIPE_FORMAT_R32G32B32A32_SINT] = 0x4842,
936 [PIPE_FORMAT_R32G32B32A32_UINT] = 0x4842,
937
938 [PIPE_FORMAT_R16G16B16A16_UNORM] = 0x3933,
939 [PIPE_FORMAT_R16G16B16A16_SNORM] = 0x3933,
940 [PIPE_FORMAT_R16G16B16A16_SINT] = 0x3933,
941 [PIPE_FORMAT_R16G16B16A16_UINT] = 0x3933,
942 [PIPE_FORMAT_R16G16B16A16_FLOAT] = 0x3933,
943
944 [PIPE_FORMAT_R32G32_FLOAT] = 0x3433,
945 [PIPE_FORMAT_R32G32_SINT] = 0x3433,
946 [PIPE_FORMAT_R32G32_UINT] = 0x3433,
947
948 [PIPE_FORMAT_R10G10B10A2_UNORM] = 0x2a24,
949 /* [PIPE_FORMAT_R10G10B10A2_UINT] = 0x2a24, */
950 [PIPE_FORMAT_R8G8B8A8_UNORM] = 0x2a24,
951 [PIPE_FORMAT_R8G8B8A8_SNORM] = 0x2a24,
952 [PIPE_FORMAT_R8G8B8A8_SINT] = 0x2a24,
953 [PIPE_FORMAT_R8G8B8A8_UINT] = 0x2a24,
954 [PIPE_FORMAT_R11G11B10_FLOAT] = 0x2a24,
955
956 [PIPE_FORMAT_R16G16_UNORM] = 0x2524,
957 [PIPE_FORMAT_R16G16_SNORM] = 0x2524,
958 [PIPE_FORMAT_R16G16_SINT] = 0x2524,
959 [PIPE_FORMAT_R16G16_UINT] = 0x2524,
960 [PIPE_FORMAT_R16G16_FLOAT] = 0x2524,
961
962 [PIPE_FORMAT_R32_SINT] = 0x2024,
963 [PIPE_FORMAT_R32_UINT] = 0x2024,
964 [PIPE_FORMAT_R32_FLOAT] = 0x2024,
965
966 [PIPE_FORMAT_R8G8_UNORM] = 0x1615,
967 [PIPE_FORMAT_R8G8_SNORM] = 0x1615,
968 [PIPE_FORMAT_R8G8_SINT] = 0x1615,
969 [PIPE_FORMAT_R8G8_UINT] = 0x1615,
970
971 [PIPE_FORMAT_R16_UNORM] = 0x1115,
972 [PIPE_FORMAT_R16_SNORM] = 0x1115,
973 [PIPE_FORMAT_R16_SINT] = 0x1115,
974 [PIPE_FORMAT_R16_UINT] = 0x1115,
975 [PIPE_FORMAT_R16_FLOAT] = 0x1115,
976
977 [PIPE_FORMAT_R8_UNORM] = 0x0206,
978 [PIPE_FORMAT_R8_SNORM] = 0x0206,
979 [PIPE_FORMAT_R8_SINT] = 0x0206,
980 [PIPE_FORMAT_R8_UINT] = 0x0206
981 };
982
983 /* NOTE: These are hardcoded offsets for the shader library.
984 * TODO: Automate them.
985 */
986 static const uint16_t nve4_suldp_lib_offset[PIPE_FORMAT_COUNT] =
987 {
988 [PIPE_FORMAT_R32G32B32A32_FLOAT] = 0x218,
989 [PIPE_FORMAT_R32G32B32A32_SINT] = 0x218,
990 [PIPE_FORMAT_R32G32B32A32_UINT] = 0x218,
991 [PIPE_FORMAT_R16G16B16A16_UNORM] = 0x248,
992 [PIPE_FORMAT_R16G16B16A16_SNORM] = 0x2b8,
993 [PIPE_FORMAT_R16G16B16A16_SINT] = 0x330,
994 [PIPE_FORMAT_R16G16B16A16_UINT] = 0x388,
995 [PIPE_FORMAT_R16G16B16A16_FLOAT] = 0x3d8,
996 [PIPE_FORMAT_R32G32_FLOAT] = 0x428,
997 [PIPE_FORMAT_R32G32_SINT] = 0x468,
998 [PIPE_FORMAT_R32G32_UINT] = 0x468,
999 [PIPE_FORMAT_R10G10B10A2_UNORM] = 0x4a8,
1000 /* [PIPE_FORMAT_R10G10B10A2_UINT] = 0x530, */
1001 [PIPE_FORMAT_R8G8B8A8_UNORM] = 0x588,
1002 [PIPE_FORMAT_R8G8B8A8_SNORM] = 0x5f8,
1003 [PIPE_FORMAT_R8G8B8A8_SINT] = 0x670,
1004 [PIPE_FORMAT_R8G8B8A8_UINT] = 0x6c8,
1005 [PIPE_FORMAT_B5G6R5_UNORM] = 0x718,
1006 [PIPE_FORMAT_B5G5R5X1_UNORM] = 0x7a0,
1007 [PIPE_FORMAT_R16G16_UNORM] = 0x828,
1008 [PIPE_FORMAT_R16G16_SNORM] = 0x890,
1009 [PIPE_FORMAT_R16G16_SINT] = 0x8f0,
1010 [PIPE_FORMAT_R16G16_UINT] = 0x948,
1011 [PIPE_FORMAT_R16G16_FLOAT] = 0x998,
1012 [PIPE_FORMAT_R32_FLOAT] = 0x9e8,
1013 [PIPE_FORMAT_R32_SINT] = 0xa30,
1014 [PIPE_FORMAT_R32_UINT] = 0xa30,
1015 [PIPE_FORMAT_R8G8_UNORM] = 0xa78,
1016 [PIPE_FORMAT_R8G8_SNORM] = 0xae0,
1017 [PIPE_FORMAT_R8G8_UINT] = 0xb48,
1018 [PIPE_FORMAT_R8G8_SINT] = 0xb98,
1019 [PIPE_FORMAT_R16_UNORM] = 0xbe8,
1020 [PIPE_FORMAT_R16_SNORM] = 0xc48,
1021 [PIPE_FORMAT_R16_SINT] = 0xca0,
1022 [PIPE_FORMAT_R16_UINT] = 0xce8,
1023 [PIPE_FORMAT_R16_FLOAT] = 0xd30,
1024 [PIPE_FORMAT_R8_UNORM] = 0xd88,
1025 [PIPE_FORMAT_R8_SNORM] = 0xde0,
1026 [PIPE_FORMAT_R8_SINT] = 0xe38,
1027 [PIPE_FORMAT_R8_UINT] = 0xe88,
1028 [PIPE_FORMAT_R11G11B10_FLOAT] = 0xed0
1029 };