2 * Copyright 2008 Ben Skeggs
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include "nvc0/nvc0_context.h"
24 #include "nvc0/nvc0_resource.h"
25 #include "nvc0/gm107_texture.xml.h"
26 #include "nvc0/nvc0_compute.xml.h"
27 #include "nv50/g80_texture.xml.h"
28 #include "nv50/g80_defs.xml.h"
30 #include "util/u_format.h"
32 #define NVE4_TIC_ENTRY_INVALID 0x000fffff
33 #define NVE4_TSC_ENTRY_INVALID 0xfff00000
35 static inline uint32_t
36 nv50_tic_swizzle(const struct nvc0_format
*fmt
, unsigned swz
, bool tex_int
)
39 case PIPE_SWIZZLE_X
: return fmt
->tic
.src_x
;
40 case PIPE_SWIZZLE_Y
: return fmt
->tic
.src_y
;
41 case PIPE_SWIZZLE_Z
: return fmt
->tic
.src_z
;
42 case PIPE_SWIZZLE_W
: return fmt
->tic
.src_w
;
44 return tex_int
? G80_TIC_SOURCE_ONE_INT
: G80_TIC_SOURCE_ONE_FLOAT
;
47 return G80_TIC_SOURCE_ZERO
;
51 struct pipe_sampler_view
*
52 nvc0_create_sampler_view(struct pipe_context
*pipe
,
53 struct pipe_resource
*res
,
54 const struct pipe_sampler_view
*templ
)
58 if (templ
->target
== PIPE_TEXTURE_RECT
|| templ
->target
== PIPE_BUFFER
)
59 flags
|= NV50_TEXVIEW_SCALED_COORDS
;
61 return nvc0_create_texture_view(pipe
, res
, templ
, flags
, templ
->target
);
64 static struct pipe_sampler_view
*
65 gm107_create_texture_view(struct pipe_context
*pipe
,
66 struct pipe_resource
*texture
,
67 const struct pipe_sampler_view
*templ
,
69 enum pipe_texture_target target
)
71 const struct util_format_description
*desc
;
72 const struct nvc0_format
*fmt
;
76 uint32_t width
, height
;
78 struct nv50_tic_entry
*view
;
79 struct nv50_miptree
*mt
;
82 view
= MALLOC_STRUCT(nv50_tic_entry
);
85 mt
= nv50_miptree(texture
);
88 view
->pipe
.reference
.count
= 1;
89 view
->pipe
.texture
= NULL
;
90 view
->pipe
.context
= pipe
;
94 pipe_resource_reference(&view
->pipe
.texture
, texture
);
98 desc
= util_format_description(view
->pipe
.format
);
99 tex_int
= util_format_is_pure_integer(view
->pipe
.format
);
101 fmt
= &nvc0_format_table
[view
->pipe
.format
];
102 swz
[0] = nv50_tic_swizzle(fmt
, view
->pipe
.swizzle_r
, tex_int
);
103 swz
[1] = nv50_tic_swizzle(fmt
, view
->pipe
.swizzle_g
, tex_int
);
104 swz
[2] = nv50_tic_swizzle(fmt
, view
->pipe
.swizzle_b
, tex_int
);
105 swz
[3] = nv50_tic_swizzle(fmt
, view
->pipe
.swizzle_a
, tex_int
);
107 tic
[0] = fmt
->tic
.format
<< GM107_TIC2_0_COMPONENTS_SIZES__SHIFT
;
108 tic
[0] |= fmt
->tic
.type_r
<< GM107_TIC2_0_R_DATA_TYPE__SHIFT
;
109 tic
[0] |= fmt
->tic
.type_g
<< GM107_TIC2_0_G_DATA_TYPE__SHIFT
;
110 tic
[0] |= fmt
->tic
.type_b
<< GM107_TIC2_0_B_DATA_TYPE__SHIFT
;
111 tic
[0] |= fmt
->tic
.type_a
<< GM107_TIC2_0_A_DATA_TYPE__SHIFT
;
112 tic
[0] |= swz
[0] << GM107_TIC2_0_X_SOURCE__SHIFT
;
113 tic
[0] |= swz
[1] << GM107_TIC2_0_Y_SOURCE__SHIFT
;
114 tic
[0] |= swz
[2] << GM107_TIC2_0_Z_SOURCE__SHIFT
;
115 tic
[0] |= swz
[3] << GM107_TIC2_0_W_SOURCE__SHIFT
;
117 address
= mt
->base
.address
;
119 tic
[3] = GM107_TIC2_3_LOD_ANISO_QUALITY_2
;
120 tic
[4] = GM107_TIC2_4_SECTOR_PROMOTION_PROMOTE_TO_2_V
;
121 tic
[4] |= GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR
;
123 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
124 tic
[4] |= GM107_TIC2_4_SRGB_CONVERSION
;
126 if (!(flags
& NV50_TEXVIEW_SCALED_COORDS
))
127 tic
[5] = GM107_TIC2_5_NORMALIZED_COORDS
;
131 /* check for linear storage type */
132 if (unlikely(!nouveau_bo_memtype(nv04_resource(texture
)->bo
))) {
133 if (texture
->target
== PIPE_BUFFER
) {
134 assert(!(tic
[5] & GM107_TIC2_5_NORMALIZED_COORDS
));
135 width
= view
->pipe
.u
.buf
.last_element
- view
->pipe
.u
.buf
.first_element
;
137 view
->pipe
.u
.buf
.first_element
* desc
->block
.bits
/ 8;
138 tic
[2] = GM107_TIC2_2_HEADER_VERSION_ONE_D_BUFFER
;
139 tic
[3] |= width
>> 16;
140 tic
[4] |= GM107_TIC2_4_TEXTURE_TYPE_ONE_D_BUFFER
;
141 tic
[4] |= width
& 0xffff;
143 assert(!(mt
->level
[0].pitch
& 0x1f));
144 /* must be 2D texture without mip maps */
145 tic
[2] = GM107_TIC2_2_HEADER_VERSION_PITCH
;
146 tic
[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP
;
147 tic
[3] |= mt
->level
[0].pitch
>> 5;
148 tic
[4] |= mt
->base
.base
.width0
- 1;
149 tic
[5] |= 0 << GM107_TIC2_5_DEPTH_MINUS_ONE__SHIFT
;
150 tic
[5] |= mt
->base
.base
.height0
- 1;
153 tic
[2] |= address
>> 32;
159 tic
[2] = GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR
;
161 ((mt
->level
[0].tile_mode
& 0x0f0) >> 4 << 3) |
162 ((mt
->level
[0].tile_mode
& 0xf00) >> 8 << 6);
164 depth
= MAX2(mt
->base
.base
.array_size
, mt
->base
.base
.depth0
);
166 if (mt
->base
.base
.array_size
> 1) {
167 /* there doesn't seem to be a base layer field in TIC */
168 address
+= view
->pipe
.u
.tex
.first_layer
* mt
->layer_stride
;
169 depth
= view
->pipe
.u
.tex
.last_layer
- view
->pipe
.u
.tex
.first_layer
+ 1;
172 tic
[2] |= address
>> 32;
175 case PIPE_TEXTURE_1D
:
176 tic
[4] |= GM107_TIC2_4_TEXTURE_TYPE_ONE_D
;
178 case PIPE_TEXTURE_2D
:
179 tic
[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D
;
181 case PIPE_TEXTURE_RECT
:
182 tic
[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D
;
184 case PIPE_TEXTURE_3D
:
185 tic
[4] |= GM107_TIC2_4_TEXTURE_TYPE_THREE_D
;
187 case PIPE_TEXTURE_CUBE
:
189 tic
[4] |= GM107_TIC2_4_TEXTURE_TYPE_CUBEMAP
;
191 case PIPE_TEXTURE_1D_ARRAY
:
192 tic
[4] |= GM107_TIC2_4_TEXTURE_TYPE_ONE_D_ARRAY
;
194 case PIPE_TEXTURE_2D_ARRAY
:
195 tic
[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D_ARRAY
;
197 case PIPE_TEXTURE_CUBE_ARRAY
:
199 tic
[4] |= GM107_TIC2_4_TEXTURE_TYPE_CUBE_ARRAY
;
202 unreachable("unexpected/invalid texture target");
205 tic
[3] |= (flags
& NV50_TEXVIEW_FILTER_MSAA8
) ?
206 GM107_TIC2_3_USE_HEADER_OPT_CONTROL
:
207 GM107_TIC2_3_LOD_ANISO_QUALITY_HIGH
|
208 GM107_TIC2_3_LOD_ISO_QUALITY_HIGH
;
210 if (flags
& NV50_TEXVIEW_ACCESS_RESOLVE
) {
211 width
= mt
->base
.base
.width0
<< mt
->ms_x
;
212 height
= mt
->base
.base
.height0
<< mt
->ms_y
;
214 width
= mt
->base
.base
.width0
;
215 height
= mt
->base
.base
.height0
;
220 tic
[5] |= (height
- 1) & 0xffff;
221 tic
[5] |= (depth
- 1) << GM107_TIC2_5_DEPTH_MINUS_ONE__SHIFT
;
222 tic
[3] |= mt
->base
.base
.last_level
<< GM107_TIC2_3_MAX_MIP_LEVEL__SHIFT
;
224 /* sampling points: (?) */
225 if ((flags
& NV50_TEXVIEW_ACCESS_RESOLVE
) && mt
->ms_x
> 1) {
226 tic
[6] = GM107_TIC2_6_ANISO_FINE_SPREAD_MODIFIER_CONST_TWO
;
227 tic
[6] |= GM107_TIC2_6_MAX_ANISOTROPY_2_TO_1
;
229 tic
[6] = GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_TWO
;
230 tic
[6] |= GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_ONE
;
233 tic
[7] = (view
->pipe
.u
.tex
.last_level
<< 4) | view
->pipe
.u
.tex
.first_level
;
234 tic
[7] |= mt
->ms_mode
<< GM107_TIC2_7_MULTI_SAMPLE_COUNT__SHIFT
;
239 static struct pipe_sampler_view
*
240 gf100_create_texture_view(struct pipe_context
*pipe
,
241 struct pipe_resource
*texture
,
242 const struct pipe_sampler_view
*templ
,
244 enum pipe_texture_target target
)
246 const struct util_format_description
*desc
;
247 const struct nvc0_format
*fmt
;
251 uint32_t width
, height
;
254 struct nv50_tic_entry
*view
;
255 struct nv50_miptree
*mt
;
258 view
= MALLOC_STRUCT(nv50_tic_entry
);
261 mt
= nv50_miptree(texture
);
264 view
->pipe
.reference
.count
= 1;
265 view
->pipe
.texture
= NULL
;
266 view
->pipe
.context
= pipe
;
270 pipe_resource_reference(&view
->pipe
.texture
, texture
);
274 desc
= util_format_description(view
->pipe
.format
);
276 fmt
= &nvc0_format_table
[view
->pipe
.format
];
278 tex_int
= util_format_is_pure_integer(view
->pipe
.format
);
279 tex_fmt
= fmt
->tic
.format
& 0x3f;
281 swz
[0] = nv50_tic_swizzle(fmt
, view
->pipe
.swizzle_r
, tex_int
);
282 swz
[1] = nv50_tic_swizzle(fmt
, view
->pipe
.swizzle_g
, tex_int
);
283 swz
[2] = nv50_tic_swizzle(fmt
, view
->pipe
.swizzle_b
, tex_int
);
284 swz
[3] = nv50_tic_swizzle(fmt
, view
->pipe
.swizzle_a
, tex_int
);
285 tic
[0] = (tex_fmt
<< G80_TIC_0_COMPONENTS_SIZES__SHIFT
) |
286 (fmt
->tic
.type_r
<< G80_TIC_0_R_DATA_TYPE__SHIFT
) |
287 (fmt
->tic
.type_g
<< G80_TIC_0_G_DATA_TYPE__SHIFT
) |
288 (fmt
->tic
.type_b
<< G80_TIC_0_B_DATA_TYPE__SHIFT
) |
289 (fmt
->tic
.type_a
<< G80_TIC_0_A_DATA_TYPE__SHIFT
) |
290 (swz
[0] << G80_TIC_0_X_SOURCE__SHIFT
) |
291 (swz
[1] << G80_TIC_0_Y_SOURCE__SHIFT
) |
292 (swz
[2] << G80_TIC_0_Z_SOURCE__SHIFT
) |
293 (swz
[3] << G80_TIC_0_W_SOURCE__SHIFT
) |
294 ((fmt
->tic
.format
& 0x40) << (GK20A_TIC_0_USE_COMPONENT_SIZES_EXTENDED__SHIFT
- 6));
296 address
= mt
->base
.address
;
298 tic
[2] = 0x10001000 | G80_TIC_2_BORDER_SOURCE_COLOR
;
300 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
301 tic
[2] |= G80_TIC_2_SRGB_CONVERSION
;
303 if (!(flags
& NV50_TEXVIEW_SCALED_COORDS
))
304 tic
[2] |= G80_TIC_2_NORMALIZED_COORDS
;
306 /* check for linear storage type */
307 if (unlikely(!nouveau_bo_memtype(nv04_resource(texture
)->bo
))) {
308 if (texture
->target
== PIPE_BUFFER
) {
309 assert(!(tic
[2] & G80_TIC_2_NORMALIZED_COORDS
));
311 view
->pipe
.u
.buf
.first_element
* desc
->block
.bits
/ 8;
312 tic
[2] |= G80_TIC_2_LAYOUT_PITCH
| G80_TIC_2_TEXTURE_TYPE_ONE_D_BUFFER
;
315 view
->pipe
.u
.buf
.last_element
- view
->pipe
.u
.buf
.first_element
+ 1;
318 /* must be 2D texture without mip maps */
319 tic
[2] |= G80_TIC_2_LAYOUT_PITCH
| G80_TIC_2_TEXTURE_TYPE_TWO_D_NO_MIPMAP
;
320 tic
[3] = mt
->level
[0].pitch
;
321 tic
[4] = mt
->base
.base
.width0
;
322 tic
[5] = (1 << 16) | mt
->base
.base
.height0
;
327 tic
[2] |= address
>> 32;
332 ((mt
->level
[0].tile_mode
& 0x0f0) << (22 - 4)) |
333 ((mt
->level
[0].tile_mode
& 0xf00) << (25 - 8));
335 depth
= MAX2(mt
->base
.base
.array_size
, mt
->base
.base
.depth0
);
337 if (mt
->base
.base
.array_size
> 1) {
338 /* there doesn't seem to be a base layer field in TIC */
339 address
+= view
->pipe
.u
.tex
.first_layer
* mt
->layer_stride
;
340 depth
= view
->pipe
.u
.tex
.last_layer
- view
->pipe
.u
.tex
.first_layer
+ 1;
343 tic
[2] |= address
>> 32;
346 case PIPE_TEXTURE_1D
:
347 tic
[2] |= G80_TIC_2_TEXTURE_TYPE_ONE_D
;
349 case PIPE_TEXTURE_2D
:
350 tic
[2] |= G80_TIC_2_TEXTURE_TYPE_TWO_D
;
352 case PIPE_TEXTURE_RECT
:
353 tic
[2] |= G80_TIC_2_TEXTURE_TYPE_TWO_D
;
355 case PIPE_TEXTURE_3D
:
356 tic
[2] |= G80_TIC_2_TEXTURE_TYPE_THREE_D
;
358 case PIPE_TEXTURE_CUBE
:
360 tic
[2] |= G80_TIC_2_TEXTURE_TYPE_CUBEMAP
;
362 case PIPE_TEXTURE_1D_ARRAY
:
363 tic
[2] |= G80_TIC_2_TEXTURE_TYPE_ONE_D_ARRAY
;
365 case PIPE_TEXTURE_2D_ARRAY
:
366 tic
[2] |= G80_TIC_2_TEXTURE_TYPE_TWO_D_ARRAY
;
368 case PIPE_TEXTURE_CUBE_ARRAY
:
370 tic
[2] |= G80_TIC_2_TEXTURE_TYPE_CUBE_ARRAY
;
373 unreachable("unexpected/invalid texture target");
376 tic
[3] = (flags
& NV50_TEXVIEW_FILTER_MSAA8
) ? 0x20000000 : 0x00300000;
378 if (flags
& NV50_TEXVIEW_ACCESS_RESOLVE
) {
379 width
= mt
->base
.base
.width0
<< mt
->ms_x
;
380 height
= mt
->base
.base
.height0
<< mt
->ms_y
;
382 width
= mt
->base
.base
.width0
;
383 height
= mt
->base
.base
.height0
;
386 tic
[4] = (1 << 31) | width
;
388 tic
[5] = height
& 0xffff;
389 tic
[5] |= depth
<< 16;
390 tic
[5] |= mt
->base
.base
.last_level
<< 28;
392 /* sampling points: (?) */
393 if (flags
& NV50_TEXVIEW_ACCESS_RESOLVE
)
394 tic
[6] = (mt
->ms_x
> 1) ? 0x88000000 : 0x03000000;
398 tic
[7] = (view
->pipe
.u
.tex
.last_level
<< 4) | view
->pipe
.u
.tex
.first_level
;
399 tic
[7] |= mt
->ms_mode
<< 12;
404 struct pipe_sampler_view
*
405 nvc0_create_texture_view(struct pipe_context
*pipe
,
406 struct pipe_resource
*texture
,
407 const struct pipe_sampler_view
*templ
,
409 enum pipe_texture_target target
)
411 if (nvc0_context(pipe
)->screen
->tic
.maxwell
)
412 return gm107_create_texture_view(pipe
, texture
, templ
, flags
, target
);
413 return gf100_create_texture_view(pipe
, texture
, templ
, flags
, target
);
417 nvc0_update_tic(struct nvc0_context
*nvc0
, struct nv50_tic_entry
*tic
,
418 struct nv04_resource
*res
)
420 uint64_t address
= res
->address
;
421 if (res
->base
.target
!= PIPE_BUFFER
)
423 address
+= tic
->pipe
.u
.buf
.first_element
*
424 util_format_get_blocksize(tic
->pipe
.format
);
425 if (tic
->tic
[1] == (uint32_t)address
&&
426 (tic
->tic
[2] & 0xff) == address
>> 32)
429 nvc0_screen_tic_unlock(nvc0
->screen
, tic
);
431 tic
->tic
[1] = address
;
432 tic
->tic
[2] &= 0xffffff00;
433 tic
->tic
[2] |= address
>> 32;
437 nvc0_validate_tic(struct nvc0_context
*nvc0
, int s
)
439 uint32_t commands
[32];
440 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
441 struct nouveau_bo
*txc
= nvc0
->screen
->txc
;
444 bool need_flush
= false;
446 for (i
= 0; i
< nvc0
->num_textures
[s
]; ++i
) {
447 struct nv50_tic_entry
*tic
= nv50_tic_entry(nvc0
->textures
[s
][i
]);
448 struct nv04_resource
*res
;
449 const bool dirty
= !!(nvc0
->textures_dirty
[s
] & (1 << i
));
453 commands
[n
++] = (i
<< 1) | 0;
456 res
= nv04_resource(tic
->pipe
.texture
);
457 nvc0_update_tic(nvc0
, tic
, res
);
460 tic
->id
= nvc0_screen_tic_alloc(nvc0
->screen
, tic
);
462 PUSH_SPACE(push
, 17);
463 BEGIN_NVC0(push
, NVC0_M2MF(OFFSET_OUT_HIGH
), 2);
464 PUSH_DATAh(push
, txc
->offset
+ (tic
->id
* 32));
465 PUSH_DATA (push
, txc
->offset
+ (tic
->id
* 32));
466 BEGIN_NVC0(push
, NVC0_M2MF(LINE_LENGTH_IN
), 2);
467 PUSH_DATA (push
, 32);
469 BEGIN_NVC0(push
, NVC0_M2MF(EXEC
), 1);
470 PUSH_DATA (push
, 0x100111);
471 BEGIN_NIC0(push
, NVC0_M2MF(DATA
), 8);
472 PUSH_DATAp(push
, &tic
->tic
[0], 8);
476 if (res
->status
& NOUVEAU_BUFFER_STATUS_GPU_WRITING
) {
477 if (unlikely(s
== 5))
478 BEGIN_NVC0(push
, NVC0_CP(TEX_CACHE_CTL
), 1);
480 BEGIN_NVC0(push
, NVC0_3D(TEX_CACHE_CTL
), 1);
481 PUSH_DATA (push
, (tic
->id
<< 4) | 1);
482 NOUVEAU_DRV_STAT(&nvc0
->screen
->base
, tex_cache_flush_count
, 1);
484 nvc0
->screen
->tic
.lock
[tic
->id
/ 32] |= 1 << (tic
->id
% 32);
486 res
->status
&= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING
;
487 res
->status
|= NOUVEAU_BUFFER_STATUS_GPU_READING
;
491 commands
[n
++] = (tic
->id
<< 9) | (i
<< 1) | 1;
493 if (unlikely(s
== 5))
494 BCTX_REFN(nvc0
->bufctx_cp
, CP_TEX(i
), res
, RD
);
496 BCTX_REFN(nvc0
->bufctx_3d
, 3D_TEX(s
, i
), res
, RD
);
498 for (; i
< nvc0
->state
.num_textures
[s
]; ++i
)
499 commands
[n
++] = (i
<< 1) | 0;
501 nvc0
->state
.num_textures
[s
] = nvc0
->num_textures
[s
];
504 if (unlikely(s
== 5))
505 BEGIN_NIC0(push
, NVC0_CP(BIND_TIC
), n
);
507 BEGIN_NIC0(push
, NVC0_3D(BIND_TIC(s
)), n
);
508 PUSH_DATAp(push
, commands
, n
);
510 nvc0
->textures_dirty
[s
] = 0;
516 nve4_validate_tic(struct nvc0_context
*nvc0
, unsigned s
)
518 struct nouveau_bo
*txc
= nvc0
->screen
->txc
;
519 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
521 bool need_flush
= false;
523 for (i
= 0; i
< nvc0
->num_textures
[s
]; ++i
) {
524 struct nv50_tic_entry
*tic
= nv50_tic_entry(nvc0
->textures
[s
][i
]);
525 struct nv04_resource
*res
;
526 const bool dirty
= !!(nvc0
->textures_dirty
[s
] & (1 << i
));
529 nvc0
->tex_handles
[s
][i
] |= NVE4_TIC_ENTRY_INVALID
;
532 res
= nv04_resource(tic
->pipe
.texture
);
533 nvc0_update_tic(nvc0
, tic
, res
);
536 tic
->id
= nvc0_screen_tic_alloc(nvc0
->screen
, tic
);
538 PUSH_SPACE(push
, 16);
539 BEGIN_NVC0(push
, NVE4_P2MF(UPLOAD_DST_ADDRESS_HIGH
), 2);
540 PUSH_DATAh(push
, txc
->offset
+ (tic
->id
* 32));
541 PUSH_DATA (push
, txc
->offset
+ (tic
->id
* 32));
542 BEGIN_NVC0(push
, NVE4_P2MF(UPLOAD_LINE_LENGTH_IN
), 2);
543 PUSH_DATA (push
, 32);
545 BEGIN_1IC0(push
, NVE4_P2MF(UPLOAD_EXEC
), 9);
546 PUSH_DATA (push
, 0x1001);
547 PUSH_DATAp(push
, &tic
->tic
[0], 8);
551 if (res
->status
& NOUVEAU_BUFFER_STATUS_GPU_WRITING
) {
552 BEGIN_NVC0(push
, NVC0_3D(TEX_CACHE_CTL
), 1);
553 PUSH_DATA (push
, (tic
->id
<< 4) | 1);
555 nvc0
->screen
->tic
.lock
[tic
->id
/ 32] |= 1 << (tic
->id
% 32);
557 res
->status
&= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING
;
558 res
->status
|= NOUVEAU_BUFFER_STATUS_GPU_READING
;
560 nvc0
->tex_handles
[s
][i
] &= ~NVE4_TIC_ENTRY_INVALID
;
561 nvc0
->tex_handles
[s
][i
] |= tic
->id
;
563 BCTX_REFN(nvc0
->bufctx_3d
, 3D_TEX(s
, i
), res
, RD
);
565 for (; i
< nvc0
->state
.num_textures
[s
]; ++i
) {
566 nvc0
->tex_handles
[s
][i
] |= NVE4_TIC_ENTRY_INVALID
;
567 nvc0
->textures_dirty
[s
] |= 1 << i
;
570 nvc0
->state
.num_textures
[s
] = nvc0
->num_textures
[s
];
575 void nvc0_validate_textures(struct nvc0_context
*nvc0
)
577 bool need_flush
= false;
580 for (i
= 0; i
< 5; i
++) {
581 if (nvc0
->screen
->base
.class_3d
>= NVE4_3D_CLASS
)
582 need_flush
|= nve4_validate_tic(nvc0
, i
);
584 need_flush
|= nvc0_validate_tic(nvc0
, i
);
588 BEGIN_NVC0(nvc0
->base
.pushbuf
, NVC0_3D(TIC_FLUSH
), 1);
589 PUSH_DATA (nvc0
->base
.pushbuf
, 0);
594 nvc0_validate_tsc(struct nvc0_context
*nvc0
, int s
)
596 uint32_t commands
[16];
597 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
600 bool need_flush
= false;
602 for (i
= 0; i
< nvc0
->num_samplers
[s
]; ++i
) {
603 struct nv50_tsc_entry
*tsc
= nv50_tsc_entry(nvc0
->samplers
[s
][i
]);
605 if (!(nvc0
->samplers_dirty
[s
] & (1 << i
)))
608 commands
[n
++] = (i
<< 4) | 0;
611 nvc0
->seamless_cube_map
= tsc
->seamless_cube_map
;
613 tsc
->id
= nvc0_screen_tsc_alloc(nvc0
->screen
, tsc
);
615 nvc0_m2mf_push_linear(&nvc0
->base
, nvc0
->screen
->txc
,
616 65536 + tsc
->id
* 32, NV_VRAM_DOMAIN(&nvc0
->screen
->base
),
620 nvc0
->screen
->tsc
.lock
[tsc
->id
/ 32] |= 1 << (tsc
->id
% 32);
622 commands
[n
++] = (tsc
->id
<< 12) | (i
<< 4) | 1;
624 for (; i
< nvc0
->state
.num_samplers
[s
]; ++i
)
625 commands
[n
++] = (i
<< 4) | 0;
627 nvc0
->state
.num_samplers
[s
] = nvc0
->num_samplers
[s
];
630 if (unlikely(s
== 5))
631 BEGIN_NIC0(push
, NVC0_CP(BIND_TSC
), n
);
633 BEGIN_NIC0(push
, NVC0_3D(BIND_TSC(s
)), n
);
634 PUSH_DATAp(push
, commands
, n
);
636 nvc0
->samplers_dirty
[s
] = 0;
642 nve4_validate_tsc(struct nvc0_context
*nvc0
, int s
)
644 struct nouveau_bo
*txc
= nvc0
->screen
->txc
;
645 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
647 bool need_flush
= false;
649 for (i
= 0; i
< nvc0
->num_samplers
[s
]; ++i
) {
650 struct nv50_tsc_entry
*tsc
= nv50_tsc_entry(nvc0
->samplers
[s
][i
]);
653 nvc0
->tex_handles
[s
][i
] |= NVE4_TSC_ENTRY_INVALID
;
657 tsc
->id
= nvc0_screen_tsc_alloc(nvc0
->screen
, tsc
);
659 PUSH_SPACE(push
, 16);
660 BEGIN_NVC0(push
, NVE4_P2MF(UPLOAD_DST_ADDRESS_HIGH
), 2);
661 PUSH_DATAh(push
, txc
->offset
+ 65536 + (tsc
->id
* 32));
662 PUSH_DATA (push
, txc
->offset
+ 65536 + (tsc
->id
* 32));
663 BEGIN_NVC0(push
, NVE4_P2MF(UPLOAD_LINE_LENGTH_IN
), 2);
664 PUSH_DATA (push
, 32);
666 BEGIN_1IC0(push
, NVE4_P2MF(UPLOAD_EXEC
), 9);
667 PUSH_DATA (push
, 0x1001);
668 PUSH_DATAp(push
, &tsc
->tsc
[0], 8);
672 nvc0
->screen
->tsc
.lock
[tsc
->id
/ 32] |= 1 << (tsc
->id
% 32);
674 nvc0
->tex_handles
[s
][i
] &= ~NVE4_TSC_ENTRY_INVALID
;
675 nvc0
->tex_handles
[s
][i
] |= tsc
->id
<< 20;
677 for (; i
< nvc0
->state
.num_samplers
[s
]; ++i
) {
678 nvc0
->tex_handles
[s
][i
] |= NVE4_TSC_ENTRY_INVALID
;
679 nvc0
->samplers_dirty
[s
] |= 1 << i
;
682 nvc0
->state
.num_samplers
[s
] = nvc0
->num_samplers
[s
];
687 void nvc0_validate_samplers(struct nvc0_context
*nvc0
)
689 bool need_flush
= false;
692 for (i
= 0; i
< 5; i
++) {
693 if (nvc0
->screen
->base
.class_3d
>= NVE4_3D_CLASS
)
694 need_flush
|= nve4_validate_tsc(nvc0
, i
);
696 need_flush
|= nvc0_validate_tsc(nvc0
, i
);
700 BEGIN_NVC0(nvc0
->base
.pushbuf
, NVC0_3D(TSC_FLUSH
), 1);
701 PUSH_DATA (nvc0
->base
.pushbuf
, 0);
705 /* Upload the "diagonal" entries for the possible texture sources ($t == $s).
706 * At some point we might want to get a list of the combinations used by a
707 * shader and fill in those entries instead of having it extract the handles.
710 nve4_set_tex_handles(struct nvc0_context
*nvc0
)
712 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
713 struct nvc0_screen
*screen
= nvc0
->screen
;
716 if (nvc0
->screen
->base
.class_3d
< NVE4_3D_CLASS
)
719 for (s
= 0; s
< 5; ++s
) {
720 uint32_t dirty
= nvc0
->textures_dirty
[s
] | nvc0
->samplers_dirty
[s
];
723 BEGIN_NVC0(push
, NVC0_3D(CB_SIZE
), 3);
724 PUSH_DATA (push
, 2048);
725 PUSH_DATAh(push
, screen
->uniform_bo
->offset
+ NVC0_CB_AUX_INFO(s
));
726 PUSH_DATA (push
, screen
->uniform_bo
->offset
+ NVC0_CB_AUX_INFO(s
));
728 int i
= ffs(dirty
) - 1;
731 BEGIN_NVC0(push
, NVC0_3D(CB_POS
), 2);
732 PUSH_DATA (push
, (8 + i
) * 4);
733 PUSH_DATA (push
, nvc0
->tex_handles
[s
][i
]);
736 nvc0
->textures_dirty
[s
] = 0;
737 nvc0
->samplers_dirty
[s
] = 0;
742 static const uint8_t nve4_su_format_map
[PIPE_FORMAT_COUNT
];
743 static const uint16_t nve4_su_format_aux_map
[PIPE_FORMAT_COUNT
];
744 static const uint16_t nve4_suldp_lib_offset
[PIPE_FORMAT_COUNT
];
747 nvc0_get_surface_dims(struct pipe_image_view
*view
, int *width
, int *height
,
750 struct nv04_resource
*res
= nv04_resource(view
->resource
);
753 *width
= *height
= *depth
= 1;
754 if (res
->base
.target
== PIPE_BUFFER
) {
755 *width
= view
->u
.buf
.last_element
- view
->u
.buf
.first_element
+ 1;
759 level
= view
->u
.tex
.level
;
760 *width
= u_minify(view
->resource
->width0
, level
);
761 *height
= u_minify(view
->resource
->height0
, level
);
762 *depth
= u_minify(view
->resource
->depth0
, level
);
764 switch (res
->base
.target
) {
765 case PIPE_TEXTURE_1D_ARRAY
:
766 case PIPE_TEXTURE_2D_ARRAY
:
767 case PIPE_TEXTURE_CUBE
:
768 case PIPE_TEXTURE_CUBE_ARRAY
:
769 *depth
= view
->u
.tex
.last_layer
- view
->u
.tex
.first_layer
+ 1;
771 case PIPE_TEXTURE_1D
:
772 case PIPE_TEXTURE_2D
:
773 case PIPE_TEXTURE_RECT
:
774 case PIPE_TEXTURE_3D
:
777 assert(!"unexpected texture target");
783 nve4_set_surface_info(struct nouveau_pushbuf
*push
,
784 struct pipe_image_view
*view
,
785 struct nvc0_screen
*screen
)
787 struct nv04_resource
*res
;
789 uint32_t *const info
= push
->cur
;
790 int width
, height
, depth
;
793 if (view
&& !nve4_su_format_map
[view
->format
])
794 NOUVEAU_ERR("unsupported surface format, try is_format_supported() !\n");
798 if (!view
|| !nve4_su_format_map
[view
->format
]) {
799 memset(info
, 0, 16 * sizeof(*info
));
801 info
[0] = 0xbadf0000;
802 info
[1] = 0x80004000;
803 info
[12] = nve4_suldp_lib_offset
[PIPE_FORMAT_R32G32B32A32_UINT
] +
804 screen
->lib_code
->start
;
807 res
= nv04_resource(view
->resource
);
809 address
= res
->address
;
811 /* get surface dimensions based on the target. */
812 nvc0_get_surface_dims(view
, &width
, &height
, &depth
);
817 switch (res
->base
.target
) {
818 case PIPE_TEXTURE_1D_ARRAY
:
821 case PIPE_TEXTURE_2D
:
822 case PIPE_TEXTURE_RECT
:
825 case PIPE_TEXTURE_3D
:
828 case PIPE_TEXTURE_2D_ARRAY
:
829 case PIPE_TEXTURE_CUBE
:
830 case PIPE_TEXTURE_CUBE_ARRAY
:
837 log2cpp
= (0xf000 & nve4_su_format_aux_map
[view
->format
]) >> 12;
839 info
[12] = nve4_suldp_lib_offset
[view
->format
] + screen
->lib_code
->start
;
841 /* limit in bytes for raw access */
842 info
[13] = (0x06 << 22) | ((width
<< log2cpp
) - 1);
844 info
[1] = nve4_su_format_map
[view
->format
];
847 switch (util_format_get_blocksizebits(view
->format
)) {
848 case 16: info
[1] |= 1 << 16; break;
849 case 32: info
[1] |= 2 << 16; break;
850 case 64: info
[1] |= 3 << 16; break;
851 case 128: info
[1] |= 4 << 16; break;
856 info
[1] |= log2cpp
<< 16;
858 info
[1] |= (0x0f00 & nve4_su_format_aux_map
[view
->format
]);
861 if (res
->base
.target
== PIPE_BUFFER
) {
862 info
[0] = address
>> 8;
864 info
[2] |= (0xff & nve4_su_format_aux_map
[view
->format
]) << 22;
873 struct nv50_miptree
*mt
= nv50_miptree(&res
->base
);
874 struct nv50_miptree_level
*lvl
= &mt
->level
[view
->u
.tex
.level
];
875 const unsigned z
= view
->u
.tex
.first_layer
;
879 address
+= nvc0_mt_zslice_offset(mt
, view
->u
.tex
.level
, z
);
880 /* doesn't work if z passes z-tile boundary */
883 address
+= mt
->layer_stride
* z
;
887 info
[0] = address
>> 8;
889 /* NOTE: this is really important: */
890 info
[2] |= (0xff & nve4_su_format_aux_map
[view
->format
]) << 22;
891 info
[3] = (0x88 << 24) | (lvl
->pitch
/ 64);
892 info
[4] = height
- 1;
893 info
[4] |= (lvl
->tile_mode
& 0x0f0) << 25;
894 info
[4] |= NVC0_TILE_SHIFT_Y(lvl
->tile_mode
) << 22;
895 info
[5] = mt
->layer_stride
>> 8;
897 info
[6] |= (lvl
->tile_mode
& 0xf00) << 21;
898 info
[6] |= NVC0_TILE_SHIFT_Z(lvl
->tile_mode
) << 22;
906 nvc0_update_surface_bindings(struct nvc0_context
*nvc0
)
912 nve4_update_surface_bindings(struct nvc0_context
*nvc0
)
914 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
915 struct nvc0_screen
*screen
= nvc0
->screen
;
918 for (s
= 0; s
< 5; s
++) {
919 if (!nvc0
->images_dirty
[s
])
922 BEGIN_NVC0(push
, NVC0_3D(CB_SIZE
), 3);
923 PUSH_DATA (push
, 2048);
924 PUSH_DATAh(push
, screen
->uniform_bo
->offset
+ NVC0_CB_AUX_INFO(s
));
925 PUSH_DATA (push
, screen
->uniform_bo
->offset
+ NVC0_CB_AUX_INFO(s
));
926 BEGIN_1IC0(push
, NVC0_3D(CB_POS
), 1 + 16 * NVC0_MAX_IMAGES
);
927 PUSH_DATA (push
, NVC0_CB_AUX_SU_INFO(0));
929 for (i
= 0; i
< NVC0_MAX_IMAGES
; ++i
) {
930 struct pipe_image_view
*view
= &nvc0
->images
[s
][i
];
931 if (view
->resource
) {
932 struct nv04_resource
*res
= nv04_resource(view
->resource
);
934 nve4_set_surface_info(push
, view
, screen
);
935 BCTX_REFN(nvc0
->bufctx_3d
, 3D_SUF
, res
, RDWR
);
937 for (j
= 0; j
< 16; j
++)
945 nvc0_validate_surfaces(struct nvc0_context
*nvc0
)
947 if (nvc0
->screen
->base
.class_3d
>= NVE4_3D_CLASS
) {
948 nve4_update_surface_bindings(nvc0
);
950 nvc0_update_surface_bindings(nvc0
);
955 static const uint8_t nve4_su_format_map
[PIPE_FORMAT_COUNT
] =
957 [PIPE_FORMAT_R32G32B32A32_FLOAT
] = GK104_IMAGE_FORMAT_RGBA32_FLOAT
,
958 [PIPE_FORMAT_R32G32B32A32_SINT
] = GK104_IMAGE_FORMAT_RGBA32_SINT
,
959 [PIPE_FORMAT_R32G32B32A32_UINT
] = GK104_IMAGE_FORMAT_RGBA32_UINT
,
960 [PIPE_FORMAT_R16G16B16A16_FLOAT
] = GK104_IMAGE_FORMAT_RGBA16_FLOAT
,
961 [PIPE_FORMAT_R16G16B16A16_UNORM
] = GK104_IMAGE_FORMAT_RGBA16_UNORM
,
962 [PIPE_FORMAT_R16G16B16A16_SNORM
] = GK104_IMAGE_FORMAT_RGBA16_SNORM
,
963 [PIPE_FORMAT_R16G16B16A16_SINT
] = GK104_IMAGE_FORMAT_RGBA16_SINT
,
964 [PIPE_FORMAT_R16G16B16A16_UINT
] = GK104_IMAGE_FORMAT_RGBA16_UINT
,
965 [PIPE_FORMAT_R8G8B8A8_UNORM
] = GK104_IMAGE_FORMAT_RGBA8_UNORM
,
966 [PIPE_FORMAT_R8G8B8A8_SNORM
] = GK104_IMAGE_FORMAT_RGBA8_SNORM
,
967 [PIPE_FORMAT_R8G8B8A8_SINT
] = GK104_IMAGE_FORMAT_RGBA8_SINT
,
968 [PIPE_FORMAT_R8G8B8A8_UINT
] = GK104_IMAGE_FORMAT_RGBA8_UINT
,
969 [PIPE_FORMAT_R11G11B10_FLOAT
] = GK104_IMAGE_FORMAT_R11G11B10_FLOAT
,
970 [PIPE_FORMAT_R10G10B10A2_UNORM
] = GK104_IMAGE_FORMAT_RGB10_A2_UNORM
,
971 /* [PIPE_FORMAT_R10G10B10A2_UINT] = GK104_IMAGE_FORMAT_RGB10_A2_UINT, */
972 [PIPE_FORMAT_R32G32_FLOAT
] = GK104_IMAGE_FORMAT_RG32_FLOAT
,
973 [PIPE_FORMAT_R32G32_SINT
] = GK104_IMAGE_FORMAT_RG32_SINT
,
974 [PIPE_FORMAT_R32G32_UINT
] = GK104_IMAGE_FORMAT_RG32_UINT
,
975 [PIPE_FORMAT_R16G16_FLOAT
] = GK104_IMAGE_FORMAT_RG16_FLOAT
,
976 [PIPE_FORMAT_R16G16_UNORM
] = GK104_IMAGE_FORMAT_RG16_UNORM
,
977 [PIPE_FORMAT_R16G16_SNORM
] = GK104_IMAGE_FORMAT_RG16_SNORM
,
978 [PIPE_FORMAT_R16G16_SINT
] = GK104_IMAGE_FORMAT_RG16_SINT
,
979 [PIPE_FORMAT_R16G16_UINT
] = GK104_IMAGE_FORMAT_RG16_UINT
,
980 [PIPE_FORMAT_R8G8_UNORM
] = GK104_IMAGE_FORMAT_RG8_UNORM
,
981 [PIPE_FORMAT_R8G8_SNORM
] = GK104_IMAGE_FORMAT_RG8_SNORM
,
982 [PIPE_FORMAT_R8G8_SINT
] = GK104_IMAGE_FORMAT_RG8_SINT
,
983 [PIPE_FORMAT_R8G8_UINT
] = GK104_IMAGE_FORMAT_RG8_UINT
,
984 [PIPE_FORMAT_R32_FLOAT
] = GK104_IMAGE_FORMAT_R32_FLOAT
,
985 [PIPE_FORMAT_R32_SINT
] = GK104_IMAGE_FORMAT_R32_SINT
,
986 [PIPE_FORMAT_R32_UINT
] = GK104_IMAGE_FORMAT_R32_UINT
,
987 [PIPE_FORMAT_R16_FLOAT
] = GK104_IMAGE_FORMAT_R16_FLOAT
,
988 [PIPE_FORMAT_R16_UNORM
] = GK104_IMAGE_FORMAT_R16_UNORM
,
989 [PIPE_FORMAT_R16_SNORM
] = GK104_IMAGE_FORMAT_R16_SNORM
,
990 [PIPE_FORMAT_R16_SINT
] = GK104_IMAGE_FORMAT_R16_SINT
,
991 [PIPE_FORMAT_R16_UINT
] = GK104_IMAGE_FORMAT_R16_UINT
,
992 [PIPE_FORMAT_R8_UNORM
] = GK104_IMAGE_FORMAT_R8_UNORM
,
993 [PIPE_FORMAT_R8_SNORM
] = GK104_IMAGE_FORMAT_R8_SNORM
,
994 [PIPE_FORMAT_R8_SINT
] = GK104_IMAGE_FORMAT_R8_SINT
,
995 [PIPE_FORMAT_R8_UINT
] = GK104_IMAGE_FORMAT_R8_UINT
,
998 /* Auxiliary format description values for surface instructions.
999 * (log2(bytes per pixel) << 12) | (unk8 << 8) | unk22
1001 static const uint16_t nve4_su_format_aux_map
[PIPE_FORMAT_COUNT
] =
1003 [PIPE_FORMAT_R32G32B32A32_FLOAT
] = 0x4842,
1004 [PIPE_FORMAT_R32G32B32A32_SINT
] = 0x4842,
1005 [PIPE_FORMAT_R32G32B32A32_UINT
] = 0x4842,
1007 [PIPE_FORMAT_R16G16B16A16_UNORM
] = 0x3933,
1008 [PIPE_FORMAT_R16G16B16A16_SNORM
] = 0x3933,
1009 [PIPE_FORMAT_R16G16B16A16_SINT
] = 0x3933,
1010 [PIPE_FORMAT_R16G16B16A16_UINT
] = 0x3933,
1011 [PIPE_FORMAT_R16G16B16A16_FLOAT
] = 0x3933,
1013 [PIPE_FORMAT_R32G32_FLOAT
] = 0x3433,
1014 [PIPE_FORMAT_R32G32_SINT
] = 0x3433,
1015 [PIPE_FORMAT_R32G32_UINT
] = 0x3433,
1017 [PIPE_FORMAT_R10G10B10A2_UNORM
] = 0x2a24,
1018 /* [PIPE_FORMAT_R10G10B10A2_UINT] = 0x2a24, */
1019 [PIPE_FORMAT_R8G8B8A8_UNORM
] = 0x2a24,
1020 [PIPE_FORMAT_R8G8B8A8_SNORM
] = 0x2a24,
1021 [PIPE_FORMAT_R8G8B8A8_SINT
] = 0x2a24,
1022 [PIPE_FORMAT_R8G8B8A8_UINT
] = 0x2a24,
1023 [PIPE_FORMAT_R11G11B10_FLOAT
] = 0x2a24,
1025 [PIPE_FORMAT_R16G16_UNORM
] = 0x2524,
1026 [PIPE_FORMAT_R16G16_SNORM
] = 0x2524,
1027 [PIPE_FORMAT_R16G16_SINT
] = 0x2524,
1028 [PIPE_FORMAT_R16G16_UINT
] = 0x2524,
1029 [PIPE_FORMAT_R16G16_FLOAT
] = 0x2524,
1031 [PIPE_FORMAT_R32_SINT
] = 0x2024,
1032 [PIPE_FORMAT_R32_UINT
] = 0x2024,
1033 [PIPE_FORMAT_R32_FLOAT
] = 0x2024,
1035 [PIPE_FORMAT_R8G8_UNORM
] = 0x1615,
1036 [PIPE_FORMAT_R8G8_SNORM
] = 0x1615,
1037 [PIPE_FORMAT_R8G8_SINT
] = 0x1615,
1038 [PIPE_FORMAT_R8G8_UINT
] = 0x1615,
1040 [PIPE_FORMAT_R16_UNORM
] = 0x1115,
1041 [PIPE_FORMAT_R16_SNORM
] = 0x1115,
1042 [PIPE_FORMAT_R16_SINT
] = 0x1115,
1043 [PIPE_FORMAT_R16_UINT
] = 0x1115,
1044 [PIPE_FORMAT_R16_FLOAT
] = 0x1115,
1046 [PIPE_FORMAT_R8_UNORM
] = 0x0206,
1047 [PIPE_FORMAT_R8_SNORM
] = 0x0206,
1048 [PIPE_FORMAT_R8_SINT
] = 0x0206,
1049 [PIPE_FORMAT_R8_UINT
] = 0x0206
1052 /* NOTE: These are hardcoded offsets for the shader library.
1053 * TODO: Automate them.
1055 static const uint16_t nve4_suldp_lib_offset
[PIPE_FORMAT_COUNT
] =
1057 [PIPE_FORMAT_R32G32B32A32_FLOAT
] = 0x218,
1058 [PIPE_FORMAT_R32G32B32A32_SINT
] = 0x218,
1059 [PIPE_FORMAT_R32G32B32A32_UINT
] = 0x218,
1060 [PIPE_FORMAT_R16G16B16A16_UNORM
] = 0x248,
1061 [PIPE_FORMAT_R16G16B16A16_SNORM
] = 0x2b8,
1062 [PIPE_FORMAT_R16G16B16A16_SINT
] = 0x330,
1063 [PIPE_FORMAT_R16G16B16A16_UINT
] = 0x388,
1064 [PIPE_FORMAT_R16G16B16A16_FLOAT
] = 0x3d8,
1065 [PIPE_FORMAT_R32G32_FLOAT
] = 0x428,
1066 [PIPE_FORMAT_R32G32_SINT
] = 0x468,
1067 [PIPE_FORMAT_R32G32_UINT
] = 0x468,
1068 [PIPE_FORMAT_R10G10B10A2_UNORM
] = 0x4a8,
1069 /* [PIPE_FORMAT_R10G10B10A2_UINT] = 0x530, */
1070 [PIPE_FORMAT_R8G8B8A8_UNORM
] = 0x588,
1071 [PIPE_FORMAT_R8G8B8A8_SNORM
] = 0x5f8,
1072 [PIPE_FORMAT_R8G8B8A8_SINT
] = 0x670,
1073 [PIPE_FORMAT_R8G8B8A8_UINT
] = 0x6c8,
1074 [PIPE_FORMAT_B5G6R5_UNORM
] = 0x718,
1075 [PIPE_FORMAT_B5G5R5X1_UNORM
] = 0x7a0,
1076 [PIPE_FORMAT_R16G16_UNORM
] = 0x828,
1077 [PIPE_FORMAT_R16G16_SNORM
] = 0x890,
1078 [PIPE_FORMAT_R16G16_SINT
] = 0x8f0,
1079 [PIPE_FORMAT_R16G16_UINT
] = 0x948,
1080 [PIPE_FORMAT_R16G16_FLOAT
] = 0x998,
1081 [PIPE_FORMAT_R32_FLOAT
] = 0x9e8,
1082 [PIPE_FORMAT_R32_SINT
] = 0xa30,
1083 [PIPE_FORMAT_R32_UINT
] = 0xa30,
1084 [PIPE_FORMAT_R8G8_UNORM
] = 0xa78,
1085 [PIPE_FORMAT_R8G8_SNORM
] = 0xae0,
1086 [PIPE_FORMAT_R8G8_UINT
] = 0xb48,
1087 [PIPE_FORMAT_R8G8_SINT
] = 0xb98,
1088 [PIPE_FORMAT_R16_UNORM
] = 0xbe8,
1089 [PIPE_FORMAT_R16_SNORM
] = 0xc48,
1090 [PIPE_FORMAT_R16_SINT
] = 0xca0,
1091 [PIPE_FORMAT_R16_UINT
] = 0xce8,
1092 [PIPE_FORMAT_R16_FLOAT
] = 0xd30,
1093 [PIPE_FORMAT_R8_UNORM
] = 0xd88,
1094 [PIPE_FORMAT_R8_SNORM
] = 0xde0,
1095 [PIPE_FORMAT_R8_SINT
] = 0xe38,
1096 [PIPE_FORMAT_R8_UINT
] = 0xe88,
1097 [PIPE_FORMAT_R11G11B10_FLOAT
] = 0xed0