projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
nvc0: switch nvc0_tex.c to updated g80_texture.xml.h
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_tex.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "nvc0/nvc0_context.h"
24 #include "nvc0/nvc0_resource.h"
25 #include "nv50/g80_texture.xml.h"
26 #include "nv50/g80_defs.xml.h"
27
28 #include "util/u_format.h"
29
30 #define NVE4_TIC_ENTRY_INVALID 0x000fffff
31 #define NVE4_TSC_ENTRY_INVALID 0xfff00000
32
33 #define G80_TIC_0_SWIZZLE__MASK \
34 (G80_TIC_0_W_SOURCE__MASK | G80_TIC_0_Z_SOURCE__MASK | \
35 G80_TIC_0_Y_SOURCE__MASK | G80_TIC_0_X_SOURCE__MASK)
36
37 static inline uint32_t
38 nv50_tic_swizzle(uint32_t tc, unsigned swz, bool tex_int)
39 {
40 switch (swz) {
41 case PIPE_SWIZZLE_RED:
42 return (tc & G80_TIC_0_X_SOURCE__MASK) >> G80_TIC_0_X_SOURCE__SHIFT;
43 case PIPE_SWIZZLE_GREEN:
44 return (tc & G80_TIC_0_Y_SOURCE__MASK) >> G80_TIC_0_Y_SOURCE__SHIFT;
45 case PIPE_SWIZZLE_BLUE:
46 return (tc & G80_TIC_0_Z_SOURCE__MASK) >> G80_TIC_0_Z_SOURCE__SHIFT;
47 case PIPE_SWIZZLE_ALPHA:
48 return (tc & G80_TIC_0_W_SOURCE__MASK) >> G80_TIC_0_W_SOURCE__SHIFT;
49 case PIPE_SWIZZLE_ONE:
50 return tex_int ? G80_TIC_SOURCE_ONE_INT : G80_TIC_SOURCE_ONE_FLOAT;
51 case PIPE_SWIZZLE_ZERO:
52 default:
53 return G80_TIC_SOURCE_ZERO;
54 }
55 }
56
57 struct pipe_sampler_view *
58 nvc0_create_sampler_view(struct pipe_context *pipe,
59 struct pipe_resource *res,
60 const struct pipe_sampler_view *templ)
61 {
62 uint32_t flags = 0;
63
64 if (templ->target == PIPE_TEXTURE_RECT || templ->target == PIPE_BUFFER)
65 flags |= NV50_TEXVIEW_SCALED_COORDS;
66
67 return nvc0_create_texture_view(pipe, res, templ, flags, templ->target);
68 }
69
70 struct pipe_sampler_view *
71 nvc0_create_texture_view(struct pipe_context *pipe,
72 struct pipe_resource *texture,
73 const struct pipe_sampler_view *templ,
74 uint32_t flags,
75 enum pipe_texture_target target)
76 {
77 const struct util_format_description *desc;
78 uint64_t address;
79 uint32_t *tic;
80 uint32_t swz[4];
81 uint32_t width, height;
82 uint32_t depth;
83 struct nv50_tic_entry *view;
84 struct nv50_miptree *mt;
85 bool tex_int;
86
87 view = MALLOC_STRUCT(nv50_tic_entry);
88 if (!view)
89 return NULL;
90 mt = nv50_miptree(texture);
91
92 view->pipe = *templ;
93 view->pipe.reference.count = 1;
94 view->pipe.texture = NULL;
95 view->pipe.context = pipe;
96
97 view->id = -1;
98
99 pipe_resource_reference(&view->pipe.texture, texture);
100
101 tic = &view->tic[0];
102
103 desc = util_format_description(view->pipe.format);
104
105 tic[0] = nvc0_format_table[view->pipe.format].tic;
106
107 tex_int = util_format_is_pure_integer(view->pipe.format);
108
109 swz[0] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_r, tex_int);
110 swz[1] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_g, tex_int);
111 swz[2] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_b, tex_int);
112 swz[3] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_a, tex_int);
113 tic[0] = (tic[0] & ~G80_TIC_0_SWIZZLE__MASK) |
114 (swz[0] << G80_TIC_0_X_SOURCE__SHIFT) |
115 (swz[1] << G80_TIC_0_Y_SOURCE__SHIFT) |
116 (swz[2] << G80_TIC_0_Z_SOURCE__SHIFT) |
117 (swz[3] << G80_TIC_0_W_SOURCE__SHIFT);
118
119 address = mt->base.address;
120
121 tic[2] = 0x10001000 | G80_TIC_2_BORDER_SOURCE_COLOR;
122
123 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
124 tic[2] |= G80_TIC_2_SRGB_CONVERSION;
125
126 if (!(flags & NV50_TEXVIEW_SCALED_COORDS))
127 tic[2] |= G80_TIC_2_NORMALIZED_COORDS;
128
129 /* check for linear storage type */
130 if (unlikely(!nouveau_bo_memtype(nv04_resource(texture)->bo))) {
131 if (texture->target == PIPE_BUFFER) {
132 assert(!(tic[2] & G80_TIC_2_NORMALIZED_COORDS));
133 address +=
134 view->pipe.u.buf.first_element * desc->block.bits / 8;
135 tic[2] |= G80_TIC_2_LAYOUT_PITCH | G80_TIC_2_TEXTURE_TYPE_ONE_D_BUFFER;
136 tic[3] = 0;
137 tic[4] = /* width */
138 view->pipe.u.buf.last_element - view->pipe.u.buf.first_element + 1;
139 tic[5] = 0;
140 } else {
141 /* must be 2D texture without mip maps */
142 tic[2] |= G80_TIC_2_LAYOUT_PITCH | G80_TIC_2_TEXTURE_TYPE_TWO_D_NO_MIPMAP;
143 tic[3] = mt->level[0].pitch;
144 tic[4] = mt->base.base.width0;
145 tic[5] = (1 << 16) | mt->base.base.height0;
146 }
147 tic[6] =
148 tic[7] = 0;
149 tic[1] = address;
150 tic[2] |= address >> 32;
151 return &view->pipe;
152 }
153
154 tic[2] |=
155 ((mt->level[0].tile_mode & 0x0f0) << (22 - 4)) |
156 ((mt->level[0].tile_mode & 0xf00) << (25 - 8));
157
158 depth = MAX2(mt->base.base.array_size, mt->base.base.depth0);
159
160 if (mt->base.base.array_size > 1) {
161 /* there doesn't seem to be a base layer field in TIC */
162 address += view->pipe.u.tex.first_layer * mt->layer_stride;
163 depth = view->pipe.u.tex.last_layer - view->pipe.u.tex.first_layer + 1;
164 }
165 tic[1] = address;
166 tic[2] |= address >> 32;
167
168 switch (target) {
169 case PIPE_TEXTURE_1D:
170 tic[2] |= G80_TIC_2_TEXTURE_TYPE_ONE_D;
171 break;
172 case PIPE_TEXTURE_2D:
173 tic[2] |= G80_TIC_2_TEXTURE_TYPE_TWO_D;
174 break;
175 case PIPE_TEXTURE_RECT:
176 tic[2] |= G80_TIC_2_TEXTURE_TYPE_TWO_D;
177 break;
178 case PIPE_TEXTURE_3D:
179 tic[2] |= G80_TIC_2_TEXTURE_TYPE_THREE_D;
180 break;
181 case PIPE_TEXTURE_CUBE:
182 depth /= 6;
183 tic[2] |= G80_TIC_2_TEXTURE_TYPE_CUBEMAP;
184 break;
185 case PIPE_TEXTURE_1D_ARRAY:
186 tic[2] |= G80_TIC_2_TEXTURE_TYPE_ONE_D_ARRAY;
187 break;
188 case PIPE_TEXTURE_2D_ARRAY:
189 tic[2] |= G80_TIC_2_TEXTURE_TYPE_TWO_D_ARRAY;
190 break;
191 case PIPE_TEXTURE_CUBE_ARRAY:
192 depth /= 6;
193 tic[2] |= G80_TIC_2_TEXTURE_TYPE_CUBE_ARRAY;
194 break;
195 default:
196 unreachable("unexpected/invalid texture target");
197 }
198
199 tic[3] = (flags & NV50_TEXVIEW_FILTER_MSAA8) ? 0x20000000 : 0x00300000;
200
201 if (flags & NV50_TEXVIEW_ACCESS_RESOLVE) {
202 width = mt->base.base.width0 << mt->ms_x;
203 height = mt->base.base.height0 << mt->ms_y;
204 } else {
205 width = mt->base.base.width0;
206 height = mt->base.base.height0;
207 }
208
209 tic[4] = (1 << 31) | width;
210
211 tic[5] = height & 0xffff;
212 tic[5] |= depth << 16;
213 tic[5] |= mt->base.base.last_level << 28;
214
215 /* sampling points: (?) */
216 if (flags & NV50_TEXVIEW_ACCESS_RESOLVE)
217 tic[6] = (mt->ms_x > 1) ? 0x88000000 : 0x03000000;
218 else
219 tic[6] = 0x03000000;
220
221 tic[7] = (view->pipe.u.tex.last_level << 4) | view->pipe.u.tex.first_level;
222 tic[7] |= mt->ms_mode << 12;
223
224 return &view->pipe;
225 }
226
227 static void
228 nvc0_update_tic(struct nvc0_context *nvc0, struct nv50_tic_entry *tic,
229 struct nv04_resource *res)
230 {
231 uint64_t address = res->address;
232 if (res->base.target != PIPE_BUFFER)
233 return;
234 address += tic->pipe.u.buf.first_element *
235 util_format_get_blocksize(tic->pipe.format);
236 if (tic->tic[1] == (uint32_t)address &&
237 (tic->tic[2] & 0xff) == address >> 32)
238 return;
239
240 nvc0_screen_tic_unlock(nvc0->screen, tic);
241 tic->id = -1;
242 tic->tic[1] = address;
243 tic->tic[2] &= 0xffffff00;
244 tic->tic[2] |= address >> 32;
245 }
246
247 static bool
248 nvc0_validate_tic(struct nvc0_context *nvc0, int s)
249 {
250 uint32_t commands[32];
251 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
252 struct nouveau_bo *txc = nvc0->screen->txc;
253 unsigned i;
254 unsigned n = 0;
255 bool need_flush = false;
256
257 for (i = 0; i < nvc0->num_textures[s]; ++i) {
258 struct nv50_tic_entry *tic = nv50_tic_entry(nvc0->textures[s][i]);
259 struct nv04_resource *res;
260 const bool dirty = !!(nvc0->textures_dirty[s] & (1 << i));
261
262 if (!tic) {
263 if (dirty)
264 commands[n++] = (i << 1) | 0;
265 continue;
266 }
267 res = nv04_resource(tic->pipe.texture);
268 nvc0_update_tic(nvc0, tic, res);
269
270 if (tic->id < 0) {
271 tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
272
273 PUSH_SPACE(push, 17);
274 BEGIN_NVC0(push, NVC0_M2MF(OFFSET_OUT_HIGH), 2);
275 PUSH_DATAh(push, txc->offset + (tic->id * 32));
276 PUSH_DATA (push, txc->offset + (tic->id * 32));
277 BEGIN_NVC0(push, NVC0_M2MF(LINE_LENGTH_IN), 2);
278 PUSH_DATA (push, 32);
279 PUSH_DATA (push, 1);
280 BEGIN_NVC0(push, NVC0_M2MF(EXEC), 1);
281 PUSH_DATA (push, 0x100111);
282 BEGIN_NIC0(push, NVC0_M2MF(DATA), 8);
283 PUSH_DATAp(push, &tic->tic[0], 8);
284
285 need_flush = true;
286 } else
287 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
288 BEGIN_NVC0(push, NVC0_3D(TEX_CACHE_CTL), 1);
289 PUSH_DATA (push, (tic->id << 4) | 1);
290 NOUVEAU_DRV_STAT(&nvc0->screen->base, tex_cache_flush_count, 1);
291 }
292 nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
293
294 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
295 res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
296
297 if (!dirty)
298 continue;
299 commands[n++] = (tic->id << 9) | (i << 1) | 1;
300
301 BCTX_REFN(nvc0->bufctx_3d, TEX(s, i), res, RD);
302 }
303 for (; i < nvc0->state.num_textures[s]; ++i)
304 commands[n++] = (i << 1) | 0;
305
306 nvc0->state.num_textures[s] = nvc0->num_textures[s];
307
308 if (n) {
309 BEGIN_NIC0(push, NVC0_3D(BIND_TIC(s)), n);
310 PUSH_DATAp(push, commands, n);
311 }
312 nvc0->textures_dirty[s] = 0;
313
314 return need_flush;
315 }
316
317 static bool
318 nve4_validate_tic(struct nvc0_context *nvc0, unsigned s)
319 {
320 struct nouveau_bo *txc = nvc0->screen->txc;
321 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
322 unsigned i;
323 bool need_flush = false;
324
325 for (i = 0; i < nvc0->num_textures[s]; ++i) {
326 struct nv50_tic_entry *tic = nv50_tic_entry(nvc0->textures[s][i]);
327 struct nv04_resource *res;
328 const bool dirty = !!(nvc0->textures_dirty[s] & (1 << i));
329
330 if (!tic) {
331 nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID;
332 continue;
333 }
334 res = nv04_resource(tic->pipe.texture);
335 nvc0_update_tic(nvc0, tic, res);
336
337 if (tic->id < 0) {
338 tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
339
340 PUSH_SPACE(push, 16);
341 BEGIN_NVC0(push, NVE4_P2MF(UPLOAD_DST_ADDRESS_HIGH), 2);
342 PUSH_DATAh(push, txc->offset + (tic->id * 32));
343 PUSH_DATA (push, txc->offset + (tic->id * 32));
344 BEGIN_NVC0(push, NVE4_P2MF(UPLOAD_LINE_LENGTH_IN), 2);
345 PUSH_DATA (push, 32);
346 PUSH_DATA (push, 1);
347 BEGIN_1IC0(push, NVE4_P2MF(UPLOAD_EXEC), 9);
348 PUSH_DATA (push, 0x1001);
349 PUSH_DATAp(push, &tic->tic[0], 8);
350
351 need_flush = true;
352 } else
353 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
354 BEGIN_NVC0(push, NVC0_3D(TEX_CACHE_CTL), 1);
355 PUSH_DATA (push, (tic->id << 4) | 1);
356 }
357 nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
358
359 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
360 res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
361
362 nvc0->tex_handles[s][i] &= ~NVE4_TIC_ENTRY_INVALID;
363 nvc0->tex_handles[s][i] |= tic->id;
364 if (dirty)
365 BCTX_REFN(nvc0->bufctx_3d, TEX(s, i), res, RD);
366 }
367 for (; i < nvc0->state.num_textures[s]; ++i) {
368 nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID;
369 nvc0->textures_dirty[s] |= 1 << i;
370 }
371
372 nvc0->state.num_textures[s] = nvc0->num_textures[s];
373
374 return need_flush;
375 }
376
377 void nvc0_validate_textures(struct nvc0_context *nvc0)
378 {
379 bool need_flush = false;
380 int i;
381
382 for (i = 0; i < 5; i++) {
383 if (nvc0->screen->base.class_3d >= NVE4_3D_CLASS)
384 need_flush |= nve4_validate_tic(nvc0, i);
385 else
386 need_flush |= nvc0_validate_tic(nvc0, i);
387 }
388
389 if (need_flush) {
390 BEGIN_NVC0(nvc0->base.pushbuf, NVC0_3D(TIC_FLUSH), 1);
391 PUSH_DATA (nvc0->base.pushbuf, 0);
392 }
393 }
394
395 static bool
396 nvc0_validate_tsc(struct nvc0_context *nvc0, int s)
397 {
398 uint32_t commands[16];
399 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
400 unsigned i;
401 unsigned n = 0;
402 bool need_flush = false;
403
404 for (i = 0; i < nvc0->num_samplers[s]; ++i) {
405 struct nv50_tsc_entry *tsc = nv50_tsc_entry(nvc0->samplers[s][i]);
406
407 if (!(nvc0->samplers_dirty[s] & (1 << i)))
408 continue;
409 if (!tsc) {
410 commands[n++] = (i << 4) | 0;
411 continue;
412 }
413 if (tsc->id < 0) {
414 tsc->id = nvc0_screen_tsc_alloc(nvc0->screen, tsc);
415
416 nvc0_m2mf_push_linear(&nvc0->base, nvc0->screen->txc,
417 65536 + tsc->id * 32, NV_VRAM_DOMAIN(&nvc0->screen->base),
418 32, tsc->tsc);
419 need_flush = true;
420 }
421 nvc0->screen->tsc.lock[tsc->id / 32] |= 1 << (tsc->id % 32);
422
423 commands[n++] = (tsc->id << 12) | (i << 4) | 1;
424 }
425 for (; i < nvc0->state.num_samplers[s]; ++i)
426 commands[n++] = (i << 4) | 0;
427
428 nvc0->state.num_samplers[s] = nvc0->num_samplers[s];
429
430 if (n) {
431 BEGIN_NIC0(push, NVC0_3D(BIND_TSC(s)), n);
432 PUSH_DATAp(push, commands, n);
433 }
434 nvc0->samplers_dirty[s] = 0;
435
436 return need_flush;
437 }
438
439 bool
440 nve4_validate_tsc(struct nvc0_context *nvc0, int s)
441 {
442 struct nouveau_bo *txc = nvc0->screen->txc;
443 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
444 unsigned i;
445 bool need_flush = false;
446
447 for (i = 0; i < nvc0->num_samplers[s]; ++i) {
448 struct nv50_tsc_entry *tsc = nv50_tsc_entry(nvc0->samplers[s][i]);
449
450 if (!tsc) {
451 nvc0->tex_handles[s][i] |= NVE4_TSC_ENTRY_INVALID;
452 continue;
453 }
454 if (tsc->id < 0) {
455 tsc->id = nvc0_screen_tsc_alloc(nvc0->screen, tsc);
456
457 PUSH_SPACE(push, 16);
458 BEGIN_NVC0(push, NVE4_P2MF(UPLOAD_DST_ADDRESS_HIGH), 2);
459 PUSH_DATAh(push, txc->offset + 65536 + (tsc->id * 32));
460 PUSH_DATA (push, txc->offset + 65536 + (tsc->id * 32));
461 BEGIN_NVC0(push, NVE4_P2MF(UPLOAD_LINE_LENGTH_IN), 2);
462 PUSH_DATA (push, 32);
463 PUSH_DATA (push, 1);
464 BEGIN_1IC0(push, NVE4_P2MF(UPLOAD_EXEC), 9);
465 PUSH_DATA (push, 0x1001);
466 PUSH_DATAp(push, &tsc->tsc[0], 8);
467
468 need_flush = true;
469 }
470 nvc0->screen->tsc.lock[tsc->id / 32] |= 1 << (tsc->id % 32);
471
472 nvc0->tex_handles[s][i] &= ~NVE4_TSC_ENTRY_INVALID;
473 nvc0->tex_handles[s][i] |= tsc->id << 20;
474 }
475 for (; i < nvc0->state.num_samplers[s]; ++i) {
476 nvc0->tex_handles[s][i] |= NVE4_TSC_ENTRY_INVALID;
477 nvc0->samplers_dirty[s] |= 1 << i;
478 }
479
480 nvc0->state.num_samplers[s] = nvc0->num_samplers[s];
481
482 return need_flush;
483 }
484
485 void nvc0_validate_samplers(struct nvc0_context *nvc0)
486 {
487 bool need_flush = false;
488 int i;
489
490 for (i = 0; i < 5; i++) {
491 if (nvc0->screen->base.class_3d >= NVE4_3D_CLASS)
492 need_flush |= nve4_validate_tsc(nvc0, i);
493 else
494 need_flush |= nvc0_validate_tsc(nvc0, i);
495 }
496
497 if (need_flush) {
498 BEGIN_NVC0(nvc0->base.pushbuf, NVC0_3D(TSC_FLUSH), 1);
499 PUSH_DATA (nvc0->base.pushbuf, 0);
500 }
501 }
502
503 /* Upload the "diagonal" entries for the possible texture sources ($t == $s).
504 * At some point we might want to get a list of the combinations used by a
505 * shader and fill in those entries instead of having it extract the handles.
506 */
507 void
508 nve4_set_tex_handles(struct nvc0_context *nvc0)
509 {
510 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
511 uint64_t address;
512 unsigned s;
513
514 if (nvc0->screen->base.class_3d < NVE4_3D_CLASS)
515 return;
516 address = nvc0->screen->uniform_bo->offset + (5 << 16);
517
518 for (s = 0; s < 5; ++s, address += (1 << 10)) {
519 uint32_t dirty = nvc0->textures_dirty[s] | nvc0->samplers_dirty[s];
520 if (!dirty)
521 continue;
522 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
523 PUSH_DATA (push, 1024);
524 PUSH_DATAh(push, address);
525 PUSH_DATA (push, address);
526 do {
527 int i = ffs(dirty) - 1;
528 dirty &= ~(1 << i);
529
530 BEGIN_NVC0(push, NVC0_3D(CB_POS), 2);
531 PUSH_DATA (push, (8 + i) * 4);
532 PUSH_DATA (push, nvc0->tex_handles[s][i]);
533 } while (dirty);
534
535 nvc0->textures_dirty[s] = 0;
536 nvc0->samplers_dirty[s] = 0;
537 }
538 }
539
540
541 static const uint8_t nve4_su_format_map[PIPE_FORMAT_COUNT];
542 static const uint16_t nve4_su_format_aux_map[PIPE_FORMAT_COUNT];
543 static const uint16_t nve4_suldp_lib_offset[PIPE_FORMAT_COUNT];
544
545 void
546 nve4_set_surface_info(struct nouveau_pushbuf *push,
547 struct pipe_surface *psf,
548 struct nvc0_screen *screen)
549 {
550 struct nv50_surface *sf = nv50_surface(psf);
551 struct nv04_resource *res;
552 uint64_t address;
553 uint32_t *const info = push->cur;
554 uint8_t log2cpp;
555
556 if (psf && !nve4_su_format_map[psf->format])
557 NOUVEAU_ERR("unsupported surface format, try is_format_supported() !\n");
558
559 push->cur += 16;
560
561 if (!psf || !nve4_su_format_map[psf->format]) {
562 memset(info, 0, 16 * sizeof(*info));
563
564 info[0] = 0xbadf0000;
565 info[1] = 0x80004000;
566 info[12] = nve4_suldp_lib_offset[PIPE_FORMAT_R32G32B32A32_UINT] +
567 screen->lib_code->start;
568 return;
569 }
570 res = nv04_resource(sf->base.texture);
571
572 address = res->address + sf->offset;
573
574 info[8] = sf->width;
575 info[9] = sf->height;
576 info[10] = sf->depth;
577 switch (res->base.target) {
578 case PIPE_TEXTURE_1D_ARRAY:
579 info[11] = 1;
580 break;
581 case PIPE_TEXTURE_2D:
582 case PIPE_TEXTURE_RECT:
583 info[11] = 2;
584 break;
585 case PIPE_TEXTURE_3D:
586 info[11] = 3;
587 break;
588 case PIPE_TEXTURE_2D_ARRAY:
589 case PIPE_TEXTURE_CUBE:
590 case PIPE_TEXTURE_CUBE_ARRAY:
591 info[11] = 4;
592 break;
593 default:
594 info[11] = 0;
595 break;
596 }
597 log2cpp = (0xf000 & nve4_su_format_aux_map[sf->base.format]) >> 12;
598
599 info[12] = nve4_suldp_lib_offset[sf->base.format] + screen->lib_code->start;
600
601 /* limit in bytes for raw access */
602 info[13] = (0x06 << 22) | ((sf->width << log2cpp) - 1);
603
604 info[1] = nve4_su_format_map[sf->base.format];
605
606 #if 0
607 switch (util_format_get_blocksizebits(sf->base.format)) {
608 case 16: info[1] |= 1 << 16; break;
609 case 32: info[1] |= 2 << 16; break;
610 case 64: info[1] |= 3 << 16; break;
611 case 128: info[1] |= 4 << 16; break;
612 default:
613 break;
614 }
615 #else
616 info[1] |= log2cpp << 16;
617 info[1] |= 0x4000;
618 info[1] |= (0x0f00 & nve4_su_format_aux_map[sf->base.format]);
619 #endif
620
621 if (res->base.target == PIPE_BUFFER) {
622 info[0] = address >> 8;
623 info[2] = sf->width - 1;
624 info[2] |= (0xff & nve4_su_format_aux_map[sf->base.format]) << 22;
625 info[3] = 0;
626 info[4] = 0;
627 info[5] = 0;
628 info[6] = 0;
629 info[7] = 0;
630 info[14] = 0;
631 info[15] = 0;
632 } else {
633 struct nv50_miptree *mt = nv50_miptree(&res->base);
634 struct nv50_miptree_level *lvl = &mt->level[sf->base.u.tex.level];
635 const unsigned z = sf->base.u.tex.first_layer;
636
637 if (z) {
638 if (mt->layout_3d) {
639 address += nvc0_mt_zslice_offset(mt, psf->u.tex.level, z);
640 /* doesn't work if z passes z-tile boundary */
641 assert(sf->depth == 1);
642 } else {
643 address += mt->layer_stride * z;
644 }
645 }
646 info[0] = address >> 8;
647 info[2] = sf->width - 1;
648 /* NOTE: this is really important: */
649 info[2] |= (0xff & nve4_su_format_aux_map[sf->base.format]) << 22;
650 info[3] = (0x88 << 24) | (lvl->pitch / 64);
651 info[4] = sf->height - 1;
652 info[4] |= (lvl->tile_mode & 0x0f0) << 25;
653 info[4] |= NVC0_TILE_SHIFT_Y(lvl->tile_mode) << 22;
654 info[5] = mt->layer_stride >> 8;
655 info[6] = sf->depth - 1;
656 info[6] |= (lvl->tile_mode & 0xf00) << 21;
657 info[6] |= NVC0_TILE_SHIFT_Z(lvl->tile_mode) << 22;
658 info[7] = 0;
659 info[14] = mt->ms_x;
660 info[15] = mt->ms_y;
661 }
662 }
663
664 static inline void
665 nvc0_update_surface_bindings(struct nvc0_context *nvc0)
666 {
667 /* TODO */
668 }
669
670 static inline void
671 nve4_update_surface_bindings(struct nvc0_context *nvc0)
672 {
673 /* TODO */
674 }
675
676 void
677 nvc0_validate_surfaces(struct nvc0_context *nvc0)
678 {
679 if (nvc0->screen->base.class_3d >= NVE4_3D_CLASS) {
680 nve4_update_surface_bindings(nvc0);
681 } else {
682 nvc0_update_surface_bindings(nvc0);
683 }
684 }
685
686
687 static const uint8_t nve4_su_format_map[PIPE_FORMAT_COUNT] =
688 {
689 [PIPE_FORMAT_R32G32B32A32_FLOAT] = GK104_IMAGE_FORMAT_RGBA32_FLOAT,
690 [PIPE_FORMAT_R32G32B32A32_SINT] = GK104_IMAGE_FORMAT_RGBA32_SINT,
691 [PIPE_FORMAT_R32G32B32A32_UINT] = GK104_IMAGE_FORMAT_RGBA32_UINT,
692 [PIPE_FORMAT_R16G16B16A16_FLOAT] = GK104_IMAGE_FORMAT_RGBA16_FLOAT,
693 [PIPE_FORMAT_R16G16B16A16_UNORM] = GK104_IMAGE_FORMAT_RGBA16_UNORM,
694 [PIPE_FORMAT_R16G16B16A16_SNORM] = GK104_IMAGE_FORMAT_RGBA16_SNORM,
695 [PIPE_FORMAT_R16G16B16A16_SINT] = GK104_IMAGE_FORMAT_RGBA16_SINT,
696 [PIPE_FORMAT_R16G16B16A16_UINT] = GK104_IMAGE_FORMAT_RGBA16_UINT,
697 [PIPE_FORMAT_R8G8B8A8_UNORM] = GK104_IMAGE_FORMAT_RGBA8_UNORM,
698 [PIPE_FORMAT_R8G8B8A8_SNORM] = GK104_IMAGE_FORMAT_RGBA8_SNORM,
699 [PIPE_FORMAT_R8G8B8A8_SINT] = GK104_IMAGE_FORMAT_RGBA8_SINT,
700 [PIPE_FORMAT_R8G8B8A8_UINT] = GK104_IMAGE_FORMAT_RGBA8_UINT,
701 [PIPE_FORMAT_R11G11B10_FLOAT] = GK104_IMAGE_FORMAT_R11G11B10_FLOAT,
702 [PIPE_FORMAT_R10G10B10A2_UNORM] = GK104_IMAGE_FORMAT_RGB10_A2_UNORM,
703 /* [PIPE_FORMAT_R10G10B10A2_UINT] = GK104_IMAGE_FORMAT_RGB10_A2_UINT, */
704 [PIPE_FORMAT_R32G32_FLOAT] = GK104_IMAGE_FORMAT_RG32_FLOAT,
705 [PIPE_FORMAT_R32G32_SINT] = GK104_IMAGE_FORMAT_RG32_SINT,
706 [PIPE_FORMAT_R32G32_UINT] = GK104_IMAGE_FORMAT_RG32_UINT,
707 [PIPE_FORMAT_R16G16_FLOAT] = GK104_IMAGE_FORMAT_RG16_FLOAT,
708 [PIPE_FORMAT_R16G16_UNORM] = GK104_IMAGE_FORMAT_RG16_UNORM,
709 [PIPE_FORMAT_R16G16_SNORM] = GK104_IMAGE_FORMAT_RG16_SNORM,
710 [PIPE_FORMAT_R16G16_SINT] = GK104_IMAGE_FORMAT_RG16_SINT,
711 [PIPE_FORMAT_R16G16_UINT] = GK104_IMAGE_FORMAT_RG16_UINT,
712 [PIPE_FORMAT_R8G8_UNORM] = GK104_IMAGE_FORMAT_RG8_UNORM,
713 [PIPE_FORMAT_R8G8_SNORM] = GK104_IMAGE_FORMAT_RG8_SNORM,
714 [PIPE_FORMAT_R8G8_SINT] = GK104_IMAGE_FORMAT_RG8_SINT,
715 [PIPE_FORMAT_R8G8_UINT] = GK104_IMAGE_FORMAT_RG8_UINT,
716 [PIPE_FORMAT_R32_FLOAT] = GK104_IMAGE_FORMAT_R32_FLOAT,
717 [PIPE_FORMAT_R32_SINT] = GK104_IMAGE_FORMAT_R32_SINT,
718 [PIPE_FORMAT_R32_UINT] = GK104_IMAGE_FORMAT_R32_UINT,
719 [PIPE_FORMAT_R16_FLOAT] = GK104_IMAGE_FORMAT_R16_FLOAT,
720 [PIPE_FORMAT_R16_UNORM] = GK104_IMAGE_FORMAT_R16_UNORM,
721 [PIPE_FORMAT_R16_SNORM] = GK104_IMAGE_FORMAT_R16_SNORM,
722 [PIPE_FORMAT_R16_SINT] = GK104_IMAGE_FORMAT_R16_SINT,
723 [PIPE_FORMAT_R16_UINT] = GK104_IMAGE_FORMAT_R16_UINT,
724 [PIPE_FORMAT_R8_UNORM] = GK104_IMAGE_FORMAT_R8_UNORM,
725 [PIPE_FORMAT_R8_SNORM] = GK104_IMAGE_FORMAT_R8_SNORM,
726 [PIPE_FORMAT_R8_SINT] = GK104_IMAGE_FORMAT_R8_SINT,
727 [PIPE_FORMAT_R8_UINT] = GK104_IMAGE_FORMAT_R8_UINT,
728 };
729
730 /* Auxiliary format description values for surface instructions.
731 * (log2(bytes per pixel) << 12) | (unk8 << 8) | unk22
732 */
733 static const uint16_t nve4_su_format_aux_map[PIPE_FORMAT_COUNT] =
734 {
735 [PIPE_FORMAT_R32G32B32A32_FLOAT] = 0x4842,
736 [PIPE_FORMAT_R32G32B32A32_SINT] = 0x4842,
737 [PIPE_FORMAT_R32G32B32A32_UINT] = 0x4842,
738
739 [PIPE_FORMAT_R16G16B16A16_UNORM] = 0x3933,
740 [PIPE_FORMAT_R16G16B16A16_SNORM] = 0x3933,
741 [PIPE_FORMAT_R16G16B16A16_SINT] = 0x3933,
742 [PIPE_FORMAT_R16G16B16A16_UINT] = 0x3933,
743 [PIPE_FORMAT_R16G16B16A16_FLOAT] = 0x3933,
744
745 [PIPE_FORMAT_R32G32_FLOAT] = 0x3433,
746 [PIPE_FORMAT_R32G32_SINT] = 0x3433,
747 [PIPE_FORMAT_R32G32_UINT] = 0x3433,
748
749 [PIPE_FORMAT_R10G10B10A2_UNORM] = 0x2a24,
750 /* [PIPE_FORMAT_R10G10B10A2_UINT] = 0x2a24, */
751 [PIPE_FORMAT_R8G8B8A8_UNORM] = 0x2a24,
752 [PIPE_FORMAT_R8G8B8A8_SNORM] = 0x2a24,
753 [PIPE_FORMAT_R8G8B8A8_SINT] = 0x2a24,
754 [PIPE_FORMAT_R8G8B8A8_UINT] = 0x2a24,
755 [PIPE_FORMAT_R11G11B10_FLOAT] = 0x2a24,
756
757 [PIPE_FORMAT_R16G16_UNORM] = 0x2524,
758 [PIPE_FORMAT_R16G16_SNORM] = 0x2524,
759 [PIPE_FORMAT_R16G16_SINT] = 0x2524,
760 [PIPE_FORMAT_R16G16_UINT] = 0x2524,
761 [PIPE_FORMAT_R16G16_FLOAT] = 0x2524,
762
763 [PIPE_FORMAT_R32_SINT] = 0x2024,
764 [PIPE_FORMAT_R32_UINT] = 0x2024,
765 [PIPE_FORMAT_R32_FLOAT] = 0x2024,
766
767 [PIPE_FORMAT_R8G8_UNORM] = 0x1615,
768 [PIPE_FORMAT_R8G8_SNORM] = 0x1615,
769 [PIPE_FORMAT_R8G8_SINT] = 0x1615,
770 [PIPE_FORMAT_R8G8_UINT] = 0x1615,
771
772 [PIPE_FORMAT_R16_UNORM] = 0x1115,
773 [PIPE_FORMAT_R16_SNORM] = 0x1115,
774 [PIPE_FORMAT_R16_SINT] = 0x1115,
775 [PIPE_FORMAT_R16_UINT] = 0x1115,
776 [PIPE_FORMAT_R16_FLOAT] = 0x1115,
777
778 [PIPE_FORMAT_R8_UNORM] = 0x0206,
779 [PIPE_FORMAT_R8_SNORM] = 0x0206,
780 [PIPE_FORMAT_R8_SINT] = 0x0206,
781 [PIPE_FORMAT_R8_UINT] = 0x0206
782 };
783
784 /* NOTE: These are hardcoded offsets for the shader library.
785 * TODO: Automate them.
786 */
787 static const uint16_t nve4_suldp_lib_offset[PIPE_FORMAT_COUNT] =
788 {
789 [PIPE_FORMAT_R32G32B32A32_FLOAT] = 0x218,
790 [PIPE_FORMAT_R32G32B32A32_SINT] = 0x218,
791 [PIPE_FORMAT_R32G32B32A32_UINT] = 0x218,
792 [PIPE_FORMAT_R16G16B16A16_UNORM] = 0x248,
793 [PIPE_FORMAT_R16G16B16A16_SNORM] = 0x2b8,
794 [PIPE_FORMAT_R16G16B16A16_SINT] = 0x330,
795 [PIPE_FORMAT_R16G16B16A16_UINT] = 0x388,
796 [PIPE_FORMAT_R16G16B16A16_FLOAT] = 0x3d8,
797 [PIPE_FORMAT_R32G32_FLOAT] = 0x428,
798 [PIPE_FORMAT_R32G32_SINT] = 0x468,
799 [PIPE_FORMAT_R32G32_UINT] = 0x468,
800 [PIPE_FORMAT_R10G10B10A2_UNORM] = 0x4a8,
801 /* [PIPE_FORMAT_R10G10B10A2_UINT] = 0x530, */
802 [PIPE_FORMAT_R8G8B8A8_UNORM] = 0x588,
803 [PIPE_FORMAT_R8G8B8A8_SNORM] = 0x5f8,
804 [PIPE_FORMAT_R8G8B8A8_SINT] = 0x670,
805 [PIPE_FORMAT_R8G8B8A8_UINT] = 0x6c8,
806 [PIPE_FORMAT_B5G6R5_UNORM] = 0x718,
807 [PIPE_FORMAT_B5G5R5X1_UNORM] = 0x7a0,
808 [PIPE_FORMAT_R16G16_UNORM] = 0x828,
809 [PIPE_FORMAT_R16G16_SNORM] = 0x890,
810 [PIPE_FORMAT_R16G16_SINT] = 0x8f0,
811 [PIPE_FORMAT_R16G16_UINT] = 0x948,
812 [PIPE_FORMAT_R16G16_FLOAT] = 0x998,
813 [PIPE_FORMAT_R32_FLOAT] = 0x9e8,
814 [PIPE_FORMAT_R32_SINT] = 0xa30,
815 [PIPE_FORMAT_R32_UINT] = 0xa30,
816 [PIPE_FORMAT_R8G8_UNORM] = 0xa78,
817 [PIPE_FORMAT_R8G8_SNORM] = 0xae0,
818 [PIPE_FORMAT_R8G8_UINT] = 0xb48,
819 [PIPE_FORMAT_R8G8_SINT] = 0xb98,
820 [PIPE_FORMAT_R16_UNORM] = 0xbe8,
821 [PIPE_FORMAT_R16_SNORM] = 0xc48,
822 [PIPE_FORMAT_R16_SINT] = 0xca0,
823 [PIPE_FORMAT_R16_UINT] = 0xce8,
824 [PIPE_FORMAT_R16_FLOAT] = 0xd30,
825 [PIPE_FORMAT_R8_UNORM] = 0xd88,
826 [PIPE_FORMAT_R8_SNORM] = 0xde0,
827 [PIPE_FORMAT_R8_SINT] = 0xe38,
828 [PIPE_FORMAT_R8_UINT] = 0xe88,
829 [PIPE_FORMAT_R11G11B10_FLOAT] = 0xed0
830 };