src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #define NVC0_PUSH_EXPLICIT_SPACE_CHECKING
  24
  25 #include "pipe/p_context.h"
  26 #include "pipe/p_state.h"
  27 #include "util/u_inlines.h"
  28 #include "util/u_format.h"
  29 #include "translate/translate.h"
  30
  31 #include "nvc0/nvc0_context.h"
  32 #include "nvc0/nvc0_query_hw.h"
  33 #include "nvc0/nvc0_resource.h"
  34
  35 #include "nvc0/nvc0_3d.xml.h"
  36
  37 void
  38 nvc0_vertex_state_delete(struct pipe_context *pipe,
  39                          void *hwcso)
  40 {
  41    struct nvc0_vertex_stateobj *so = hwcso;
  42
  43    if (so->translate)
  44       so->translate->release(so->translate);
  45    FREE(hwcso);
  46 }
  47
  48 void *
  49 nvc0_vertex_state_create(struct pipe_context *pipe,
  50                          unsigned num_elements,
  51                          const struct pipe_vertex_element *elements)
  52 {
  53     struct nvc0_vertex_stateobj *so;
  54     struct translate_key transkey;
  55     unsigned i;
  56     unsigned src_offset_max = 0;
  57
  58     so = MALLOC(sizeof(*so) +
  59                 num_elements * sizeof(struct nvc0_vertex_element));
  60     if (!so)
  61         return NULL;
  62     so->num_elements = num_elements;
  63     so->instance_elts = 0;
  64     so->instance_bufs = 0;
  65     so->shared_slots = false;
  66     so->need_conversion = false;
  67
  68     memset(so->vb_access_size, 0, sizeof(so->vb_access_size));
  69
  70     for (i = 0; i < PIPE_MAX_ATTRIBS; ++i)
  71        so->min_instance_div[i] = 0xffffffff;
  72
  73     transkey.nr_elements = 0;
  74     transkey.output_stride = 0;
  75
  76     for (i = 0; i < num_elements; ++i) {
  77         const struct pipe_vertex_element *ve = &elements[i];
  78         const unsigned vbi = ve->vertex_buffer_index;
  79         unsigned size;
  80         enum pipe_format fmt = ve->src_format;
  81
  82         so->element[i].pipe = elements[i];
  83         so->element[i].state = nvc0_format_table[fmt].vtx;
  84
  85         if (!so->element[i].state) {
  86             switch (util_format_get_nr_components(fmt)) {
  87             case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
  88             case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
  89             case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
  90             case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
  91             default:
  92                 assert(0);
  93                 FREE(so);
  94                 return NULL;
  95             }
  96             so->element[i].state = nvc0_format_table[fmt].vtx;
  97             so->need_conversion = true;
  98             pipe_debug_message(&nouveau_context(pipe)->debug, FALLBACK,
  99                                "Converting vertex element %d, no hw format %s",
 100                                i, util_format_name(ve->src_format));
 101         }
 102         size = util_format_get_blocksize(fmt);
 103
 104         src_offset_max = MAX2(src_offset_max, ve->src_offset);
 105
 106         if (so->vb_access_size[vbi] < (ve->src_offset + size))
 107            so->vb_access_size[vbi] = ve->src_offset + size;
 108
 109         if (unlikely(ve->instance_divisor)) {
 110            so->instance_elts |= 1 << i;
 111            so->instance_bufs |= 1 << vbi;
 112            if (ve->instance_divisor < so->min_instance_div[vbi])
 113               so->min_instance_div[vbi] = ve->instance_divisor;
 114         }
 115
 116         if (1) {
 117             unsigned ca;
 118             unsigned j = transkey.nr_elements++;
 119
 120             ca = util_format_description(fmt)->channel[0].size / 8;
 121             if (ca != 1 && ca != 2)
 122                ca = 4;
 123
 124             transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
 125             transkey.element[j].input_format = ve->src_format;
 126             transkey.element[j].input_buffer = vbi;
 127             transkey.element[j].input_offset = ve->src_offset;
 128             transkey.element[j].instance_divisor = ve->instance_divisor;
 129
 130             transkey.output_stride = align(transkey.output_stride, ca);
 131             transkey.element[j].output_format = fmt;
 132             transkey.element[j].output_offset = transkey.output_stride;
 133             transkey.output_stride += size;
 134
 135             so->element[i].state_alt = so->element[i].state;
 136             so->element[i].state_alt |= transkey.element[j].output_offset << 7;
 137         }
 138
 139         so->element[i].state |= i << NVC0_3D_VERTEX_ATTRIB_FORMAT_BUFFER__SHIFT;
 140     }
 141     transkey.output_stride = align(transkey.output_stride, 4);
 142
 143     so->size = transkey.output_stride;
 144     so->translate = translate_create(&transkey);
 145
 146     if (so->instance_elts || src_offset_max >= (1 << 14))
 147        return so;
 148     so->shared_slots = true;
 149
 150     for (i = 0; i < num_elements; ++i) {
 151        const unsigned b = elements[i].vertex_buffer_index;
 152        const unsigned s = elements[i].src_offset;
 153        so->element[i].state &= ~NVC0_3D_VERTEX_ATTRIB_FORMAT_BUFFER__MASK;
 154        so->element[i].state |= b << NVC0_3D_VERTEX_ATTRIB_FORMAT_BUFFER__SHIFT;
 155        so->element[i].state |= s << NVC0_3D_VERTEX_ATTRIB_FORMAT_OFFSET__SHIFT;
 156     }
 157     return so;
 158 }
 159
 160 #define NVC0_3D_VERTEX_ATTRIB_INACTIVE                                       \
 161    NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT |                                 \
 162    NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32 | NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST
 163
 164 #define VTX_ATTR(a, c, t, s)                            \
 165    ((NVC0_3D_VTX_ATTR_DEFINE_TYPE_##t) |                \
 166     (NVC0_3D_VTX_ATTR_DEFINE_SIZE_##s) |                \
 167     ((a) << NVC0_3D_VTX_ATTR_DEFINE_ATTR__SHIFT) |      \
 168     ((c) << NVC0_3D_VTX_ATTR_DEFINE_COMP__SHIFT))
 169
 170 static void
 171 nvc0_set_constant_vertex_attrib(struct nvc0_context *nvc0, const unsigned a)
 172 {
 173    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 174    struct pipe_vertex_element *ve = &nvc0->vertex->element[a].pipe;
 175    struct pipe_vertex_buffer *vb = &nvc0->vtxbuf[ve->vertex_buffer_index];
 176    uint32_t mode;
 177    const struct util_format_description *desc;
 178    void *dst;
 179    const void *src = (const uint8_t *)vb->user_buffer + ve->src_offset;
 180    assert(!vb->buffer);
 181
 182    desc = util_format_description(ve->src_format);
 183
 184    PUSH_SPACE(push, 6);
 185    BEGIN_NVC0(push, NVC0_3D(VTX_ATTR_DEFINE), 5);
 186    dst = &push->cur[1];
 187    if (desc->channel[0].pure_integer) {
 188       if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED) {
 189          mode = VTX_ATTR(a, 4, SINT, 32);
 190          desc->unpack_rgba_sint(dst, 0, src, 0, 1, 1);
 191       } else {
 192          mode = VTX_ATTR(a, 4, UINT, 32);
 193          desc->unpack_rgba_uint(dst, 0, src, 0, 1, 1);
 194       }
 195    } else {
 196       mode = VTX_ATTR(a, 4, FLOAT, 32);
 197       desc->unpack_rgba_float(dst, 0, src, 0, 1, 1);
 198    }
 199    push->cur[0] = mode;
 200    push->cur += 5;
 201 }
 202
 203 static inline void
 204 nvc0_user_vbuf_range(struct nvc0_context *nvc0, int vbi,
 205                      uint32_t *base, uint32_t *size)
 206 {
 207    if (unlikely(nvc0->vertex->instance_bufs & (1 << vbi))) {
 208       const uint32_t div = nvc0->vertex->min_instance_div[vbi];
 209       *base = nvc0->instance_off * nvc0->vtxbuf[vbi].stride;
 210       *size = (nvc0->instance_max / div) * nvc0->vtxbuf[vbi].stride +
 211          nvc0->vertex->vb_access_size[vbi];
 212    } else {
 213       /* NOTE: if there are user buffers, we *must* have index bounds */
 214       assert(nvc0->vb_elt_limit != ~0);
 215       *base = nvc0->vb_elt_first * nvc0->vtxbuf[vbi].stride;
 216       *size = nvc0->vb_elt_limit * nvc0->vtxbuf[vbi].stride +
 217          nvc0->vertex->vb_access_size[vbi];
 218    }
 219 }
 220
 221 static inline void
 222 nvc0_release_user_vbufs(struct nvc0_context *nvc0)
 223 {
 224    if (nvc0->vbo_user) {
 225       nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_VTX_TMP);
 226       nouveau_scratch_done(&nvc0->base);
 227    }
 228 }
 229
 230 static void
 231 nvc0_update_user_vbufs(struct nvc0_context *nvc0)
 232 {
 233    uint64_t address[PIPE_MAX_ATTRIBS];
 234    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 235    int i;
 236    uint32_t written = 0;
 237
 238    PUSH_SPACE(push, nvc0->vertex->num_elements * 8);
 239    for (i = 0; i < nvc0->vertex->num_elements; ++i) {
 240       struct pipe_vertex_element *ve = &nvc0->vertex->element[i].pipe;
 241       const unsigned b = ve->vertex_buffer_index;
 242       struct pipe_vertex_buffer *vb = &nvc0->vtxbuf[b];
 243       uint32_t base, size;
 244
 245       if (!(nvc0->vbo_user & (1 << b)))
 246          continue;
 247       if (nvc0->constant_vbos & (1 << b)) {
 248          nvc0_set_constant_vertex_attrib(nvc0, i);
 249          continue;
 250       }
 251       nvc0_user_vbuf_range(nvc0, b, &base, &size);
 252
 253       if (!(written & (1 << b))) {
 254          struct nouveau_bo *bo;
 255          const uint32_t bo_flags = NOUVEAU_BO_RD | NOUVEAU_BO_GART;
 256          written |= 1 << b;
 257          address[b] = nouveau_scratch_data(&nvc0->base, vb->user_buffer,
 258                                            base, size, &bo);
 259          if (bo)
 260             BCTX_REFN_bo(nvc0->bufctx_3d, VTX_TMP, bo_flags, bo);
 261
 262          NOUVEAU_DRV_STAT(&nvc0->screen->base, user_buffer_upload_bytes, size);
 263       }
 264
 265       BEGIN_1IC0(push, NVC0_3D(MACRO_VERTEX_ARRAY_SELECT), 5);
 266       PUSH_DATA (push, i);
 267       PUSH_DATAh(push, address[b] + base + size - 1);
 268       PUSH_DATA (push, address[b] + base + size - 1);
 269       PUSH_DATAh(push, address[b] + ve->src_offset);
 270       PUSH_DATA (push, address[b] + ve->src_offset);
 271    }
 272    nvc0->base.vbo_dirty = true;
 273 }
 274
 275 static void
 276 nvc0_update_user_vbufs_shared(struct nvc0_context *nvc0)
 277 {
 278    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 279    uint32_t mask = nvc0->vbo_user & ~nvc0->constant_vbos;
 280
 281    PUSH_SPACE(push, nvc0->num_vtxbufs * 8);
 282    while (mask) {
 283       struct nouveau_bo *bo;
 284       const uint32_t bo_flags = NOUVEAU_BO_RD | NOUVEAU_BO_GART;
 285       uint64_t address;
 286       uint32_t base, size;
 287       const int b = ffs(mask) - 1;
 288       mask &= ~(1 << b);
 289
 290       nvc0_user_vbuf_range(nvc0, b, &base, &size);
 291
 292       address = nouveau_scratch_data(&nvc0->base, nvc0->vtxbuf[b].user_buffer,
 293                                      base, size, &bo);
 294       if (bo)
 295          BCTX_REFN_bo(nvc0->bufctx_3d, VTX_TMP, bo_flags, bo);
 296
 297       BEGIN_1IC0(push, NVC0_3D(MACRO_VERTEX_ARRAY_SELECT), 5);
 298       PUSH_DATA (push, b);
 299       PUSH_DATAh(push, address + base + size - 1);
 300       PUSH_DATA (push, address + base + size - 1);
 301       PUSH_DATAh(push, address);
 302       PUSH_DATA (push, address);
 303
 304       NOUVEAU_DRV_STAT(&nvc0->screen->base, user_buffer_upload_bytes, size);
 305    }
 306
 307    mask = nvc0->state.constant_elts;
 308    while (mask) {
 309       int i = ffs(mask) - 1;
 310       mask &= ~(1 << i);
 311       nvc0_set_constant_vertex_attrib(nvc0, i);
 312    }
 313 }
 314
 315 static void
 316 nvc0_validate_vertex_buffers(struct nvc0_context *nvc0)
 317 {
 318    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 319    const struct nvc0_vertex_stateobj *vertex = nvc0->vertex;
 320    uint32_t refd = 0;
 321    unsigned i;
 322
 323    PUSH_SPACE(push, vertex->num_elements * 8);
 324    for (i = 0; i < vertex->num_elements; ++i) {
 325       const struct nvc0_vertex_element *ve;
 326       const struct pipe_vertex_buffer *vb;
 327       struct nv04_resource *res;
 328       unsigned b;
 329       unsigned limit, offset;
 330
 331       if (nvc0->state.constant_elts & (1 << i))
 332          continue;
 333       ve = &vertex->element[i];
 334       b = ve->pipe.vertex_buffer_index;
 335       vb = &nvc0->vtxbuf[b];
 336
 337       if (nvc0->vbo_user & (1 << b)) {
 338          if (!(nvc0->constant_vbos & (1 << b))) {
 339             if (ve->pipe.instance_divisor) {
 340                BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_DIVISOR(i)), 1);
 341                PUSH_DATA (push, ve->pipe.instance_divisor);
 342             }
 343             BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 1);
 344             PUSH_DATA (push, (1 << 12) | vb->stride);
 345          }
 346          /* address/value set in nvc0_update_user_vbufs */
 347          continue;
 348       }
 349       res = nv04_resource(vb->buffer);
 350       offset = ve->pipe.src_offset + vb->buffer_offset;
 351       limit = vb->buffer->width0 - 1;
 352
 353       if (unlikely(ve->pipe.instance_divisor)) {
 354          BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 4);
 355          PUSH_DATA (push, NVC0_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
 356          PUSH_DATAh(push, res->address + offset);
 357          PUSH_DATA (push, res->address + offset);
 358          PUSH_DATA (push, ve->pipe.instance_divisor);
 359       } else {
 360          BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 3);
 361          PUSH_DATA (push, NVC0_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
 362          PUSH_DATAh(push, res->address + offset);
 363          PUSH_DATA (push, res->address + offset);
 364       }
 365       BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
 366       PUSH_DATAh(push, res->address + limit);
 367       PUSH_DATA (push, res->address + limit);
 368
 369       if (!(refd & (1 << b))) {
 370          refd |= 1 << b;
 371          BCTX_REFN(nvc0->bufctx_3d, VTX, res, RD);
 372       }
 373    }
 374    if (nvc0->vbo_user)
 375       nvc0_update_user_vbufs(nvc0);
 376 }
 377
 378 static void
 379 nvc0_validate_vertex_buffers_shared(struct nvc0_context *nvc0)
 380 {
 381    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 382    unsigned b;
 383    const uint32_t mask = nvc0->vbo_user;
 384
 385    PUSH_SPACE(push, nvc0->num_vtxbufs * 8 + nvc0->vertex->num_elements);
 386    for (b = 0; b < nvc0->num_vtxbufs; ++b) {
 387       struct pipe_vertex_buffer *vb = &nvc0->vtxbuf[b];
 388       struct nv04_resource *buf;
 389       uint32_t offset, limit;
 390
 391       if (mask & (1 << b)) {
 392          if (!(nvc0->constant_vbos & (1 << b))) {
 393             BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(b)), 1);
 394             PUSH_DATA (push, NVC0_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
 395          }
 396          /* address/value set in nvc0_update_user_vbufs_shared */
 397          continue;
 398       } else if (!vb->buffer) {
 399          /* there can be holes in the vertex buffer lists */
 400          IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(b)), 0);
 401          continue;
 402       }
 403       buf = nv04_resource(vb->buffer);
 404       offset = vb->buffer_offset;
 405       limit = buf->base.width0 - 1;
 406
 407       BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(b)), 3);
 408       PUSH_DATA (push, NVC0_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
 409       PUSH_DATAh(push, buf->address + offset);
 410       PUSH_DATA (push, buf->address + offset);
 411       BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_LIMIT_HIGH(b)), 2);
 412       PUSH_DATAh(push, buf->address + limit);
 413       PUSH_DATA (push, buf->address + limit);
 414
 415       BCTX_REFN(nvc0->bufctx_3d, VTX, buf, RD);
 416    }
 417    /* If there are more elements than buffers, we might not have unset
 418     * fetching on the later elements.
 419     */
 420    for (; b < nvc0->vertex->num_elements; ++b)
 421       IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(b)), 0);
 422
 423    if (nvc0->vbo_user)
 424       nvc0_update_user_vbufs_shared(nvc0);
 425 }
 426
 427 void
 428 nvc0_vertex_arrays_validate(struct nvc0_context *nvc0)
 429 {
 430    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 431    struct nvc0_vertex_stateobj *vertex = nvc0->vertex;
 432    struct nvc0_vertex_element *ve;
 433    uint32_t const_vbos;
 434    unsigned i;
 435    uint8_t vbo_mode;
 436    bool update_vertex;
 437
 438    nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_VTX);
 439
 440    assert(vertex);
 441    if (unlikely(vertex->need_conversion) ||
 442        unlikely(nvc0->vertprog->vp.edgeflag < PIPE_MAX_ATTRIBS)) {
 443       vbo_mode = 3;
 444    } else {
 445       vbo_mode = (nvc0->vbo_user && nvc0->vbo_push_hint) ? 1 : 0;
 446    }
 447    const_vbos = vbo_mode ? 0 : nvc0->constant_vbos;
 448
 449    update_vertex = (nvc0->dirty & NVC0_NEW_VERTEX) ||
 450       (const_vbos != nvc0->state.constant_vbos) ||
 451       (vbo_mode != nvc0->state.vbo_mode);
 452
 453    if (update_vertex) {
 454       const unsigned n = MAX2(vertex->num_elements, nvc0->state.num_vtxelts);
 455
 456       nvc0->state.constant_vbos = const_vbos;
 457       nvc0->state.constant_elts = 0;
 458       nvc0->state.num_vtxelts = vertex->num_elements;
 459       nvc0->state.vbo_mode = vbo_mode;
 460
 461       if (unlikely(vbo_mode)) {
 462          if (unlikely(nvc0->state.instance_elts & 3)) {
 463             /* translate mode uses only 2 vertex buffers */
 464             nvc0->state.instance_elts &= ~3;
 465             PUSH_SPACE(push, 3);
 466             BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_PER_INSTANCE(0)), 2);
 467             PUSH_DATA (push, 0);
 468             PUSH_DATA (push, 0);
 469          }
 470
 471          PUSH_SPACE(push, n * 2 + 4);
 472
 473          BEGIN_NVC0(push, NVC0_3D(VERTEX_ATTRIB_FORMAT(0)), n);
 474          for (i = 0; i < vertex->num_elements; ++i)
 475             PUSH_DATA(push, vertex->element[i].state_alt);
 476          for (; i < n; ++i)
 477             PUSH_DATA(push, NVC0_3D_VERTEX_ATTRIB_INACTIVE);
 478
 479          BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(0)), 1);
 480          PUSH_DATA (push, (1 << 12) | vertex->size);
 481          for (i = 1; i < n; ++i)
 482             IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 0);
 483       } else {
 484          uint32_t *restrict data;
 485
 486          if (unlikely(vertex->instance_elts != nvc0->state.instance_elts)) {
 487             nvc0->state.instance_elts = vertex->instance_elts;
 488             assert(n); /* if (n == 0), both masks should be 0 */
 489             PUSH_SPACE(push, 3);
 490             BEGIN_NVC0(push, NVC0_3D(MACRO_VERTEX_ARRAY_PER_INSTANCE), 2);
 491             PUSH_DATA (push, n);
 492             PUSH_DATA (push, vertex->instance_elts);
 493          }
 494
 495          PUSH_SPACE(push, n * 2 + 1);
 496          BEGIN_NVC0(push, NVC0_3D(VERTEX_ATTRIB_FORMAT(0)), n);
 497          data = push->cur;
 498          push->cur += n;
 499          for (i = 0; i < vertex->num_elements; ++i) {
 500             ve = &vertex->element[i];
 501             data[i] = ve->state;
 502             if (unlikely(const_vbos & (1 << ve->pipe.vertex_buffer_index))) {
 503                nvc0->state.constant_elts |= 1 << i;
 504                data[i] |= NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST;
 505                IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 0);
 506             }
 507          }
 508          for (; i < n; ++i) {
 509             data[i] = NVC0_3D_VERTEX_ATTRIB_INACTIVE;
 510             IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 0);
 511          }
 512       }
 513    }
 514    if (nvc0->state.vbo_mode) /* using translate, don't set up arrays here */
 515       return;
 516
 517    if (vertex->shared_slots)
 518       nvc0_validate_vertex_buffers_shared(nvc0);
 519    else
 520       nvc0_validate_vertex_buffers(nvc0);
 521 }
 522
 523 void
 524 nvc0_idxbuf_validate(struct nvc0_context *nvc0)
 525 {
 526    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 527    struct nv04_resource *buf = nv04_resource(nvc0->idxbuf.buffer);
 528
 529    assert(buf);
 530    assert(nouveau_resource_mapped_by_gpu(&buf->base));
 531
 532    PUSH_SPACE(push, 6);
 533    BEGIN_NVC0(push, NVC0_3D(INDEX_ARRAY_START_HIGH), 5);
 534    PUSH_DATAh(push, buf->address + nvc0->idxbuf.offset);
 535    PUSH_DATA (push, buf->address + nvc0->idxbuf.offset);
 536    PUSH_DATAh(push, buf->address + buf->base.width0 - 1);
 537    PUSH_DATA (push, buf->address + buf->base.width0 - 1);
 538    PUSH_DATA (push, nvc0->idxbuf.index_size >> 1);
 539
 540    BCTX_REFN(nvc0->bufctx_3d, IDX, buf, RD);
 541 }
 542
 543 #define NVC0_PRIM_GL_CASE(n) \
 544    case PIPE_PRIM_##n: return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
 545
 546 static inline unsigned
 547 nvc0_prim_gl(unsigned prim)
 548 {
 549    switch (prim) {
 550    NVC0_PRIM_GL_CASE(POINTS);
 551    NVC0_PRIM_GL_CASE(LINES);
 552    NVC0_PRIM_GL_CASE(LINE_LOOP);
 553    NVC0_PRIM_GL_CASE(LINE_STRIP);
 554    NVC0_PRIM_GL_CASE(TRIANGLES);
 555    NVC0_PRIM_GL_CASE(TRIANGLE_STRIP);
 556    NVC0_PRIM_GL_CASE(TRIANGLE_FAN);
 557    NVC0_PRIM_GL_CASE(QUADS);
 558    NVC0_PRIM_GL_CASE(QUAD_STRIP);
 559    NVC0_PRIM_GL_CASE(POLYGON);
 560    NVC0_PRIM_GL_CASE(LINES_ADJACENCY);
 561    NVC0_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
 562    NVC0_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
 563    NVC0_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
 564    NVC0_PRIM_GL_CASE(PATCHES);
 565    default:
 566       return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
 567    }
 568 }
 569
 570 static void
 571 nvc0_draw_vbo_kick_notify(struct nouveau_pushbuf *push)
 572 {
 573    struct nvc0_screen *screen = push->user_priv;
 574
 575    nouveau_fence_update(&screen->base, true);
 576
 577    NOUVEAU_DRV_STAT(&screen->base, pushbuf_count, 1);
 578 }
 579
 580 static void
 581 nvc0_draw_arrays(struct nvc0_context *nvc0,
 582                  unsigned mode, unsigned start, unsigned count,
 583                  unsigned instance_count)
 584 {
 585    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 586    unsigned prim;
 587
 588    if (nvc0->state.index_bias) {
 589       /* index_bias is implied 0 if !info->indexed (really ?) */
 590       /* TODO: can we deactivate it for the VERTEX_BUFFER_FIRST command ? */
 591       PUSH_SPACE(push, 2);
 592       IMMED_NVC0(push, NVC0_3D(VB_ELEMENT_BASE), 0);
 593       IMMED_NVC0(push, NVC0_3D(VERTEX_ID_BASE), 0);
 594       nvc0->state.index_bias = 0;
 595    }
 596
 597    prim = nvc0_prim_gl(mode);
 598
 599    while (instance_count--) {
 600       PUSH_SPACE(push, 6);
 601       BEGIN_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), 1);
 602       PUSH_DATA (push, prim);
 603       BEGIN_NVC0(push, NVC0_3D(VERTEX_BUFFER_FIRST), 2);
 604       PUSH_DATA (push, start);
 605       PUSH_DATA (push, count);
 606       IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
 607
 608       prim |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 609    }
 610    NOUVEAU_DRV_STAT(&nvc0->screen->base, draw_calls_array, 1);
 611 }
 612
 613 static void
 614 nvc0_draw_elements_inline_u08(struct nouveau_pushbuf *push, const uint8_t *map,
 615                               unsigned start, unsigned count)
 616 {
 617    map += start;
 618
 619    if (count & 3) {
 620       unsigned i;
 621       PUSH_SPACE(push, 4);
 622       BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U32), count & 3);
 623       for (i = 0; i < (count & 3); ++i)
 624          PUSH_DATA(push, *map++);
 625       count &= ~3;
 626    }
 627    while (count) {
 628       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4;
 629
 630       PUSH_SPACE(push, nr + 1);
 631       BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U8), nr);
 632       for (i = 0; i < nr; ++i) {
 633          PUSH_DATA(push,
 634                   (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]);
 635          map += 4;
 636       }
 637       count -= nr * 4;
 638    }
 639 }
 640
 641 static void
 642 nvc0_draw_elements_inline_u16(struct nouveau_pushbuf *push, const uint16_t *map,
 643                               unsigned start, unsigned count)
 644 {
 645    map += start;
 646
 647    if (count & 1) {
 648       count &= ~1;
 649       PUSH_SPACE(push, 2);
 650       BEGIN_NVC0(push, NVC0_3D(VB_ELEMENT_U32), 1);
 651       PUSH_DATA (push, *map++);
 652    }
 653    while (count) {
 654       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
 655
 656       PUSH_SPACE(push, nr + 1);
 657       BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U16), nr);
 658       for (i = 0; i < nr; ++i) {
 659          PUSH_DATA(push, (map[1] << 16) | map[0]);
 660          map += 2;
 661       }
 662       count -= nr * 2;
 663    }
 664 }
 665
 666 static void
 667 nvc0_draw_elements_inline_u32(struct nouveau_pushbuf *push, const uint32_t *map,
 668                               unsigned start, unsigned count)
 669 {
 670    map += start;
 671
 672    while (count) {
 673       const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
 674
 675       PUSH_SPACE(push, nr + 1);
 676       BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U32), nr);
 677       PUSH_DATAp(push, map, nr);
 678
 679       map += nr;
 680       count -= nr;
 681    }
 682 }
 683
 684 static void
 685 nvc0_draw_elements_inline_u32_short(struct nouveau_pushbuf *push,
 686                                     const uint32_t *map,
 687                                     unsigned start, unsigned count)
 688 {
 689    map += start;
 690
 691    if (count & 1) {
 692       count--;
 693       PUSH_SPACE(push, 2);
 694       BEGIN_NVC0(push, NVC0_3D(VB_ELEMENT_U32), 1);
 695       PUSH_DATA (push, *map++);
 696    }
 697    while (count) {
 698       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
 699
 700       PUSH_SPACE(push, nr + 1);
 701       BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U16), nr);
 702       for (i = 0; i < nr; ++i) {
 703          PUSH_DATA(push, (map[1] << 16) | map[0]);
 704          map += 2;
 705       }
 706       count -= nr * 2;
 707    }
 708 }
 709
 710 static void
 711 nvc0_draw_elements(struct nvc0_context *nvc0, bool shorten,
 712                    unsigned mode, unsigned start, unsigned count,
 713                    unsigned instance_count, int32_t index_bias)
 714 {
 715    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 716    unsigned prim;
 717    const unsigned index_size = nvc0->idxbuf.index_size;
 718
 719    prim = nvc0_prim_gl(mode);
 720
 721    if (index_bias != nvc0->state.index_bias) {
 722       PUSH_SPACE(push, 4);
 723       BEGIN_NVC0(push, NVC0_3D(VB_ELEMENT_BASE), 1);
 724       PUSH_DATA (push, index_bias);
 725       BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_BASE), 1);
 726       PUSH_DATA (push, index_bias);
 727       nvc0->state.index_bias = index_bias;
 728    }
 729
 730    if (nvc0->idxbuf.buffer) {
 731       PUSH_SPACE(push, 1);
 732       IMMED_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), prim);
 733       do {
 734          PUSH_SPACE(push, 7);
 735          BEGIN_NVC0(push, NVC0_3D(INDEX_BATCH_FIRST), 2);
 736          PUSH_DATA (push, start);
 737          PUSH_DATA (push, count);
 738          if (--instance_count) {
 739             BEGIN_NVC0(push, NVC0_3D(VERTEX_END_GL), 2);
 740             PUSH_DATA (push, 0);
 741             PUSH_DATA (push, prim | NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT);
 742          }
 743       } while (instance_count);
 744       IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
 745    } else {
 746       const void *data = nvc0->idxbuf.user_buffer;
 747
 748       while (instance_count--) {
 749          PUSH_SPACE(push, 2);
 750          BEGIN_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), 1);
 751          PUSH_DATA (push, prim);
 752          switch (index_size) {
 753          case 1:
 754             nvc0_draw_elements_inline_u08(push, data, start, count);
 755             break;
 756          case 2:
 757             nvc0_draw_elements_inline_u16(push, data, start, count);
 758             break;
 759          case 4:
 760             if (shorten)
 761                nvc0_draw_elements_inline_u32_short(push, data, start, count);
 762             else
 763                nvc0_draw_elements_inline_u32(push, data, start, count);
 764             break;
 765          default:
 766             assert(0);
 767             return;
 768          }
 769          PUSH_SPACE(push, 1);
 770          IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
 771
 772          prim |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 773       }
 774    }
 775    NOUVEAU_DRV_STAT(&nvc0->screen->base, draw_calls_indexed, 1);
 776 }
 777
 778 static void
 779 nvc0_draw_stream_output(struct nvc0_context *nvc0,
 780                         const struct pipe_draw_info *info)
 781 {
 782    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 783    struct nvc0_so_target *so = nvc0_so_target(info->count_from_stream_output);
 784    struct nv04_resource *res = nv04_resource(so->pipe.buffer);
 785    unsigned mode = nvc0_prim_gl(info->mode);
 786    unsigned num_instances = info->instance_count;
 787
 788    if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
 789       res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
 790       PUSH_SPACE(push, 2);
 791       IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
 792       nvc0_hw_query_fifo_wait(nvc0, nvc0_query(so->pq));
 793       if (nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
 794          IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FLUSH), 0);
 795
 796       NOUVEAU_DRV_STAT(&nvc0->screen->base, gpu_serialize_count, 1);
 797    }
 798
 799    while (num_instances--) {
 800       nouveau_pushbuf_space(push, 9, 0, 1);
 801       BEGIN_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), 1);
 802       PUSH_DATA (push, mode);
 803       BEGIN_NVC0(push, NVC0_3D(DRAW_TFB_BASE), 1);
 804       PUSH_DATA (push, 0);
 805       BEGIN_NVC0(push, NVC0_3D(DRAW_TFB_STRIDE), 1);
 806       PUSH_DATA (push, so->stride);
 807       BEGIN_NVC0(push, NVC0_3D(DRAW_TFB_BYTES), 1);
 808       nvc0_hw_query_pushbuf_submit(push, nvc0_query(so->pq), 0x4);
 809       IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
 810
 811       mode |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 812    }
 813 }
 814
 815 static void
 816 nvc0_draw_indirect(struct nvc0_context *nvc0, const struct pipe_draw_info *info)
 817 {
 818    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 819    struct nv04_resource *buf = nv04_resource(info->indirect);
 820    struct nv04_resource *buf_count = nv04_resource(info->indirect_params);
 821    unsigned size, macro, count = info->indirect_count, drawid = info->drawid;
 822    uint32_t offset = buf->offset + info->indirect_offset;
 823
 824    PUSH_SPACE(push, 7);
 825
 826    /* must make FIFO wait for engines idle before continuing to process */
 827    if ((buf->fence_wr && !nouveau_fence_signalled(buf->fence_wr)) ||
 828        (buf_count && buf_count->fence_wr &&
 829         !nouveau_fence_signalled(buf_count->fence_wr))) {
 830       IMMED_NVC0(push, SUBC_3D(NV10_SUBCHAN_REF_CNT), 0);
 831    }
 832
 833    /* Queue things up to let the macros write params to the driver constbuf */
 834    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 835    PUSH_DATA (push, 512);
 836    PUSH_DATAh(push, nvc0->screen->uniform_bo->offset + (5 << 16) + (0 << 9));
 837    PUSH_DATA (push, nvc0->screen->uniform_bo->offset + (5 << 16) + (0 << 9));
 838
 839    if (info->indexed) {
 840       assert(nvc0->idxbuf.buffer);
 841       assert(nouveau_resource_mapped_by_gpu(nvc0->idxbuf.buffer));
 842       size = 5;
 843       if (buf_count)
 844          macro = NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT;
 845       else
 846          macro = NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT;
 847    } else {
 848       if (nvc0->state.index_bias) {
 849          /* index_bias is implied 0 if !info->indexed (really ?) */
 850          IMMED_NVC0(push, NVC0_3D(VB_ELEMENT_BASE), 0);
 851          IMMED_NVC0(push, NVC0_3D(VERTEX_ID_BASE), 0);
 852          nvc0->state.index_bias = 0;
 853       }
 854       size = 4;
 855       if (buf_count)
 856          macro = NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT;
 857       else
 858          macro = NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT;
 859    }
 860
 861    /* If the stride is not the natural stride, we have to stick a separate
 862     * push data reference for each draw. Otherwise it can all go in as one.
 863     * Of course there is a maximum packet size, so we have to break things up
 864     * along those borders as well.
 865     */
 866    while (count) {
 867       unsigned draws = count, pushes, i;
 868       if (info->indirect_stride == size * 4) {
 869          draws = MIN2(draws, (NV04_PFIFO_MAX_PACKET_LEN - 4) / size);
 870          pushes = 1;
 871       } else {
 872          draws = MIN2(draws, 32);
 873          pushes = draws;
 874       }
 875
 876       nouveau_pushbuf_space(push, 16, 0, pushes + !!buf_count);
 877       PUSH_REFN(push, buf->bo, NOUVEAU_BO_RD | buf->domain);
 878       if (buf_count)
 879          PUSH_REFN(push, buf_count->bo, NOUVEAU_BO_RD | buf_count->domain);
 880       PUSH_DATA(push,
 881                 NVC0_FIFO_PKHDR_1I(0, macro, 3 + !!buf_count + draws * size));
 882       PUSH_DATA(push, nvc0_prim_gl(info->mode));
 883       PUSH_DATA(push, drawid);
 884       PUSH_DATA(push, draws);
 885       if (buf_count) {
 886          nouveau_pushbuf_data(push,
 887                               buf_count->bo,
 888                               buf_count->offset + info->indirect_params_offset,
 889                               NVC0_IB_ENTRY_1_NO_PREFETCH | 4);
 890       }
 891       if (pushes == 1) {
 892          nouveau_pushbuf_data(push,
 893                               buf->bo, offset,
 894                               NVC0_IB_ENTRY_1_NO_PREFETCH | (size * 4 * draws));
 895          offset += draws * info->indirect_stride;
 896       } else {
 897          for (i = 0; i < pushes; i++) {
 898             nouveau_pushbuf_data(push,
 899                                  buf->bo, offset,
 900                                  NVC0_IB_ENTRY_1_NO_PREFETCH | (size * 4));
 901             offset += info->indirect_stride;
 902          }
 903       }
 904       count -= draws;
 905       drawid += draws;
 906    }
 907 }
 908
 909 static inline void
 910 nvc0_update_prim_restart(struct nvc0_context *nvc0, bool en, uint32_t index)
 911 {
 912    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 913
 914    if (en != nvc0->state.prim_restart) {
 915       if (en) {
 916          BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_ENABLE), 2);
 917          PUSH_DATA (push, 1);
 918          PUSH_DATA (push, index);
 919       } else {
 920          IMMED_NVC0(push, NVC0_3D(PRIM_RESTART_ENABLE), 0);
 921       }
 922       nvc0->state.prim_restart = en;
 923    } else
 924    if (en) {
 925       BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_INDEX), 1);
 926       PUSH_DATA (push, index);
 927    }
 928 }
 929
 930 void
 931 nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 932 {
 933    struct nvc0_context *nvc0 = nvc0_context(pipe);
 934    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 935    int s;
 936
 937    /* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */
 938    nvc0->vb_elt_first = info->min_index + info->index_bias;
 939    nvc0->vb_elt_limit = info->max_index - info->min_index;
 940    nvc0->instance_off = info->start_instance;
 941    nvc0->instance_max = info->instance_count - 1;
 942
 943    /* For picking only a few vertices from a large user buffer, push is better,
 944     * if index count is larger and we expect repeated vertices, suggest upload.
 945     */
 946    nvc0->vbo_push_hint =
 947       info->indexed && (nvc0->vb_elt_limit >= (info->count * 2));
 948
 949    /* Check whether we want to switch vertex-submission mode. */
 950    if (nvc0->vbo_user && !(nvc0->dirty & (NVC0_NEW_ARRAYS | NVC0_NEW_VERTEX))) {
 951       if (nvc0->vbo_push_hint != !!nvc0->state.vbo_mode)
 952          if (nvc0->state.vbo_mode != 3)
 953             nvc0->dirty |= NVC0_NEW_ARRAYS;
 954
 955       if (!(nvc0->dirty & NVC0_NEW_ARRAYS) && nvc0->state.vbo_mode == 0) {
 956          if (nvc0->vertex->shared_slots)
 957             nvc0_update_user_vbufs_shared(nvc0);
 958          else
 959             nvc0_update_user_vbufs(nvc0);
 960       }
 961    }
 962
 963    if (info->mode == PIPE_PRIM_PATCHES &&
 964        nvc0->state.patch_vertices != info->vertices_per_patch) {
 965       nvc0->state.patch_vertices = info->vertices_per_patch;
 966       PUSH_SPACE(push, 1);
 967       IMMED_NVC0(push, NVC0_3D(PATCH_VERTICES), nvc0->state.patch_vertices);
 968    }
 969
 970    /* 8 as minimum to avoid immediate double validation of new buffers */
 971    nvc0_state_validate(nvc0, ~0, 8);
 972
 973    if (nvc0->vertprog->vp.need_draw_parameters) {
 974       PUSH_SPACE(push, 9);
 975       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 976       PUSH_DATA (push, 512);
 977       PUSH_DATAh(push, nvc0->screen->uniform_bo->offset + (5 << 16) + (0 << 9));
 978       PUSH_DATA (push, nvc0->screen->uniform_bo->offset + (5 << 16) + (0 << 9));
 979       if (!info->indirect) {
 980          BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 3);
 981          PUSH_DATA (push, 256 + 128);
 982          PUSH_DATA (push, info->index_bias);
 983          PUSH_DATA (push, info->start_instance);
 984          PUSH_DATA (push, info->drawid);
 985       }
 986    }
 987
 988    push->kick_notify = nvc0_draw_vbo_kick_notify;
 989
 990    for (s = 0; s < 5 && !nvc0->cb_dirty; ++s) {
 991       if (nvc0->constbuf_coherent[s])
 992          nvc0->cb_dirty = true;
 993    }
 994
 995    if (nvc0->cb_dirty) {
 996       PUSH_SPACE(push, 1);
 997       IMMED_NVC0(push, NVC0_3D(MEM_BARRIER), 0x1011);
 998       nvc0->cb_dirty = false;
 999    }
1000
1001    for (s = 0; s < 5; ++s) {
1002       if (!nvc0->textures_coherent[s])
1003          continue;
1004
1005       PUSH_SPACE(push, nvc0->num_textures[s] * 2);
1006
1007       for (int i = 0; i < nvc0->num_textures[s]; ++i) {
1008          struct nv50_tic_entry *tic = nv50_tic_entry(nvc0->textures[s][i]);
1009          if (!(nvc0->textures_coherent[s] & (1 << i)))
1010             continue;
1011
1012          BEGIN_NVC0(push, NVC0_3D(TEX_CACHE_CTL), 1);
1013          PUSH_DATA (push, (tic->id << 4) | 1);
1014          NOUVEAU_DRV_STAT(&nvc0->screen->base, tex_cache_flush_count, 1);
1015       }
1016    }
1017
1018    if (nvc0->state.vbo_mode) {
1019       nvc0_push_vbo(nvc0, info);
1020       push->kick_notify = nvc0_default_kick_notify;
1021       nouveau_pushbuf_bufctx(push, NULL);
1022       return;
1023    }
1024
1025    /* space for base instance, flush, and prim restart */
1026    PUSH_SPACE(push, 8);
1027
1028    if (nvc0->state.instance_base != info->start_instance) {
1029       nvc0->state.instance_base = info->start_instance;
1030       /* NOTE: this does not affect the shader input, should it ? */
1031       BEGIN_NVC0(push, NVC0_3D(VB_INSTANCE_BASE), 1);
1032       PUSH_DATA (push, info->start_instance);
1033    }
1034
1035    nvc0->base.vbo_dirty |= !!nvc0->vtxbufs_coherent;
1036
1037    if (!nvc0->base.vbo_dirty && nvc0->idxbuf.buffer &&
1038        nvc0->idxbuf.buffer->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
1039       nvc0->base.vbo_dirty = true;
1040
1041    nvc0_update_prim_restart(nvc0, info->primitive_restart, info->restart_index);
1042
1043    if (nvc0->base.vbo_dirty) {
1044       if (nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
1045          IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FLUSH), 0);
1046       nvc0->base.vbo_dirty = false;
1047    }
1048
1049    if (unlikely(info->indirect)) {
1050       nvc0_draw_indirect(nvc0, info);
1051    } else
1052    if (unlikely(info->count_from_stream_output)) {
1053       nvc0_draw_stream_output(nvc0, info);
1054    } else
1055    if (info->indexed) {
1056       bool shorten = info->max_index <= 65535;
1057
1058       if (info->primitive_restart && info->restart_index > 65535)
1059          shorten = false;
1060
1061       nvc0_draw_elements(nvc0, shorten,
1062                          info->mode, info->start, info->count,
1063                          info->instance_count, info->index_bias);
1064    } else {
1065       nvc0_draw_arrays(nvc0,
1066                        info->mode, info->start, info->count,
1067                        info->instance_count);
1068    }
1069    push->kick_notify = nvc0_default_kick_notify;
1070
1071    nvc0_release_user_vbufs(nvc0);
1072
1073    nouveau_pushbuf_bufctx(push, NULL);
1074 }