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nvc0: add support for texture gather
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_vbo.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #define NVC0_PUSH_EXPLICIT_SPACE_CHECKING
24
25 #include "pipe/p_context.h"
26 #include "pipe/p_state.h"
27 #include "util/u_inlines.h"
28 #include "util/u_format.h"
29 #include "translate/translate.h"
30
31 #include "nvc0/nvc0_context.h"
32 #include "nvc0/nvc0_resource.h"
33
34 #include "nvc0/nvc0_3d.xml.h"
35
36 void
37 nvc0_vertex_state_delete(struct pipe_context *pipe,
38 void *hwcso)
39 {
40 struct nvc0_vertex_stateobj *so = hwcso;
41
42 if (so->translate)
43 so->translate->release(so->translate);
44 FREE(hwcso);
45 }
46
47 void *
48 nvc0_vertex_state_create(struct pipe_context *pipe,
49 unsigned num_elements,
50 const struct pipe_vertex_element *elements)
51 {
52 struct nvc0_vertex_stateobj *so;
53 struct translate_key transkey;
54 unsigned i;
55 unsigned src_offset_max = 0;
56
57 so = MALLOC(sizeof(*so) +
58 num_elements * sizeof(struct nvc0_vertex_element));
59 if (!so)
60 return NULL;
61 so->num_elements = num_elements;
62 so->instance_elts = 0;
63 so->instance_bufs = 0;
64 so->shared_slots = FALSE;
65 so->need_conversion = FALSE;
66
67 memset(so->vb_access_size, 0, sizeof(so->vb_access_size));
68
69 for (i = 0; i < PIPE_MAX_ATTRIBS; ++i)
70 so->min_instance_div[i] = 0xffffffff;
71
72 transkey.nr_elements = 0;
73 transkey.output_stride = 0;
74
75 for (i = 0; i < num_elements; ++i) {
76 const struct pipe_vertex_element *ve = &elements[i];
77 const unsigned vbi = ve->vertex_buffer_index;
78 unsigned size;
79 enum pipe_format fmt = ve->src_format;
80
81 so->element[i].pipe = elements[i];
82 so->element[i].state = nvc0_format_table[fmt].vtx;
83
84 if (!so->element[i].state) {
85 switch (util_format_get_nr_components(fmt)) {
86 case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
87 case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
88 case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
89 case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
90 default:
91 assert(0);
92 FREE(so);
93 return NULL;
94 }
95 so->element[i].state = nvc0_format_table[fmt].vtx;
96 so->need_conversion = TRUE;
97 }
98 size = util_format_get_blocksize(fmt);
99
100 src_offset_max = MAX2(src_offset_max, ve->src_offset);
101
102 if (so->vb_access_size[vbi] < (ve->src_offset + size))
103 so->vb_access_size[vbi] = ve->src_offset + size;
104
105 if (unlikely(ve->instance_divisor)) {
106 so->instance_elts |= 1 << i;
107 so->instance_bufs |= 1 << vbi;
108 if (ve->instance_divisor < so->min_instance_div[vbi])
109 so->min_instance_div[vbi] = ve->instance_divisor;
110 }
111
112 if (1) {
113 unsigned ca;
114 unsigned j = transkey.nr_elements++;
115
116 ca = util_format_description(fmt)->channel[0].size / 8;
117 if (ca != 1 && ca != 2)
118 ca = 4;
119
120 transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
121 transkey.element[j].input_format = ve->src_format;
122 transkey.element[j].input_buffer = vbi;
123 transkey.element[j].input_offset = ve->src_offset;
124 transkey.element[j].instance_divisor = ve->instance_divisor;
125
126 transkey.output_stride = align(transkey.output_stride, ca);
127 transkey.element[j].output_format = fmt;
128 transkey.element[j].output_offset = transkey.output_stride;
129 transkey.output_stride += size;
130
131 so->element[i].state_alt = so->element[i].state;
132 so->element[i].state_alt |= transkey.element[j].output_offset << 7;
133 }
134
135 so->element[i].state |= i << NVC0_3D_VERTEX_ATTRIB_FORMAT_BUFFER__SHIFT;
136 }
137 transkey.output_stride = align(transkey.output_stride, 4);
138
139 so->size = transkey.output_stride;
140 so->translate = translate_create(&transkey);
141
142 if (so->instance_elts || src_offset_max >= (1 << 14))
143 return so;
144 so->shared_slots = TRUE;
145
146 for (i = 0; i < num_elements; ++i) {
147 const unsigned b = elements[i].vertex_buffer_index;
148 const unsigned s = elements[i].src_offset;
149 so->element[i].state &= ~NVC0_3D_VERTEX_ATTRIB_FORMAT_BUFFER__MASK;
150 so->element[i].state |= b << NVC0_3D_VERTEX_ATTRIB_FORMAT_BUFFER__SHIFT;
151 so->element[i].state |= s << NVC0_3D_VERTEX_ATTRIB_FORMAT_OFFSET__SHIFT;
152 }
153 return so;
154 }
155
156 #define NVC0_3D_VERTEX_ATTRIB_INACTIVE \
157 NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT | \
158 NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32 | NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST
159
160 #define VTX_ATTR(a, c, t, s) \
161 ((NVC0_3D_VTX_ATTR_DEFINE_TYPE_##t) | \
162 (NVC0_3D_VTX_ATTR_DEFINE_SIZE_##s) | \
163 ((a) << NVC0_3D_VTX_ATTR_DEFINE_ATTR__SHIFT) | \
164 ((c) << NVC0_3D_VTX_ATTR_DEFINE_COMP__SHIFT))
165
166 static void
167 nvc0_set_constant_vertex_attrib(struct nvc0_context *nvc0, const unsigned a)
168 {
169 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
170 struct pipe_vertex_element *ve = &nvc0->vertex->element[a].pipe;
171 struct pipe_vertex_buffer *vb = &nvc0->vtxbuf[ve->vertex_buffer_index];
172 uint32_t mode;
173 const struct util_format_description *desc;
174 void *dst;
175 const void *src = (const uint8_t *)vb->user_buffer + ve->src_offset;
176 assert(!vb->buffer);
177
178 desc = util_format_description(ve->src_format);
179
180 PUSH_SPACE(push, 6);
181 BEGIN_NVC0(push, NVC0_3D(VTX_ATTR_DEFINE), 5);
182 dst = &push->cur[1];
183 if (desc->channel[0].pure_integer) {
184 if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED) {
185 mode = VTX_ATTR(a, 4, SINT, 32);
186 desc->unpack_rgba_sint(dst, 0, src, 0, 1, 1);
187 } else {
188 mode = VTX_ATTR(a, 4, UINT, 32);
189 desc->unpack_rgba_uint(dst, 0, src, 0, 1, 1);
190 }
191 } else {
192 mode = VTX_ATTR(a, 4, FLOAT, 32);
193 desc->unpack_rgba_float(dst, 0, src, 0, 1, 1);
194 }
195 push->cur[0] = mode;
196 push->cur += 5;
197 }
198
199 static INLINE void
200 nvc0_user_vbuf_range(struct nvc0_context *nvc0, int vbi,
201 uint32_t *base, uint32_t *size)
202 {
203 if (unlikely(nvc0->vertex->instance_bufs & (1 << vbi))) {
204 const uint32_t div = nvc0->vertex->min_instance_div[vbi];
205 *base = nvc0->instance_off * nvc0->vtxbuf[vbi].stride;
206 *size = (nvc0->instance_max / div) * nvc0->vtxbuf[vbi].stride +
207 nvc0->vertex->vb_access_size[vbi];
208 } else {
209 /* NOTE: if there are user buffers, we *must* have index bounds */
210 assert(nvc0->vb_elt_limit != ~0);
211 *base = nvc0->vb_elt_first * nvc0->vtxbuf[vbi].stride;
212 *size = nvc0->vb_elt_limit * nvc0->vtxbuf[vbi].stride +
213 nvc0->vertex->vb_access_size[vbi];
214 }
215 }
216
217 static INLINE void
218 nvc0_release_user_vbufs(struct nvc0_context *nvc0)
219 {
220 if (nvc0->vbo_user) {
221 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_VTX_TMP);
222 nouveau_scratch_done(&nvc0->base);
223 }
224 }
225
226 static void
227 nvc0_update_user_vbufs(struct nvc0_context *nvc0)
228 {
229 uint64_t address[PIPE_MAX_ATTRIBS];
230 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
231 int i;
232 uint32_t written = 0;
233
234 PUSH_SPACE(push, nvc0->vertex->num_elements * 8);
235 for (i = 0; i < nvc0->vertex->num_elements; ++i) {
236 struct pipe_vertex_element *ve = &nvc0->vertex->element[i].pipe;
237 const unsigned b = ve->vertex_buffer_index;
238 struct pipe_vertex_buffer *vb = &nvc0->vtxbuf[b];
239 uint32_t base, size;
240
241 if (!(nvc0->vbo_user & (1 << b)))
242 continue;
243 if (!vb->stride) {
244 nvc0_set_constant_vertex_attrib(nvc0, i);
245 continue;
246 }
247 nvc0_user_vbuf_range(nvc0, b, &base, &size);
248
249 if (!(written & (1 << b))) {
250 struct nouveau_bo *bo;
251 const uint32_t bo_flags = NOUVEAU_BO_RD | NOUVEAU_BO_GART;
252 written |= 1 << b;
253 address[b] = nouveau_scratch_data(&nvc0->base, vb->user_buffer,
254 base, size, &bo);
255 if (bo)
256 BCTX_REFN_bo(nvc0->bufctx_3d, VTX_TMP, bo_flags, bo);
257
258 NOUVEAU_DRV_STAT(&nvc0->screen->base, user_buffer_upload_bytes, size);
259 }
260
261 BEGIN_1IC0(push, NVC0_3D(MACRO_VERTEX_ARRAY_SELECT), 5);
262 PUSH_DATA (push, i);
263 PUSH_DATAh(push, address[b] + base + size - 1);
264 PUSH_DATA (push, address[b] + base + size - 1);
265 PUSH_DATAh(push, address[b] + ve->src_offset);
266 PUSH_DATA (push, address[b] + ve->src_offset);
267 }
268 nvc0->base.vbo_dirty = TRUE;
269 }
270
271 static void
272 nvc0_update_user_vbufs_shared(struct nvc0_context *nvc0)
273 {
274 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
275 uint32_t mask = nvc0->vbo_user & ~nvc0->constant_vbos;
276
277 PUSH_SPACE(push, nvc0->num_vtxbufs * 8);
278 while (mask) {
279 struct nouveau_bo *bo;
280 const uint32_t bo_flags = NOUVEAU_BO_RD | NOUVEAU_BO_GART;
281 uint64_t address;
282 uint32_t base, size;
283 const int b = ffs(mask) - 1;
284 mask &= ~(1 << b);
285
286 nvc0_user_vbuf_range(nvc0, b, &base, &size);
287
288 address = nouveau_scratch_data(&nvc0->base, nvc0->vtxbuf[b].user_buffer,
289 base, size, &bo);
290 if (bo)
291 BCTX_REFN_bo(nvc0->bufctx_3d, VTX_TMP, bo_flags, bo);
292
293 BEGIN_1IC0(push, NVC0_3D(MACRO_VERTEX_ARRAY_SELECT), 5);
294 PUSH_DATA (push, b);
295 PUSH_DATAh(push, address + base + size - 1);
296 PUSH_DATA (push, address + base + size - 1);
297 PUSH_DATAh(push, address);
298 PUSH_DATA (push, address);
299
300 NOUVEAU_DRV_STAT(&nvc0->screen->base, user_buffer_upload_bytes, size);
301 }
302
303 mask = nvc0->state.constant_elts;
304 while (mask) {
305 int i = ffs(mask) - 1;
306 mask &= ~(1 << i);
307 nvc0_set_constant_vertex_attrib(nvc0, i);
308 }
309 }
310
311 static void
312 nvc0_validate_vertex_buffers(struct nvc0_context *nvc0)
313 {
314 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
315 const struct nvc0_vertex_stateobj *vertex = nvc0->vertex;
316 uint32_t refd = 0;
317 unsigned i;
318
319 PUSH_SPACE(push, vertex->num_elements * 8);
320 for (i = 0; i < vertex->num_elements; ++i) {
321 const struct nvc0_vertex_element *ve;
322 const struct pipe_vertex_buffer *vb;
323 struct nv04_resource *res;
324 unsigned b;
325 unsigned limit, offset;
326
327 if (nvc0->state.constant_elts & (1 << i))
328 continue;
329 ve = &vertex->element[i];
330 b = ve->pipe.vertex_buffer_index;
331 vb = &nvc0->vtxbuf[b];
332
333 if (!vb->buffer) {
334 if (vb->stride) {
335 if (ve->pipe.instance_divisor) {
336 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_DIVISOR(i)), 1);
337 PUSH_DATA (push, ve->pipe.instance_divisor);
338 }
339 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 1);
340 PUSH_DATA (push, (1 << 12) | vb->stride);
341 }
342 /* address/value set in nvc0_update_user_vbufs */
343 continue;
344 }
345 res = nv04_resource(vb->buffer);
346 offset = ve->pipe.src_offset + vb->buffer_offset;
347 limit = vb->buffer->width0 - 1;
348
349 if (unlikely(ve->pipe.instance_divisor)) {
350 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 4);
351 PUSH_DATA (push, (1 << 12) | vb->stride);
352 PUSH_DATAh(push, res->address + offset);
353 PUSH_DATA (push, res->address + offset);
354 PUSH_DATA (push, ve->pipe.instance_divisor);
355 } else {
356 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 3);
357 PUSH_DATA (push, (1 << 12) | vb->stride);
358 PUSH_DATAh(push, res->address + offset);
359 PUSH_DATA (push, res->address + offset);
360 }
361 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
362 PUSH_DATAh(push, res->address + limit);
363 PUSH_DATA (push, res->address + limit);
364
365 if (!(refd & (1 << b))) {
366 refd |= 1 << b;
367 BCTX_REFN(nvc0->bufctx_3d, VTX, res, RD);
368 }
369 }
370 if (nvc0->vbo_user)
371 nvc0_update_user_vbufs(nvc0);
372 }
373
374 static void
375 nvc0_validate_vertex_buffers_shared(struct nvc0_context *nvc0)
376 {
377 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
378 unsigned b;
379 const uint32_t mask = nvc0->vbo_user;
380
381 PUSH_SPACE(push, nvc0->num_vtxbufs * 8);
382 for (b = 0; b < nvc0->num_vtxbufs; ++b) {
383 struct pipe_vertex_buffer *vb = &nvc0->vtxbuf[b];
384 struct nv04_resource *buf;
385 uint32_t offset, limit;
386
387 if (mask & (1 << b)) {
388 if (vb->stride) {
389 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(b)), 1);
390 PUSH_DATA (push, NVC0_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
391 }
392 /* address/value set in nvc0_update_user_vbufs_shared */
393 continue;
394 }
395 buf = nv04_resource(vb->buffer);
396 offset = vb->buffer_offset;
397 limit = buf->base.width0 - 1;
398
399 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(b)), 3);
400 PUSH_DATA (push, NVC0_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
401 PUSH_DATAh(push, buf->address + offset);
402 PUSH_DATA (push, buf->address + offset);
403 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_LIMIT_HIGH(b)), 2);
404 PUSH_DATAh(push, buf->address + limit);
405 PUSH_DATA (push, buf->address + limit);
406
407 BCTX_REFN(nvc0->bufctx_3d, VTX, buf, RD);
408 }
409 if (nvc0->vbo_user)
410 nvc0_update_user_vbufs_shared(nvc0);
411 }
412
413 void
414 nvc0_vertex_arrays_validate(struct nvc0_context *nvc0)
415 {
416 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
417 struct nvc0_vertex_stateobj *vertex = nvc0->vertex;
418 struct nvc0_vertex_element *ve;
419 uint32_t const_vbos;
420 unsigned i;
421 uint8_t vbo_mode;
422 boolean update_vertex;
423
424 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_VTX);
425
426 if (unlikely(vertex->need_conversion) ||
427 unlikely(nvc0->vertprog->vp.edgeflag < PIPE_MAX_ATTRIBS)) {
428 vbo_mode = 3;
429 } else {
430 vbo_mode = (nvc0->vbo_user && nvc0->vbo_push_hint) ? 1 : 0;
431 }
432 const_vbos = vbo_mode ? 0 : nvc0->constant_vbos;
433
434 update_vertex = (nvc0->dirty & NVC0_NEW_VERTEX) ||
435 (const_vbos != nvc0->state.constant_vbos) ||
436 (vbo_mode != nvc0->state.vbo_mode);
437
438 if (update_vertex) {
439 const unsigned n = MAX2(vertex->num_elements, nvc0->state.num_vtxelts);
440
441 nvc0->state.constant_vbos = const_vbos;
442 nvc0->state.constant_elts = 0;
443 nvc0->state.num_vtxelts = vertex->num_elements;
444 nvc0->state.vbo_mode = vbo_mode;
445
446 if (unlikely(vbo_mode)) {
447 if (unlikely(nvc0->state.instance_elts & 3)) {
448 /* translate mode uses only 2 vertex buffers */
449 nvc0->state.instance_elts &= ~3;
450 PUSH_SPACE(push, 3);
451 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_PER_INSTANCE(0)), 2);
452 PUSH_DATA (push, 0);
453 PUSH_DATA (push, 0);
454 }
455
456 PUSH_SPACE(push, n * 2 + 4);
457
458 BEGIN_NVC0(push, NVC0_3D(VERTEX_ATTRIB_FORMAT(0)), n);
459 for (i = 0; i < vertex->num_elements; ++i)
460 PUSH_DATA(push, vertex->element[i].state_alt);
461 for (; i < n; ++i)
462 PUSH_DATA(push, NVC0_3D_VERTEX_ATTRIB_INACTIVE);
463
464 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(0)), 1);
465 PUSH_DATA (push, (1 << 12) | vertex->size);
466 for (i = 1; i < n; ++i)
467 IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 0);
468 } else {
469 uint32_t *restrict data;
470
471 if (unlikely(vertex->instance_elts != nvc0->state.instance_elts)) {
472 nvc0->state.instance_elts = vertex->instance_elts;
473 assert(n); /* if (n == 0), both masks should be 0 */
474 PUSH_SPACE(push, 3);
475 BEGIN_NVC0(push, NVC0_3D(MACRO_VERTEX_ARRAY_PER_INSTANCE), 2);
476 PUSH_DATA (push, n);
477 PUSH_DATA (push, vertex->instance_elts);
478 }
479
480 PUSH_SPACE(push, n * 2 + 1);
481 BEGIN_NVC0(push, NVC0_3D(VERTEX_ATTRIB_FORMAT(0)), n);
482 data = push->cur;
483 push->cur += n;
484 for (i = 0; i < vertex->num_elements; ++i) {
485 ve = &vertex->element[i];
486 data[i] = ve->state;
487 if (unlikely(const_vbos & (1 << ve->pipe.vertex_buffer_index))) {
488 nvc0->state.constant_elts |= 1 << i;
489 data[i] |= NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST;
490 IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 0);
491 }
492 }
493 for (; i < n; ++i) {
494 data[i] = NVC0_3D_VERTEX_ATTRIB_INACTIVE;
495 IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 0);
496 }
497 }
498 }
499 if (nvc0->state.vbo_mode) /* using translate, don't set up arrays here */
500 return;
501
502 if (vertex->shared_slots)
503 nvc0_validate_vertex_buffers_shared(nvc0);
504 else
505 nvc0_validate_vertex_buffers(nvc0);
506 }
507
508 void
509 nvc0_idxbuf_validate(struct nvc0_context *nvc0)
510 {
511 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
512 struct nv04_resource *buf = nv04_resource(nvc0->idxbuf.buffer);
513
514 assert(buf);
515 assert(nouveau_resource_mapped_by_gpu(&buf->base));
516
517 PUSH_SPACE(push, 6);
518 BEGIN_NVC0(push, NVC0_3D(INDEX_ARRAY_START_HIGH), 5);
519 PUSH_DATAh(push, buf->address + nvc0->idxbuf.offset);
520 PUSH_DATA (push, buf->address + nvc0->idxbuf.offset);
521 PUSH_DATAh(push, buf->address + buf->base.width0 - 1);
522 PUSH_DATA (push, buf->address + buf->base.width0 - 1);
523 PUSH_DATA (push, nvc0->idxbuf.index_size >> 1);
524
525 BCTX_REFN(nvc0->bufctx_3d, IDX, buf, RD);
526 }
527
528 #define NVC0_PRIM_GL_CASE(n) \
529 case PIPE_PRIM_##n: return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
530
531 static INLINE unsigned
532 nvc0_prim_gl(unsigned prim)
533 {
534 switch (prim) {
535 NVC0_PRIM_GL_CASE(POINTS);
536 NVC0_PRIM_GL_CASE(LINES);
537 NVC0_PRIM_GL_CASE(LINE_LOOP);
538 NVC0_PRIM_GL_CASE(LINE_STRIP);
539 NVC0_PRIM_GL_CASE(TRIANGLES);
540 NVC0_PRIM_GL_CASE(TRIANGLE_STRIP);
541 NVC0_PRIM_GL_CASE(TRIANGLE_FAN);
542 NVC0_PRIM_GL_CASE(QUADS);
543 NVC0_PRIM_GL_CASE(QUAD_STRIP);
544 NVC0_PRIM_GL_CASE(POLYGON);
545 NVC0_PRIM_GL_CASE(LINES_ADJACENCY);
546 NVC0_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
547 NVC0_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
548 NVC0_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
549 /*
550 NVC0_PRIM_GL_CASE(PATCHES); */
551 default:
552 return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
553 }
554 }
555
556 static void
557 nvc0_draw_vbo_kick_notify(struct nouveau_pushbuf *push)
558 {
559 struct nvc0_screen *screen = push->user_priv;
560
561 nouveau_fence_update(&screen->base, TRUE);
562
563 NOUVEAU_DRV_STAT(&screen->base, pushbuf_count, 1);
564 }
565
566 static void
567 nvc0_draw_arrays(struct nvc0_context *nvc0,
568 unsigned mode, unsigned start, unsigned count,
569 unsigned instance_count)
570 {
571 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
572 unsigned prim;
573
574 if (nvc0->state.index_bias) {
575 PUSH_SPACE(push, 1);
576 IMMED_NVC0(push, NVC0_3D(VB_ELEMENT_BASE), 0);
577 nvc0->state.index_bias = 0;
578 }
579
580 prim = nvc0_prim_gl(mode);
581
582 while (instance_count--) {
583 PUSH_SPACE(push, 6);
584 BEGIN_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), 1);
585 PUSH_DATA (push, prim);
586 BEGIN_NVC0(push, NVC0_3D(VERTEX_BUFFER_FIRST), 2);
587 PUSH_DATA (push, start);
588 PUSH_DATA (push, count);
589 IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
590
591 prim |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
592 }
593 NOUVEAU_DRV_STAT(&nvc0->screen->base, draw_calls_array, 1);
594 }
595
596 static void
597 nvc0_draw_elements_inline_u08(struct nouveau_pushbuf *push, const uint8_t *map,
598 unsigned start, unsigned count)
599 {
600 map += start;
601
602 if (count & 3) {
603 unsigned i;
604 PUSH_SPACE(push, 4);
605 BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U32), count & 3);
606 for (i = 0; i < (count & 3); ++i)
607 PUSH_DATA(push, *map++);
608 count &= ~3;
609 }
610 while (count) {
611 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4;
612
613 PUSH_SPACE(push, nr + 1);
614 BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U8), nr);
615 for (i = 0; i < nr; ++i) {
616 PUSH_DATA(push,
617 (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]);
618 map += 4;
619 }
620 count -= nr * 4;
621 }
622 }
623
624 static void
625 nvc0_draw_elements_inline_u16(struct nouveau_pushbuf *push, const uint16_t *map,
626 unsigned start, unsigned count)
627 {
628 map += start;
629
630 if (count & 1) {
631 count &= ~1;
632 PUSH_SPACE(push, 2);
633 BEGIN_NVC0(push, NVC0_3D(VB_ELEMENT_U32), 1);
634 PUSH_DATA (push, *map++);
635 }
636 while (count) {
637 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
638
639 PUSH_SPACE(push, nr + 1);
640 BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U16), nr);
641 for (i = 0; i < nr; ++i) {
642 PUSH_DATA(push, (map[1] << 16) | map[0]);
643 map += 2;
644 }
645 count -= nr * 2;
646 }
647 }
648
649 static void
650 nvc0_draw_elements_inline_u32(struct nouveau_pushbuf *push, const uint32_t *map,
651 unsigned start, unsigned count)
652 {
653 map += start;
654
655 while (count) {
656 const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
657
658 PUSH_SPACE(push, nr + 1);
659 BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U32), nr);
660 PUSH_DATAp(push, map, nr);
661
662 map += nr;
663 count -= nr;
664 }
665 }
666
667 static void
668 nvc0_draw_elements_inline_u32_short(struct nouveau_pushbuf *push,
669 const uint32_t *map,
670 unsigned start, unsigned count)
671 {
672 map += start;
673
674 if (count & 1) {
675 count--;
676 PUSH_SPACE(push, 1);
677 BEGIN_NVC0(push, NVC0_3D(VB_ELEMENT_U32), 1);
678 PUSH_DATA (push, *map++);
679 }
680 while (count) {
681 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
682
683 PUSH_SPACE(push, nr + 1);
684 BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U16), nr);
685 for (i = 0; i < nr; ++i) {
686 PUSH_DATA(push, (map[1] << 16) | map[0]);
687 map += 2;
688 }
689 count -= nr * 2;
690 }
691 }
692
693 static void
694 nvc0_draw_elements(struct nvc0_context *nvc0, boolean shorten,
695 unsigned mode, unsigned start, unsigned count,
696 unsigned instance_count, int32_t index_bias)
697 {
698 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
699 unsigned prim;
700 const unsigned index_size = nvc0->idxbuf.index_size;
701
702 prim = nvc0_prim_gl(mode);
703
704 if (index_bias != nvc0->state.index_bias) {
705 PUSH_SPACE(push, 2);
706 BEGIN_NVC0(push, NVC0_3D(VB_ELEMENT_BASE), 1);
707 PUSH_DATA (push, index_bias);
708 nvc0->state.index_bias = index_bias;
709 }
710
711 if (nvc0->idxbuf.buffer) {
712 PUSH_SPACE(push, 1);
713 IMMED_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), prim);
714 do {
715 PUSH_SPACE(push, 7);
716 BEGIN_NVC0(push, NVC0_3D(INDEX_BATCH_FIRST), 2);
717 PUSH_DATA (push, start);
718 PUSH_DATA (push, count);
719 if (--instance_count) {
720 BEGIN_NVC0(push, NVC0_3D(VERTEX_END_GL), 2);
721 PUSH_DATA (push, 0);
722 PUSH_DATA (push, prim | NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT);
723 }
724 } while (instance_count);
725 IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
726 } else {
727 const void *data = nvc0->idxbuf.user_buffer;
728
729 while (instance_count--) {
730 PUSH_SPACE(push, 2);
731 BEGIN_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), 1);
732 PUSH_DATA (push, prim);
733 switch (index_size) {
734 case 1:
735 nvc0_draw_elements_inline_u08(push, data, start, count);
736 break;
737 case 2:
738 nvc0_draw_elements_inline_u16(push, data, start, count);
739 break;
740 case 4:
741 if (shorten)
742 nvc0_draw_elements_inline_u32_short(push, data, start, count);
743 else
744 nvc0_draw_elements_inline_u32(push, data, start, count);
745 break;
746 default:
747 assert(0);
748 return;
749 }
750 PUSH_SPACE(push, 1);
751 IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
752
753 prim |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
754 }
755 }
756 NOUVEAU_DRV_STAT(&nvc0->screen->base, draw_calls_indexed, 1);
757 }
758
759 static void
760 nvc0_draw_stream_output(struct nvc0_context *nvc0,
761 const struct pipe_draw_info *info)
762 {
763 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
764 struct nvc0_so_target *so = nvc0_so_target(info->count_from_stream_output);
765 struct nv04_resource *res = nv04_resource(so->pipe.buffer);
766 unsigned mode = nvc0_prim_gl(info->mode);
767 unsigned num_instances = info->instance_count;
768
769 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
770 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
771 PUSH_SPACE(push, 2);
772 IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
773 nvc0_query_fifo_wait(push, so->pq);
774 IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FLUSH), 0);
775
776 NOUVEAU_DRV_STAT(&nvc0->screen->base, gpu_serialize_count, 1);
777 }
778
779 while (num_instances--) {
780 PUSH_SPACE(push, 8);
781 BEGIN_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), 1);
782 PUSH_DATA (push, mode);
783 BEGIN_NVC0(push, NVC0_3D(DRAW_TFB_BASE), 1);
784 PUSH_DATA (push, 0);
785 BEGIN_NVC0(push, NVC0_3D(DRAW_TFB_STRIDE), 1);
786 PUSH_DATA (push, so->stride);
787 BEGIN_NVC0(push, NVC0_3D(DRAW_TFB_BYTES), 1);
788 nvc0_query_pushbuf_submit(push, so->pq, 0x4);
789 IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
790
791 mode |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
792 }
793 }
794
795 void
796 nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
797 {
798 struct nvc0_context *nvc0 = nvc0_context(pipe);
799 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
800
801 /* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */
802 nvc0->vb_elt_first = info->min_index + info->index_bias;
803 nvc0->vb_elt_limit = info->max_index - info->min_index;
804 nvc0->instance_off = info->start_instance;
805 nvc0->instance_max = info->instance_count - 1;
806
807 /* For picking only a few vertices from a large user buffer, push is better,
808 * if index count is larger and we expect repeated vertices, suggest upload.
809 */
810 nvc0->vbo_push_hint =
811 info->indexed && (nvc0->vb_elt_limit >= (info->count * 2));
812
813 /* Check whether we want to switch vertex-submission mode. */
814 if (nvc0->vbo_user && !(nvc0->dirty & (NVC0_NEW_ARRAYS | NVC0_NEW_VERTEX))) {
815 if (nvc0->vbo_push_hint != !!nvc0->state.vbo_mode)
816 if (nvc0->state.vbo_mode != 3)
817 nvc0->dirty |= NVC0_NEW_ARRAYS;
818
819 if (!(nvc0->dirty & NVC0_NEW_ARRAYS) && nvc0->state.vbo_mode == 0) {
820 if (nvc0->vertex->shared_slots)
821 nvc0_update_user_vbufs_shared(nvc0);
822 else
823 nvc0_update_user_vbufs(nvc0);
824 }
825 }
826
827 /* 8 as minimum to avoid immediate double validation of new buffers */
828 nvc0_state_validate(nvc0, ~0, 8);
829
830 push->kick_notify = nvc0_draw_vbo_kick_notify;
831
832 if (nvc0->state.vbo_mode) {
833 nvc0_push_vbo(nvc0, info);
834 push->kick_notify = nvc0_default_kick_notify;
835 nouveau_pushbuf_bufctx(push, NULL);
836 return;
837 }
838
839 /* space for base instance, flush, and prim restart */
840 PUSH_SPACE(push, 8);
841
842 if (nvc0->state.instance_base != info->start_instance) {
843 nvc0->state.instance_base = info->start_instance;
844 /* NOTE: this does not affect the shader input, should it ? */
845 BEGIN_NVC0(push, NVC0_3D(VB_INSTANCE_BASE), 1);
846 PUSH_DATA (push, info->start_instance);
847 }
848
849 if (nvc0->base.vbo_dirty) {
850 IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FLUSH), 0);
851 nvc0->base.vbo_dirty = FALSE;
852 }
853
854 if (info->indexed) {
855 boolean shorten = info->max_index <= 65535;
856
857 if (info->primitive_restart != nvc0->state.prim_restart) {
858 if (info->primitive_restart) {
859 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_ENABLE), 2);
860 PUSH_DATA (push, 1);
861 PUSH_DATA (push, info->restart_index);
862
863 if (info->restart_index > 65535)
864 shorten = FALSE;
865 } else {
866 IMMED_NVC0(push, NVC0_3D(PRIM_RESTART_ENABLE), 0);
867 }
868 nvc0->state.prim_restart = info->primitive_restart;
869 } else
870 if (info->primitive_restart) {
871 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_INDEX), 1);
872 PUSH_DATA (push, info->restart_index);
873
874 if (info->restart_index > 65535)
875 shorten = FALSE;
876 }
877
878 nvc0_draw_elements(nvc0, shorten,
879 info->mode, info->start, info->count,
880 info->instance_count, info->index_bias);
881 } else
882 if (unlikely(info->count_from_stream_output)) {
883 nvc0_draw_stream_output(nvc0, info);
884 } else {
885 nvc0_draw_arrays(nvc0,
886 info->mode, info->start, info->count,
887 info->instance_count);
888 }
889 push->kick_notify = nvc0_default_kick_notify;
890
891 nvc0_release_user_vbufs(nvc0);
892
893 nouveau_pushbuf_bufctx(push, NULL);
894 }