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nvc0/cl: hande 64 bit pointers in nvc0_set_global_handle
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_vbo.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #define NVC0_PUSH_EXPLICIT_SPACE_CHECKING
24
25 #include "pipe/p_context.h"
26 #include "pipe/p_state.h"
27 #include "util/u_inlines.h"
28 #include "util/format/u_format.h"
29 #include "translate/translate.h"
30
31 #include "nvc0/nvc0_context.h"
32 #include "nvc0/nvc0_query_hw.h"
33 #include "nvc0/nvc0_resource.h"
34
35 #include "nvc0/nvc0_3d.xml.h"
36
37 void
38 nvc0_vertex_state_delete(struct pipe_context *pipe,
39 void *hwcso)
40 {
41 struct nvc0_vertex_stateobj *so = hwcso;
42
43 if (so->translate)
44 so->translate->release(so->translate);
45 FREE(hwcso);
46 }
47
48 void *
49 nvc0_vertex_state_create(struct pipe_context *pipe,
50 unsigned num_elements,
51 const struct pipe_vertex_element *elements)
52 {
53 struct nvc0_vertex_stateobj *so;
54 struct translate_key transkey;
55 unsigned i;
56 unsigned src_offset_max = 0;
57
58 so = MALLOC(sizeof(*so) +
59 num_elements * sizeof(struct nvc0_vertex_element));
60 if (!so)
61 return NULL;
62 so->num_elements = num_elements;
63 so->instance_elts = 0;
64 so->instance_bufs = 0;
65 so->shared_slots = false;
66 so->need_conversion = false;
67
68 memset(so->vb_access_size, 0, sizeof(so->vb_access_size));
69
70 for (i = 0; i < PIPE_MAX_ATTRIBS; ++i)
71 so->min_instance_div[i] = 0xffffffff;
72
73 transkey.nr_elements = 0;
74 transkey.output_stride = 0;
75
76 for (i = 0; i < num_elements; ++i) {
77 const struct pipe_vertex_element *ve = &elements[i];
78 const unsigned vbi = ve->vertex_buffer_index;
79 unsigned size;
80 enum pipe_format fmt = ve->src_format;
81
82 so->element[i].pipe = elements[i];
83 so->element[i].state = nvc0_vertex_format[fmt].vtx;
84
85 if (!so->element[i].state) {
86 switch (util_format_get_nr_components(fmt)) {
87 case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
88 case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
89 case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
90 case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
91 default:
92 assert(0);
93 FREE(so);
94 return NULL;
95 }
96 so->element[i].state = nvc0_vertex_format[fmt].vtx;
97 so->need_conversion = true;
98 pipe_debug_message(&nouveau_context(pipe)->debug, FALLBACK,
99 "Converting vertex element %d, no hw format %s",
100 i, util_format_name(ve->src_format));
101 }
102 size = util_format_get_blocksize(fmt);
103
104 src_offset_max = MAX2(src_offset_max, ve->src_offset);
105
106 if (so->vb_access_size[vbi] < (ve->src_offset + size))
107 so->vb_access_size[vbi] = ve->src_offset + size;
108
109 if (unlikely(ve->instance_divisor)) {
110 so->instance_elts |= 1 << i;
111 so->instance_bufs |= 1 << vbi;
112 if (ve->instance_divisor < so->min_instance_div[vbi])
113 so->min_instance_div[vbi] = ve->instance_divisor;
114 }
115
116 if (1) {
117 unsigned ca;
118 unsigned j = transkey.nr_elements++;
119
120 ca = util_format_description(fmt)->channel[0].size / 8;
121 if (ca != 1 && ca != 2)
122 ca = 4;
123
124 transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
125 transkey.element[j].input_format = ve->src_format;
126 transkey.element[j].input_buffer = vbi;
127 transkey.element[j].input_offset = ve->src_offset;
128 transkey.element[j].instance_divisor = ve->instance_divisor;
129
130 transkey.output_stride = align(transkey.output_stride, ca);
131 transkey.element[j].output_format = fmt;
132 transkey.element[j].output_offset = transkey.output_stride;
133 transkey.output_stride += size;
134
135 so->element[i].state_alt = so->element[i].state;
136 so->element[i].state_alt |= transkey.element[j].output_offset << 7;
137 }
138
139 so->element[i].state |= i << NVC0_3D_VERTEX_ATTRIB_FORMAT_BUFFER__SHIFT;
140 }
141 transkey.output_stride = align(transkey.output_stride, 4);
142
143 so->size = transkey.output_stride;
144 so->translate = translate_create(&transkey);
145
146 if (so->instance_elts || src_offset_max >= (1 << 14))
147 return so;
148 so->shared_slots = true;
149
150 for (i = 0; i < num_elements; ++i) {
151 const unsigned b = elements[i].vertex_buffer_index;
152 const unsigned s = elements[i].src_offset;
153 so->element[i].state &= ~NVC0_3D_VERTEX_ATTRIB_FORMAT_BUFFER__MASK;
154 so->element[i].state |= b << NVC0_3D_VERTEX_ATTRIB_FORMAT_BUFFER__SHIFT;
155 so->element[i].state |= s << NVC0_3D_VERTEX_ATTRIB_FORMAT_OFFSET__SHIFT;
156 }
157 return so;
158 }
159
160 #define NVC0_3D_VERTEX_ATTRIB_INACTIVE \
161 NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT | \
162 NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32 | NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST
163
164 #define VTX_ATTR(a, c, t, s) \
165 ((NVC0_3D_VTX_ATTR_DEFINE_TYPE_##t) | \
166 (NVC0_3D_VTX_ATTR_DEFINE_SIZE_##s) | \
167 ((a) << NVC0_3D_VTX_ATTR_DEFINE_ATTR__SHIFT) | \
168 ((c) << NVC0_3D_VTX_ATTR_DEFINE_COMP__SHIFT))
169
170 static void
171 nvc0_set_constant_vertex_attrib(struct nvc0_context *nvc0, const unsigned a)
172 {
173 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
174 struct pipe_vertex_element *ve = &nvc0->vertex->element[a].pipe;
175 struct pipe_vertex_buffer *vb = &nvc0->vtxbuf[ve->vertex_buffer_index];
176 uint32_t mode;
177 const struct util_format_description *desc;
178 void *dst;
179 const void *src = (const uint8_t *)vb->buffer.user + ve->src_offset;
180 assert(vb->is_user_buffer);
181
182 desc = util_format_description(ve->src_format);
183
184 PUSH_SPACE(push, 6);
185 BEGIN_NVC0(push, NVC0_3D(VTX_ATTR_DEFINE), 5);
186 dst = &push->cur[1];
187 util_format_unpack_rgba(ve->src_format, dst, src, 1);
188 if (desc->channel[0].pure_integer) {
189 if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED) {
190 mode = VTX_ATTR(a, 4, SINT, 32);
191 } else {
192 mode = VTX_ATTR(a, 4, UINT, 32);
193 }
194 } else {
195 mode = VTX_ATTR(a, 4, FLOAT, 32);
196 }
197 push->cur[0] = mode;
198 push->cur += 5;
199 }
200
201 static inline void
202 nvc0_user_vbuf_range(struct nvc0_context *nvc0, int vbi,
203 uint32_t *base, uint32_t *size)
204 {
205 if (unlikely(nvc0->vertex->instance_bufs & (1 << vbi))) {
206 const uint32_t div = nvc0->vertex->min_instance_div[vbi];
207 *base = nvc0->instance_off * nvc0->vtxbuf[vbi].stride;
208 *size = (nvc0->instance_max / div) * nvc0->vtxbuf[vbi].stride +
209 nvc0->vertex->vb_access_size[vbi];
210 } else {
211 /* NOTE: if there are user buffers, we *must* have index bounds */
212 assert(nvc0->vb_elt_limit != ~0);
213 *base = nvc0->vb_elt_first * nvc0->vtxbuf[vbi].stride;
214 *size = nvc0->vb_elt_limit * nvc0->vtxbuf[vbi].stride +
215 nvc0->vertex->vb_access_size[vbi];
216 }
217 }
218
219 static inline void
220 nvc0_release_user_vbufs(struct nvc0_context *nvc0)
221 {
222 if (nvc0->vbo_user) {
223 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_VTX_TMP);
224 nouveau_scratch_done(&nvc0->base);
225 }
226 }
227
228 static void
229 nvc0_update_user_vbufs(struct nvc0_context *nvc0)
230 {
231 uint64_t address[PIPE_MAX_ATTRIBS];
232 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
233 int i;
234 uint32_t written = 0;
235
236 PUSH_SPACE(push, nvc0->vertex->num_elements * 8);
237 for (i = 0; i < nvc0->vertex->num_elements; ++i) {
238 struct pipe_vertex_element *ve = &nvc0->vertex->element[i].pipe;
239 const unsigned b = ve->vertex_buffer_index;
240 struct pipe_vertex_buffer *vb = &nvc0->vtxbuf[b];
241 uint32_t base, size;
242
243 if (!(nvc0->vbo_user & (1 << b)))
244 continue;
245 if (nvc0->constant_vbos & (1 << b)) {
246 nvc0_set_constant_vertex_attrib(nvc0, i);
247 continue;
248 }
249 nvc0_user_vbuf_range(nvc0, b, &base, &size);
250
251 if (!(written & (1 << b))) {
252 struct nouveau_bo *bo;
253 const uint32_t bo_flags = NOUVEAU_BO_RD | NOUVEAU_BO_GART;
254 written |= 1 << b;
255 address[b] = nouveau_scratch_data(&nvc0->base, vb->buffer.user,
256 base, size, &bo);
257 if (bo)
258 BCTX_REFN_bo(nvc0->bufctx_3d, 3D_VTX_TMP, bo_flags, bo);
259
260 NOUVEAU_DRV_STAT(&nvc0->screen->base, user_buffer_upload_bytes, size);
261 }
262
263 BEGIN_1IC0(push, NVC0_3D(MACRO_VERTEX_ARRAY_SELECT), 5);
264 PUSH_DATA (push, i);
265 PUSH_DATAh(push, address[b] + base + size - 1);
266 PUSH_DATA (push, address[b] + base + size - 1);
267 PUSH_DATAh(push, address[b] + ve->src_offset);
268 PUSH_DATA (push, address[b] + ve->src_offset);
269 }
270 nvc0->base.vbo_dirty = true;
271 }
272
273 static void
274 nvc0_update_user_vbufs_shared(struct nvc0_context *nvc0)
275 {
276 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
277 uint32_t mask = nvc0->vbo_user & ~nvc0->constant_vbos;
278
279 PUSH_SPACE(push, nvc0->num_vtxbufs * 8);
280 while (mask) {
281 struct nouveau_bo *bo;
282 const uint32_t bo_flags = NOUVEAU_BO_RD | NOUVEAU_BO_GART;
283 uint64_t address;
284 uint32_t base, size;
285 const int b = ffs(mask) - 1;
286 mask &= ~(1 << b);
287
288 nvc0_user_vbuf_range(nvc0, b, &base, &size);
289
290 address = nouveau_scratch_data(&nvc0->base, nvc0->vtxbuf[b].buffer.user,
291 base, size, &bo);
292 if (bo)
293 BCTX_REFN_bo(nvc0->bufctx_3d, 3D_VTX_TMP, bo_flags, bo);
294
295 BEGIN_1IC0(push, NVC0_3D(MACRO_VERTEX_ARRAY_SELECT), 5);
296 PUSH_DATA (push, b);
297 PUSH_DATAh(push, address + base + size - 1);
298 PUSH_DATA (push, address + base + size - 1);
299 PUSH_DATAh(push, address);
300 PUSH_DATA (push, address);
301
302 NOUVEAU_DRV_STAT(&nvc0->screen->base, user_buffer_upload_bytes, size);
303 }
304
305 mask = nvc0->state.constant_elts;
306 while (mask) {
307 int i = ffs(mask) - 1;
308 mask &= ~(1 << i);
309 nvc0_set_constant_vertex_attrib(nvc0, i);
310 }
311 }
312
313 static void
314 nvc0_validate_vertex_buffers(struct nvc0_context *nvc0)
315 {
316 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
317 const struct nvc0_vertex_stateobj *vertex = nvc0->vertex;
318 uint32_t refd = 0;
319 unsigned i;
320
321 PUSH_SPACE(push, vertex->num_elements * 8);
322 for (i = 0; i < vertex->num_elements; ++i) {
323 const struct nvc0_vertex_element *ve;
324 const struct pipe_vertex_buffer *vb;
325 struct nv04_resource *res;
326 unsigned b;
327 unsigned limit, offset;
328
329 if (nvc0->state.constant_elts & (1 << i))
330 continue;
331 ve = &vertex->element[i];
332 b = ve->pipe.vertex_buffer_index;
333 vb = &nvc0->vtxbuf[b];
334
335 if (nvc0->vbo_user & (1 << b)) {
336 if (!(nvc0->constant_vbos & (1 << b))) {
337 if (ve->pipe.instance_divisor) {
338 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_DIVISOR(i)), 1);
339 PUSH_DATA (push, ve->pipe.instance_divisor);
340 }
341 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 1);
342 PUSH_DATA (push, (1 << 12) | vb->stride);
343 }
344 /* address/value set in nvc0_update_user_vbufs */
345 continue;
346 }
347 res = nv04_resource(vb->buffer.resource);
348 offset = ve->pipe.src_offset + vb->buffer_offset;
349 limit = vb->buffer.resource->width0 - 1;
350
351 if (unlikely(ve->pipe.instance_divisor)) {
352 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 4);
353 PUSH_DATA (push, NVC0_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
354 PUSH_DATAh(push, res->address + offset);
355 PUSH_DATA (push, res->address + offset);
356 PUSH_DATA (push, ve->pipe.instance_divisor);
357 } else {
358 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 3);
359 PUSH_DATA (push, NVC0_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
360 PUSH_DATAh(push, res->address + offset);
361 PUSH_DATA (push, res->address + offset);
362 }
363
364 if (nvc0->screen->eng3d->oclass < TU102_3D_CLASS)
365 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
366 else
367 BEGIN_NVC0(push, SUBC_3D(TU102_3D_VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
368 PUSH_DATAh(push, res->address + limit);
369 PUSH_DATA (push, res->address + limit);
370
371 if (!(refd & (1 << b))) {
372 refd |= 1 << b;
373 BCTX_REFN(nvc0->bufctx_3d, 3D_VTX, res, RD);
374 }
375 }
376 if (nvc0->vbo_user)
377 nvc0_update_user_vbufs(nvc0);
378 }
379
380 static void
381 nvc0_validate_vertex_buffers_shared(struct nvc0_context *nvc0)
382 {
383 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
384 unsigned b;
385 const uint32_t mask = nvc0->vbo_user;
386
387 PUSH_SPACE(push, nvc0->num_vtxbufs * 8 + nvc0->vertex->num_elements);
388 for (b = 0; b < nvc0->num_vtxbufs; ++b) {
389 struct pipe_vertex_buffer *vb = &nvc0->vtxbuf[b];
390 struct nv04_resource *buf;
391 uint32_t offset, limit;
392
393 if (mask & (1 << b)) {
394 if (!(nvc0->constant_vbos & (1 << b))) {
395 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(b)), 1);
396 PUSH_DATA (push, NVC0_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
397 }
398 /* address/value set in nvc0_update_user_vbufs_shared */
399 continue;
400 } else if (!vb->buffer.resource) {
401 /* there can be holes in the vertex buffer lists */
402 IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(b)), 0);
403 continue;
404 }
405 buf = nv04_resource(vb->buffer.resource);
406 offset = vb->buffer_offset;
407 limit = buf->base.width0 - 1;
408
409 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(b)), 3);
410 PUSH_DATA (push, NVC0_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
411 PUSH_DATAh(push, buf->address + offset);
412 PUSH_DATA (push, buf->address + offset);
413
414 if (nvc0->screen->eng3d->oclass < TU102_3D_CLASS)
415 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_LIMIT_HIGH(b)), 2);
416 else
417 BEGIN_NVC0(push, SUBC_3D(TU102_3D_VERTEX_ARRAY_LIMIT_HIGH(b)), 2);
418 PUSH_DATAh(push, buf->address + limit);
419 PUSH_DATA (push, buf->address + limit);
420
421 BCTX_REFN(nvc0->bufctx_3d, 3D_VTX, buf, RD);
422 }
423 /* If there are more elements than buffers, we might not have unset
424 * fetching on the later elements.
425 */
426 for (; b < nvc0->vertex->num_elements; ++b)
427 IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(b)), 0);
428
429 if (nvc0->vbo_user)
430 nvc0_update_user_vbufs_shared(nvc0);
431 }
432
433 void
434 nvc0_vertex_arrays_validate(struct nvc0_context *nvc0)
435 {
436 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
437 struct nvc0_vertex_stateobj *vertex = nvc0->vertex;
438 struct nvc0_vertex_element *ve;
439 uint32_t const_vbos;
440 unsigned i;
441 uint8_t vbo_mode;
442 bool update_vertex;
443
444 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_VTX);
445
446 assert(vertex);
447 if (unlikely(vertex->need_conversion) ||
448 unlikely(nvc0->vertprog->vp.edgeflag < PIPE_MAX_ATTRIBS)) {
449 vbo_mode = 3;
450 } else if (nvc0->vbo_user & ~nvc0->constant_vbos) {
451 vbo_mode = nvc0->vbo_push_hint ? 1 : 0;
452 } else {
453 vbo_mode = 0;
454 }
455 const_vbos = vbo_mode ? 0 : nvc0->constant_vbos;
456
457 update_vertex = (nvc0->dirty_3d & NVC0_NEW_3D_VERTEX) ||
458 (const_vbos != nvc0->state.constant_vbos) ||
459 (vbo_mode != nvc0->state.vbo_mode);
460
461 if (update_vertex) {
462 const unsigned n = MAX2(vertex->num_elements, nvc0->state.num_vtxelts);
463
464 nvc0->state.constant_vbos = const_vbos;
465 nvc0->state.constant_elts = 0;
466 nvc0->state.num_vtxelts = vertex->num_elements;
467 nvc0->state.vbo_mode = vbo_mode;
468
469 if (unlikely(vbo_mode)) {
470 if (unlikely(nvc0->state.instance_elts & 3)) {
471 /* translate mode uses only 2 vertex buffers */
472 nvc0->state.instance_elts &= ~3;
473 PUSH_SPACE(push, 3);
474 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_PER_INSTANCE(0)), 2);
475 PUSH_DATA (push, 0);
476 PUSH_DATA (push, 0);
477 }
478
479 PUSH_SPACE(push, n * 2 + 4);
480
481 BEGIN_NVC0(push, NVC0_3D(VERTEX_ATTRIB_FORMAT(0)), n);
482 for (i = 0; i < vertex->num_elements; ++i)
483 PUSH_DATA(push, vertex->element[i].state_alt);
484 for (; i < n; ++i)
485 PUSH_DATA(push, NVC0_3D_VERTEX_ATTRIB_INACTIVE);
486
487 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(0)), 1);
488 PUSH_DATA (push, (1 << 12) | vertex->size);
489 for (i = 1; i < n; ++i)
490 IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 0);
491 } else {
492 uint32_t *restrict data;
493
494 if (unlikely(vertex->instance_elts != nvc0->state.instance_elts)) {
495 nvc0->state.instance_elts = vertex->instance_elts;
496 assert(n); /* if (n == 0), both masks should be 0 */
497 PUSH_SPACE(push, 3);
498 BEGIN_NVC0(push, NVC0_3D(MACRO_VERTEX_ARRAY_PER_INSTANCE), 2);
499 PUSH_DATA (push, n);
500 PUSH_DATA (push, vertex->instance_elts);
501 }
502
503 PUSH_SPACE(push, n * 2 + 1);
504 BEGIN_NVC0(push, NVC0_3D(VERTEX_ATTRIB_FORMAT(0)), n);
505 data = push->cur;
506 push->cur += n;
507 for (i = 0; i < vertex->num_elements; ++i) {
508 ve = &vertex->element[i];
509 data[i] = ve->state;
510 if (unlikely(const_vbos & (1 << ve->pipe.vertex_buffer_index))) {
511 nvc0->state.constant_elts |= 1 << i;
512 data[i] |= NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST;
513 IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 0);
514 }
515 }
516 for (; i < n; ++i) {
517 data[i] = NVC0_3D_VERTEX_ATTRIB_INACTIVE;
518 IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 0);
519 }
520 }
521 }
522 if (nvc0->state.vbo_mode) /* using translate, don't set up arrays here */
523 return;
524
525 if (vertex->shared_slots)
526 nvc0_validate_vertex_buffers_shared(nvc0);
527 else
528 nvc0_validate_vertex_buffers(nvc0);
529 }
530
531 #define NVC0_PRIM_GL_CASE(n) \
532 case PIPE_PRIM_##n: return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
533
534 static inline unsigned
535 nvc0_prim_gl(unsigned prim)
536 {
537 switch (prim) {
538 NVC0_PRIM_GL_CASE(POINTS);
539 NVC0_PRIM_GL_CASE(LINES);
540 NVC0_PRIM_GL_CASE(LINE_LOOP);
541 NVC0_PRIM_GL_CASE(LINE_STRIP);
542 NVC0_PRIM_GL_CASE(TRIANGLES);
543 NVC0_PRIM_GL_CASE(TRIANGLE_STRIP);
544 NVC0_PRIM_GL_CASE(TRIANGLE_FAN);
545 NVC0_PRIM_GL_CASE(QUADS);
546 NVC0_PRIM_GL_CASE(QUAD_STRIP);
547 NVC0_PRIM_GL_CASE(POLYGON);
548 NVC0_PRIM_GL_CASE(LINES_ADJACENCY);
549 NVC0_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
550 NVC0_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
551 NVC0_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
552 NVC0_PRIM_GL_CASE(PATCHES);
553 default:
554 return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
555 }
556 }
557
558 static void
559 nvc0_draw_vbo_kick_notify(struct nouveau_pushbuf *push)
560 {
561 struct nvc0_screen *screen = push->user_priv;
562
563 nouveau_fence_update(&screen->base, true);
564
565 NOUVEAU_DRV_STAT(&screen->base, pushbuf_count, 1);
566 }
567
568 static void
569 nvc0_draw_arrays(struct nvc0_context *nvc0,
570 unsigned mode, unsigned start, unsigned count,
571 unsigned instance_count)
572 {
573 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
574 unsigned prim;
575
576 if (nvc0->state.index_bias) {
577 /* index_bias is implied 0 if !info->index_size (really ?) */
578 /* TODO: can we deactivate it for the VERTEX_BUFFER_FIRST command ? */
579 PUSH_SPACE(push, 2);
580 IMMED_NVC0(push, NVC0_3D(VB_ELEMENT_BASE), 0);
581 IMMED_NVC0(push, NVC0_3D(VERTEX_ID_BASE), 0);
582 nvc0->state.index_bias = 0;
583 }
584
585 prim = nvc0_prim_gl(mode);
586
587 while (instance_count--) {
588 PUSH_SPACE(push, 6);
589 BEGIN_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), 1);
590 PUSH_DATA (push, prim);
591 BEGIN_NVC0(push, NVC0_3D(VERTEX_BUFFER_FIRST), 2);
592 PUSH_DATA (push, start);
593 PUSH_DATA (push, count);
594 IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
595
596 prim |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
597 }
598 NOUVEAU_DRV_STAT(&nvc0->screen->base, draw_calls_array, 1);
599 }
600
601 static void
602 nvc0_draw_elements_inline_u08(struct nouveau_pushbuf *push, const uint8_t *map,
603 unsigned start, unsigned count)
604 {
605 map += start;
606
607 if (count & 3) {
608 unsigned i;
609 PUSH_SPACE(push, 4);
610 BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U32), count & 3);
611 for (i = 0; i < (count & 3); ++i)
612 PUSH_DATA(push, *map++);
613 count &= ~3;
614 }
615 while (count) {
616 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4;
617
618 PUSH_SPACE(push, nr + 1);
619 BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U8), nr);
620 for (i = 0; i < nr; ++i) {
621 PUSH_DATA(push,
622 (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]);
623 map += 4;
624 }
625 count -= nr * 4;
626 }
627 }
628
629 static void
630 nvc0_draw_elements_inline_u16(struct nouveau_pushbuf *push, const uint16_t *map,
631 unsigned start, unsigned count)
632 {
633 map += start;
634
635 if (count & 1) {
636 count &= ~1;
637 PUSH_SPACE(push, 2);
638 BEGIN_NVC0(push, NVC0_3D(VB_ELEMENT_U32), 1);
639 PUSH_DATA (push, *map++);
640 }
641 while (count) {
642 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
643
644 PUSH_SPACE(push, nr + 1);
645 BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U16), nr);
646 for (i = 0; i < nr; ++i) {
647 PUSH_DATA(push, (map[1] << 16) | map[0]);
648 map += 2;
649 }
650 count -= nr * 2;
651 }
652 }
653
654 static void
655 nvc0_draw_elements_inline_u32(struct nouveau_pushbuf *push, const uint32_t *map,
656 unsigned start, unsigned count)
657 {
658 map += start;
659
660 while (count) {
661 const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
662
663 PUSH_SPACE(push, nr + 1);
664 BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U32), nr);
665 PUSH_DATAp(push, map, nr);
666
667 map += nr;
668 count -= nr;
669 }
670 }
671
672 static void
673 nvc0_draw_elements_inline_u32_short(struct nouveau_pushbuf *push,
674 const uint32_t *map,
675 unsigned start, unsigned count)
676 {
677 map += start;
678
679 if (count & 1) {
680 count--;
681 PUSH_SPACE(push, 2);
682 BEGIN_NVC0(push, NVC0_3D(VB_ELEMENT_U32), 1);
683 PUSH_DATA (push, *map++);
684 }
685 while (count) {
686 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
687
688 PUSH_SPACE(push, nr + 1);
689 BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U16), nr);
690 for (i = 0; i < nr; ++i) {
691 PUSH_DATA(push, (map[1] << 16) | map[0]);
692 map += 2;
693 }
694 count -= nr * 2;
695 }
696 }
697
698 static void
699 nvc0_draw_elements(struct nvc0_context *nvc0, bool shorten,
700 const struct pipe_draw_info *info,
701 unsigned mode, unsigned start, unsigned count,
702 unsigned instance_count, int32_t index_bias,
703 unsigned index_size)
704 {
705 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
706 unsigned prim;
707
708 prim = nvc0_prim_gl(mode);
709
710 if (index_bias != nvc0->state.index_bias) {
711 PUSH_SPACE(push, 4);
712 BEGIN_NVC0(push, NVC0_3D(VB_ELEMENT_BASE), 1);
713 PUSH_DATA (push, index_bias);
714 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_BASE), 1);
715 PUSH_DATA (push, index_bias);
716 nvc0->state.index_bias = index_bias;
717 }
718
719 if (!info->has_user_indices) {
720 PUSH_SPACE(push, 1);
721 IMMED_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), prim);
722 do {
723 PUSH_SPACE(push, 7);
724 BEGIN_NVC0(push, NVC0_3D(INDEX_BATCH_FIRST), 2);
725 PUSH_DATA (push, start);
726 PUSH_DATA (push, count);
727 if (--instance_count) {
728 BEGIN_NVC0(push, NVC0_3D(VERTEX_END_GL), 2);
729 PUSH_DATA (push, 0);
730 PUSH_DATA (push, prim | NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT);
731 }
732 } while (instance_count);
733 IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
734 } else {
735 const void *data = info->index.user;
736
737 while (instance_count--) {
738 PUSH_SPACE(push, 2);
739 BEGIN_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), 1);
740 PUSH_DATA (push, prim);
741 switch (index_size) {
742 case 1:
743 nvc0_draw_elements_inline_u08(push, data, start, count);
744 break;
745 case 2:
746 nvc0_draw_elements_inline_u16(push, data, start, count);
747 break;
748 case 4:
749 if (shorten)
750 nvc0_draw_elements_inline_u32_short(push, data, start, count);
751 else
752 nvc0_draw_elements_inline_u32(push, data, start, count);
753 break;
754 default:
755 assert(0);
756 return;
757 }
758 PUSH_SPACE(push, 1);
759 IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
760
761 prim |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
762 }
763 }
764 NOUVEAU_DRV_STAT(&nvc0->screen->base, draw_calls_indexed, 1);
765 }
766
767 static void
768 nvc0_draw_stream_output(struct nvc0_context *nvc0,
769 const struct pipe_draw_info *info)
770 {
771 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
772 struct nvc0_so_target *so = nvc0_so_target(info->count_from_stream_output);
773 struct nv04_resource *res = nv04_resource(so->pipe.buffer);
774 unsigned mode = nvc0_prim_gl(info->mode);
775 unsigned num_instances = info->instance_count;
776
777 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
778 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
779 PUSH_SPACE(push, 2);
780 IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
781 nvc0_hw_query_fifo_wait(nvc0, nvc0_query(so->pq));
782 if (nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
783 IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FLUSH), 0);
784
785 NOUVEAU_DRV_STAT(&nvc0->screen->base, gpu_serialize_count, 1);
786 }
787
788 while (num_instances--) {
789 nouveau_pushbuf_space(push, 16, 0, 1);
790 BEGIN_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), 1);
791 PUSH_DATA (push, mode);
792 BEGIN_NVC0(push, NVC0_3D(DRAW_TFB_BASE), 1);
793 PUSH_DATA (push, 0);
794 BEGIN_NVC0(push, NVC0_3D(DRAW_TFB_STRIDE), 1);
795 PUSH_DATA (push, so->stride);
796 BEGIN_NVC0(push, NVC0_3D(DRAW_TFB_BYTES), 1);
797 nvc0_hw_query_pushbuf_submit(push, nvc0_query(so->pq), 0x4);
798 IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
799
800 mode |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
801 }
802 }
803
804 static void
805 nvc0_draw_indirect(struct nvc0_context *nvc0, const struct pipe_draw_info *info)
806 {
807 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
808 struct nv04_resource *buf = nv04_resource(info->indirect->buffer);
809 struct nv04_resource *buf_count = nv04_resource(info->indirect->indirect_draw_count);
810 unsigned size, macro, count = info->indirect->draw_count, drawid = info->drawid;
811 uint32_t offset = buf->offset + info->indirect->offset;
812 struct nvc0_screen *screen = nvc0->screen;
813
814 PUSH_SPACE(push, 7);
815
816 /* must make FIFO wait for engines idle before continuing to process */
817 if ((buf->fence_wr && !nouveau_fence_signalled(buf->fence_wr)) ||
818 (buf_count && buf_count->fence_wr &&
819 !nouveau_fence_signalled(buf_count->fence_wr))) {
820 IMMED_NVC0(push, SUBC_3D(NV10_SUBCHAN_REF_CNT), 0);
821 }
822
823 /* Queue things up to let the macros write params to the driver constbuf */
824 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
825 PUSH_DATA (push, NVC0_CB_AUX_SIZE);
826 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(0));
827 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(0));
828 BEGIN_NVC0(push, NVC0_3D(CB_POS), 1);
829 PUSH_DATA (push, NVC0_CB_AUX_DRAW_INFO);
830
831 if (info->index_size) {
832 assert(!info->has_user_indices);
833 assert(nouveau_resource_mapped_by_gpu(info->index.resource));
834 size = 5;
835 if (buf_count)
836 macro = NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT;
837 else
838 macro = NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT;
839 } else {
840 if (nvc0->state.index_bias) {
841 /* index_bias is implied 0 if !info->index_size (really ?) */
842 IMMED_NVC0(push, NVC0_3D(VB_ELEMENT_BASE), 0);
843 IMMED_NVC0(push, NVC0_3D(VERTEX_ID_BASE), 0);
844 nvc0->state.index_bias = 0;
845 }
846 size = 4;
847 if (buf_count)
848 macro = NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT;
849 else
850 macro = NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT;
851 }
852
853 /* If the stride is not the natural stride, we have to stick a separate
854 * push data reference for each draw. Otherwise it can all go in as one.
855 * Of course there is a maximum packet size, so we have to break things up
856 * along those borders as well.
857 */
858 while (count) {
859 unsigned draws = count, pushes, i;
860 if (info->indirect->stride == size * 4) {
861 draws = MIN2(draws, (NV04_PFIFO_MAX_PACKET_LEN - 4) / size);
862 pushes = 1;
863 } else {
864 draws = MIN2(draws, 32);
865 pushes = draws;
866 }
867
868 nouveau_pushbuf_space(push, 16, 0, pushes + !!buf_count);
869 PUSH_REFN(push, buf->bo, NOUVEAU_BO_RD | buf->domain);
870 if (buf_count)
871 PUSH_REFN(push, buf_count->bo, NOUVEAU_BO_RD | buf_count->domain);
872 PUSH_DATA(push,
873 NVC0_FIFO_PKHDR_1I(0, macro, 3 + !!buf_count + draws * size));
874 PUSH_DATA(push, nvc0_prim_gl(info->mode));
875 PUSH_DATA(push, drawid);
876 PUSH_DATA(push, draws);
877 if (buf_count) {
878 nouveau_pushbuf_data(push,
879 buf_count->bo,
880 buf_count->offset + info->indirect->indirect_draw_count_offset,
881 NVC0_IB_ENTRY_1_NO_PREFETCH | 4);
882 }
883 if (pushes == 1) {
884 nouveau_pushbuf_data(push,
885 buf->bo, offset,
886 NVC0_IB_ENTRY_1_NO_PREFETCH | (size * 4 * draws));
887 offset += draws * info->indirect->stride;
888 } else {
889 for (i = 0; i < pushes; i++) {
890 nouveau_pushbuf_data(push,
891 buf->bo, offset,
892 NVC0_IB_ENTRY_1_NO_PREFETCH | (size * 4));
893 offset += info->indirect->stride;
894 }
895 }
896 count -= draws;
897 drawid += draws;
898 }
899 }
900
901 static inline void
902 nvc0_update_prim_restart(struct nvc0_context *nvc0, bool en, uint32_t index)
903 {
904 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
905
906 if (en != nvc0->state.prim_restart) {
907 if (en) {
908 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_ENABLE), 2);
909 PUSH_DATA (push, 1);
910 PUSH_DATA (push, index);
911 } else {
912 IMMED_NVC0(push, NVC0_3D(PRIM_RESTART_ENABLE), 0);
913 }
914 nvc0->state.prim_restart = en;
915 } else
916 if (en) {
917 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_INDEX), 1);
918 PUSH_DATA (push, index);
919 }
920 }
921
922 void
923 nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
924 {
925 struct nvc0_context *nvc0 = nvc0_context(pipe);
926 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
927 struct nvc0_screen *screen = nvc0->screen;
928 unsigned vram_domain = NV_VRAM_DOMAIN(&screen->base);
929 int s;
930
931 /* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */
932 nvc0->vb_elt_first = info->min_index + info->index_bias;
933 nvc0->vb_elt_limit = info->max_index - info->min_index;
934 nvc0->instance_off = info->start_instance;
935 nvc0->instance_max = info->instance_count - 1;
936
937 /* For picking only a few vertices from a large user buffer, push is better,
938 * if index count is larger and we expect repeated vertices, suggest upload.
939 */
940 nvc0->vbo_push_hint =
941 !info->indirect && info->index_size &&
942 (nvc0->vb_elt_limit >= (info->count * 2));
943
944 /* Check whether we want to switch vertex-submission mode. */
945 if (nvc0->vbo_user && !(nvc0->dirty_3d & (NVC0_NEW_3D_ARRAYS | NVC0_NEW_3D_VERTEX))) {
946 if (nvc0->vbo_push_hint != !!nvc0->state.vbo_mode)
947 if (nvc0->state.vbo_mode != 3)
948 nvc0->dirty_3d |= NVC0_NEW_3D_ARRAYS;
949
950 if (!(nvc0->dirty_3d & NVC0_NEW_3D_ARRAYS) && nvc0->state.vbo_mode == 0) {
951 if (nvc0->vertex->shared_slots)
952 nvc0_update_user_vbufs_shared(nvc0);
953 else
954 nvc0_update_user_vbufs(nvc0);
955 }
956 }
957
958 if (info->mode == PIPE_PRIM_PATCHES &&
959 nvc0->state.patch_vertices != info->vertices_per_patch) {
960 nvc0->state.patch_vertices = info->vertices_per_patch;
961 PUSH_SPACE(push, 1);
962 IMMED_NVC0(push, NVC0_3D(PATCH_VERTICES), nvc0->state.patch_vertices);
963 }
964
965 if (info->index_size && !info->has_user_indices) {
966 struct nv04_resource *buf = nv04_resource(info->index.resource);
967
968 assert(buf);
969 assert(nouveau_resource_mapped_by_gpu(&buf->base));
970
971 PUSH_SPACE(push, 6);
972 if (nvc0->screen->eng3d->oclass < TU102_3D_CLASS) {
973 BEGIN_NVC0(push, NVC0_3D(INDEX_ARRAY_START_HIGH), 5);
974 PUSH_DATAh(push, buf->address);
975 PUSH_DATA (push, buf->address);
976 PUSH_DATAh(push, buf->address + buf->base.width0 - 1);
977 PUSH_DATA (push, buf->address + buf->base.width0 - 1);
978 PUSH_DATA (push, info->index_size >> 1);
979 } else {
980 BEGIN_NVC0(push, NVC0_3D(INDEX_ARRAY_START_HIGH), 2);
981 PUSH_DATAh(push, buf->address);
982 PUSH_DATA (push, buf->address);
983 BEGIN_NVC0(push, SUBC_3D(TU102_3D_INDEX_ARRAY_LIMIT_HIGH), 2);
984 PUSH_DATAh(push, buf->address + buf->base.width0 - 1);
985 PUSH_DATA (push, buf->address + buf->base.width0 - 1);
986 BEGIN_NVC0(push, NVC0_3D(INDEX_FORMAT), 1);
987 PUSH_DATA (push, info->index_size >> 1);
988 }
989
990 BCTX_REFN(nvc0->bufctx_3d, 3D_IDX, buf, RD);
991 }
992
993 list_for_each_entry(struct nvc0_resident, resident, &nvc0->tex_head, list) {
994 nvc0_add_resident(nvc0->bufctx_3d, NVC0_BIND_3D_BINDLESS, resident->buf,
995 resident->flags);
996 }
997
998 list_for_each_entry(struct nvc0_resident, resident, &nvc0->img_head, list) {
999 nvc0_add_resident(nvc0->bufctx_3d, NVC0_BIND_3D_BINDLESS, resident->buf,
1000 resident->flags);
1001 }
1002
1003 BCTX_REFN_bo(nvc0->bufctx_3d, 3D_TEXT, vram_domain | NOUVEAU_BO_RD,
1004 screen->text);
1005
1006 nvc0_state_validate_3d(nvc0, ~0);
1007
1008 if (nvc0->vertprog->vp.need_draw_parameters && !info->indirect) {
1009 PUSH_SPACE(push, 9);
1010 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1011 PUSH_DATA (push, NVC0_CB_AUX_SIZE);
1012 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(0));
1013 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(0));
1014 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 3);
1015 PUSH_DATA (push, NVC0_CB_AUX_DRAW_INFO);
1016 PUSH_DATA (push, info->index_bias);
1017 PUSH_DATA (push, info->start_instance);
1018 PUSH_DATA (push, info->drawid);
1019 }
1020
1021 if (nvc0->screen->base.class_3d < NVE4_3D_CLASS &&
1022 nvc0->seamless_cube_map != nvc0->state.seamless_cube_map) {
1023 nvc0->state.seamless_cube_map = nvc0->seamless_cube_map;
1024 PUSH_SPACE(push, 1);
1025 IMMED_NVC0(push, NVC0_3D(TEX_MISC),
1026 nvc0->seamless_cube_map ? NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP : 0);
1027 }
1028
1029 push->kick_notify = nvc0_draw_vbo_kick_notify;
1030
1031 for (s = 0; s < 5 && !nvc0->cb_dirty; ++s) {
1032 if (nvc0->constbuf_coherent[s])
1033 nvc0->cb_dirty = true;
1034 }
1035
1036 if (nvc0->cb_dirty) {
1037 PUSH_SPACE(push, 1);
1038 IMMED_NVC0(push, NVC0_3D(MEM_BARRIER), 0x1011);
1039 nvc0->cb_dirty = false;
1040 }
1041
1042 for (s = 0; s < 5; ++s) {
1043 if (!nvc0->textures_coherent[s])
1044 continue;
1045
1046 PUSH_SPACE(push, nvc0->num_textures[s] * 2);
1047
1048 for (int i = 0; i < nvc0->num_textures[s]; ++i) {
1049 struct nv50_tic_entry *tic = nv50_tic_entry(nvc0->textures[s][i]);
1050 if (!(nvc0->textures_coherent[s] & (1 << i)))
1051 continue;
1052
1053 BEGIN_NVC0(push, NVC0_3D(TEX_CACHE_CTL), 1);
1054 PUSH_DATA (push, (tic->id << 4) | 1);
1055 NOUVEAU_DRV_STAT(&nvc0->screen->base, tex_cache_flush_count, 1);
1056 }
1057 }
1058
1059 if (nvc0->state.vbo_mode) {
1060 if (info->indirect)
1061 nvc0_push_vbo_indirect(nvc0, info);
1062 else
1063 nvc0_push_vbo(nvc0, info);
1064 goto cleanup;
1065 }
1066
1067 /* space for base instance, flush, and prim restart */
1068 PUSH_SPACE(push, 8);
1069
1070 if (nvc0->state.instance_base != info->start_instance) {
1071 nvc0->state.instance_base = info->start_instance;
1072 /* NOTE: this does not affect the shader input, should it ? */
1073 BEGIN_NVC0(push, NVC0_3D(VB_INSTANCE_BASE), 1);
1074 PUSH_DATA (push, info->start_instance);
1075 }
1076
1077 nvc0->base.vbo_dirty |= !!nvc0->vtxbufs_coherent;
1078
1079 if (!nvc0->base.vbo_dirty && info->index_size && !info->has_user_indices &&
1080 info->index.resource->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
1081 nvc0->base.vbo_dirty = true;
1082
1083 nvc0_update_prim_restart(nvc0, info->primitive_restart, info->restart_index);
1084
1085 if (nvc0->base.vbo_dirty) {
1086 if (nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
1087 IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FLUSH), 0);
1088 nvc0->base.vbo_dirty = false;
1089 }
1090
1091 if (unlikely(info->indirect)) {
1092 nvc0_draw_indirect(nvc0, info);
1093 } else
1094 if (unlikely(info->count_from_stream_output)) {
1095 nvc0_draw_stream_output(nvc0, info);
1096 } else
1097 if (info->index_size) {
1098 bool shorten = info->max_index <= 65535;
1099
1100 if (info->primitive_restart && info->restart_index > 65535)
1101 shorten = false;
1102
1103 nvc0_draw_elements(nvc0, shorten, info,
1104 info->mode, info->start, info->count,
1105 info->instance_count, info->index_bias, info->index_size);
1106 } else {
1107 nvc0_draw_arrays(nvc0,
1108 info->mode, info->start, info->count,
1109 info->instance_count);
1110 }
1111
1112 cleanup:
1113 push->kick_notify = nvc0_default_kick_notify;
1114
1115 nvc0_release_user_vbufs(nvc0);
1116
1117 nouveau_pushbuf_bufctx(push, NULL);
1118
1119 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEXT);
1120 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_IDX);
1121 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_BINDLESS);
1122 }