src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #define NVC0_PUSH_EXPLICIT_SPACE_CHECKING
  24
  25 #include "pipe/p_context.h"
  26 #include "pipe/p_state.h"
  27 #include "util/u_inlines.h"
  28 #include "util/u_format.h"
  29 #include "translate/translate.h"
  30
  31 #include "nvc0/nvc0_context.h"
  32 #include "nvc0/nvc0_query_hw.h"
  33 #include "nvc0/nvc0_resource.h"
  34
  35 #include "nvc0/nvc0_3d.xml.h"
  36
  37 void
  38 nvc0_vertex_state_delete(struct pipe_context *pipe,
  39                          void *hwcso)
  40 {
  41    struct nvc0_vertex_stateobj *so = hwcso;
  42
  43    if (so->translate)
  44       so->translate->release(so->translate);
  45    FREE(hwcso);
  46 }
  47
  48 void *
  49 nvc0_vertex_state_create(struct pipe_context *pipe,
  50                          unsigned num_elements,
  51                          const struct pipe_vertex_element *elements)
  52 {
  53     struct nvc0_vertex_stateobj *so;
  54     struct translate_key transkey;
  55     unsigned i;
  56     unsigned src_offset_max = 0;
  57
  58     so = MALLOC(sizeof(*so) +
  59                 num_elements * sizeof(struct nvc0_vertex_element));
  60     if (!so)
  61         return NULL;
  62     so->num_elements = num_elements;
  63     so->instance_elts = 0;
  64     so->instance_bufs = 0;
  65     so->shared_slots = false;
  66     so->need_conversion = false;
  67
  68     memset(so->vb_access_size, 0, sizeof(so->vb_access_size));
  69
  70     for (i = 0; i < PIPE_MAX_ATTRIBS; ++i)
  71        so->min_instance_div[i] = 0xffffffff;
  72
  73     transkey.nr_elements = 0;
  74     transkey.output_stride = 0;
  75
  76     for (i = 0; i < num_elements; ++i) {
  77         const struct pipe_vertex_element *ve = &elements[i];
  78         const unsigned vbi = ve->vertex_buffer_index;
  79         unsigned size;
  80         enum pipe_format fmt = ve->src_format;
  81
  82         so->element[i].pipe = elements[i];
  83         so->element[i].state = nvc0_format_table[fmt].vtx;
  84
  85         if (!so->element[i].state) {
  86             switch (util_format_get_nr_components(fmt)) {
  87             case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
  88             case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
  89             case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
  90             case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
  91             default:
  92                 assert(0);
  93                 FREE(so);
  94                 return NULL;
  95             }
  96             so->element[i].state = nvc0_format_table[fmt].vtx;
  97             so->need_conversion = true;
  98         }
  99         size = util_format_get_blocksize(fmt);
 100
 101         src_offset_max = MAX2(src_offset_max, ve->src_offset);
 102
 103         if (so->vb_access_size[vbi] < (ve->src_offset + size))
 104            so->vb_access_size[vbi] = ve->src_offset + size;
 105
 106         if (unlikely(ve->instance_divisor)) {
 107            so->instance_elts |= 1 << i;
 108            so->instance_bufs |= 1 << vbi;
 109            if (ve->instance_divisor < so->min_instance_div[vbi])
 110               so->min_instance_div[vbi] = ve->instance_divisor;
 111         }
 112
 113         if (1) {
 114             unsigned ca;
 115             unsigned j = transkey.nr_elements++;
 116
 117             ca = util_format_description(fmt)->channel[0].size / 8;
 118             if (ca != 1 && ca != 2)
 119                ca = 4;
 120
 121             transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
 122             transkey.element[j].input_format = ve->src_format;
 123             transkey.element[j].input_buffer = vbi;
 124             transkey.element[j].input_offset = ve->src_offset;
 125             transkey.element[j].instance_divisor = ve->instance_divisor;
 126
 127             transkey.output_stride = align(transkey.output_stride, ca);
 128             transkey.element[j].output_format = fmt;
 129             transkey.element[j].output_offset = transkey.output_stride;
 130             transkey.output_stride += size;
 131
 132             so->element[i].state_alt = so->element[i].state;
 133             so->element[i].state_alt |= transkey.element[j].output_offset << 7;
 134         }
 135
 136         so->element[i].state |= i << NVC0_3D_VERTEX_ATTRIB_FORMAT_BUFFER__SHIFT;
 137     }
 138     transkey.output_stride = align(transkey.output_stride, 4);
 139
 140     so->size = transkey.output_stride;
 141     so->translate = translate_create(&transkey);
 142
 143     if (so->instance_elts || src_offset_max >= (1 << 14))
 144        return so;
 145     so->shared_slots = true;
 146
 147     for (i = 0; i < num_elements; ++i) {
 148        const unsigned b = elements[i].vertex_buffer_index;
 149        const unsigned s = elements[i].src_offset;
 150        so->element[i].state &= ~NVC0_3D_VERTEX_ATTRIB_FORMAT_BUFFER__MASK;
 151        so->element[i].state |= b << NVC0_3D_VERTEX_ATTRIB_FORMAT_BUFFER__SHIFT;
 152        so->element[i].state |= s << NVC0_3D_VERTEX_ATTRIB_FORMAT_OFFSET__SHIFT;
 153     }
 154     return so;
 155 }
 156
 157 #define NVC0_3D_VERTEX_ATTRIB_INACTIVE                                       \
 158    NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT |                                 \
 159    NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32 | NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST
 160
 161 #define VTX_ATTR(a, c, t, s)                            \
 162    ((NVC0_3D_VTX_ATTR_DEFINE_TYPE_##t) |                \
 163     (NVC0_3D_VTX_ATTR_DEFINE_SIZE_##s) |                \
 164     ((a) << NVC0_3D_VTX_ATTR_DEFINE_ATTR__SHIFT) |      \
 165     ((c) << NVC0_3D_VTX_ATTR_DEFINE_COMP__SHIFT))
 166
 167 static void
 168 nvc0_set_constant_vertex_attrib(struct nvc0_context *nvc0, const unsigned a)
 169 {
 170    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 171    struct pipe_vertex_element *ve = &nvc0->vertex->element[a].pipe;
 172    struct pipe_vertex_buffer *vb = &nvc0->vtxbuf[ve->vertex_buffer_index];
 173    uint32_t mode;
 174    const struct util_format_description *desc;
 175    void *dst;
 176    const void *src = (const uint8_t *)vb->user_buffer + ve->src_offset;
 177    assert(!vb->buffer);
 178
 179    desc = util_format_description(ve->src_format);
 180
 181    PUSH_SPACE(push, 6);
 182    BEGIN_NVC0(push, NVC0_3D(VTX_ATTR_DEFINE), 5);
 183    dst = &push->cur[1];
 184    if (desc->channel[0].pure_integer) {
 185       if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED) {
 186          mode = VTX_ATTR(a, 4, SINT, 32);
 187          desc->unpack_rgba_sint(dst, 0, src, 0, 1, 1);
 188       } else {
 189          mode = VTX_ATTR(a, 4, UINT, 32);
 190          desc->unpack_rgba_uint(dst, 0, src, 0, 1, 1);
 191       }
 192    } else {
 193       mode = VTX_ATTR(a, 4, FLOAT, 32);
 194       desc->unpack_rgba_float(dst, 0, src, 0, 1, 1);
 195    }
 196    push->cur[0] = mode;
 197    push->cur += 5;
 198 }
 199
 200 static inline void
 201 nvc0_user_vbuf_range(struct nvc0_context *nvc0, int vbi,
 202                      uint32_t *base, uint32_t *size)
 203 {
 204    if (unlikely(nvc0->vertex->instance_bufs & (1 << vbi))) {
 205       const uint32_t div = nvc0->vertex->min_instance_div[vbi];
 206       *base = nvc0->instance_off * nvc0->vtxbuf[vbi].stride;
 207       *size = (nvc0->instance_max / div) * nvc0->vtxbuf[vbi].stride +
 208          nvc0->vertex->vb_access_size[vbi];
 209    } else {
 210       /* NOTE: if there are user buffers, we *must* have index bounds */
 211       assert(nvc0->vb_elt_limit != ~0);
 212       *base = nvc0->vb_elt_first * nvc0->vtxbuf[vbi].stride;
 213       *size = nvc0->vb_elt_limit * nvc0->vtxbuf[vbi].stride +
 214          nvc0->vertex->vb_access_size[vbi];
 215    }
 216 }
 217
 218 static inline void
 219 nvc0_release_user_vbufs(struct nvc0_context *nvc0)
 220 {
 221    if (nvc0->vbo_user) {
 222       nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_VTX_TMP);
 223       nouveau_scratch_done(&nvc0->base);
 224    }
 225 }
 226
 227 static void
 228 nvc0_update_user_vbufs(struct nvc0_context *nvc0)
 229 {
 230    uint64_t address[PIPE_MAX_ATTRIBS];
 231    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 232    int i;
 233    uint32_t written = 0;
 234
 235    PUSH_SPACE(push, nvc0->vertex->num_elements * 8);
 236    for (i = 0; i < nvc0->vertex->num_elements; ++i) {
 237       struct pipe_vertex_element *ve = &nvc0->vertex->element[i].pipe;
 238       const unsigned b = ve->vertex_buffer_index;
 239       struct pipe_vertex_buffer *vb = &nvc0->vtxbuf[b];
 240       uint32_t base, size;
 241
 242       if (!(nvc0->vbo_user & (1 << b)))
 243          continue;
 244       if (nvc0->constant_vbos & (1 << b)) {
 245          nvc0_set_constant_vertex_attrib(nvc0, i);
 246          continue;
 247       }
 248       nvc0_user_vbuf_range(nvc0, b, &base, &size);
 249
 250       if (!(written & (1 << b))) {
 251          struct nouveau_bo *bo;
 252          const uint32_t bo_flags = NOUVEAU_BO_RD | NOUVEAU_BO_GART;
 253          written |= 1 << b;
 254          address[b] = nouveau_scratch_data(&nvc0->base, vb->user_buffer,
 255                                            base, size, &bo);
 256          if (bo)
 257             BCTX_REFN_bo(nvc0->bufctx_3d, VTX_TMP, bo_flags, bo);
 258
 259          NOUVEAU_DRV_STAT(&nvc0->screen->base, user_buffer_upload_bytes, size);
 260       }
 261
 262       BEGIN_1IC0(push, NVC0_3D(MACRO_VERTEX_ARRAY_SELECT), 5);
 263       PUSH_DATA (push, i);
 264       PUSH_DATAh(push, address[b] + base + size - 1);
 265       PUSH_DATA (push, address[b] + base + size - 1);
 266       PUSH_DATAh(push, address[b] + ve->src_offset);
 267       PUSH_DATA (push, address[b] + ve->src_offset);
 268    }
 269    nvc0->base.vbo_dirty = true;
 270 }
 271
 272 static void
 273 nvc0_update_user_vbufs_shared(struct nvc0_context *nvc0)
 274 {
 275    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 276    uint32_t mask = nvc0->vbo_user & ~nvc0->constant_vbos;
 277
 278    PUSH_SPACE(push, nvc0->num_vtxbufs * 8);
 279    while (mask) {
 280       struct nouveau_bo *bo;
 281       const uint32_t bo_flags = NOUVEAU_BO_RD | NOUVEAU_BO_GART;
 282       uint64_t address;
 283       uint32_t base, size;
 284       const int b = ffs(mask) - 1;
 285       mask &= ~(1 << b);
 286
 287       nvc0_user_vbuf_range(nvc0, b, &base, &size);
 288
 289       address = nouveau_scratch_data(&nvc0->base, nvc0->vtxbuf[b].user_buffer,
 290                                      base, size, &bo);
 291       if (bo)
 292          BCTX_REFN_bo(nvc0->bufctx_3d, VTX_TMP, bo_flags, bo);
 293
 294       BEGIN_1IC0(push, NVC0_3D(MACRO_VERTEX_ARRAY_SELECT), 5);
 295       PUSH_DATA (push, b);
 296       PUSH_DATAh(push, address + base + size - 1);
 297       PUSH_DATA (push, address + base + size - 1);
 298       PUSH_DATAh(push, address);
 299       PUSH_DATA (push, address);
 300
 301       NOUVEAU_DRV_STAT(&nvc0->screen->base, user_buffer_upload_bytes, size);
 302    }
 303
 304    mask = nvc0->state.constant_elts;
 305    while (mask) {
 306       int i = ffs(mask) - 1;
 307       mask &= ~(1 << i);
 308       nvc0_set_constant_vertex_attrib(nvc0, i);
 309    }
 310 }
 311
 312 static void
 313 nvc0_validate_vertex_buffers(struct nvc0_context *nvc0)
 314 {
 315    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 316    const struct nvc0_vertex_stateobj *vertex = nvc0->vertex;
 317    uint32_t refd = 0;
 318    unsigned i;
 319
 320    PUSH_SPACE(push, vertex->num_elements * 8);
 321    for (i = 0; i < vertex->num_elements; ++i) {
 322       const struct nvc0_vertex_element *ve;
 323       const struct pipe_vertex_buffer *vb;
 324       struct nv04_resource *res;
 325       unsigned b;
 326       unsigned limit, offset;
 327
 328       if (nvc0->state.constant_elts & (1 << i))
 329          continue;
 330       ve = &vertex->element[i];
 331       b = ve->pipe.vertex_buffer_index;
 332       vb = &nvc0->vtxbuf[b];
 333
 334       if (!vb->buffer) {
 335          if (!(nvc0->constant_vbos & (1 << b))) {
 336             if (ve->pipe.instance_divisor) {
 337                BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_DIVISOR(i)), 1);
 338                PUSH_DATA (push, ve->pipe.instance_divisor);
 339             }
 340             BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 1);
 341             PUSH_DATA (push, (1 << 12) | vb->stride);
 342          }
 343          /* address/value set in nvc0_update_user_vbufs */
 344          continue;
 345       }
 346       res = nv04_resource(vb->buffer);
 347       offset = ve->pipe.src_offset + vb->buffer_offset;
 348       limit = vb->buffer->width0 - 1;
 349
 350       if (unlikely(ve->pipe.instance_divisor)) {
 351          BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 4);
 352          PUSH_DATA (push, (1 << 12) | vb->stride);
 353          PUSH_DATAh(push, res->address + offset);
 354          PUSH_DATA (push, res->address + offset);
 355          PUSH_DATA (push, ve->pipe.instance_divisor);
 356       } else {
 357          BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 3);
 358          PUSH_DATA (push, (1 << 12) | vb->stride);
 359          PUSH_DATAh(push, res->address + offset);
 360          PUSH_DATA (push, res->address + offset);
 361       }
 362       BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
 363       PUSH_DATAh(push, res->address + limit);
 364       PUSH_DATA (push, res->address + limit);
 365
 366       if (!(refd & (1 << b))) {
 367          refd |= 1 << b;
 368          BCTX_REFN(nvc0->bufctx_3d, VTX, res, RD);
 369       }
 370    }
 371    if (nvc0->vbo_user)
 372       nvc0_update_user_vbufs(nvc0);
 373 }
 374
 375 static void
 376 nvc0_validate_vertex_buffers_shared(struct nvc0_context *nvc0)
 377 {
 378    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 379    unsigned b;
 380    const uint32_t mask = nvc0->vbo_user;
 381
 382    PUSH_SPACE(push, nvc0->num_vtxbufs * 8);
 383    for (b = 0; b < nvc0->num_vtxbufs; ++b) {
 384       struct pipe_vertex_buffer *vb = &nvc0->vtxbuf[b];
 385       struct nv04_resource *buf;
 386       uint32_t offset, limit;
 387
 388       if (mask & (1 << b)) {
 389          if (!(nvc0->constant_vbos & (1 << b))) {
 390             BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(b)), 1);
 391             PUSH_DATA (push, NVC0_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
 392          }
 393          /* address/value set in nvc0_update_user_vbufs_shared */
 394          continue;
 395       }
 396       buf = nv04_resource(vb->buffer);
 397       offset = vb->buffer_offset;
 398       limit = buf->base.width0 - 1;
 399
 400       BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(b)), 3);
 401       PUSH_DATA (push, NVC0_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
 402       PUSH_DATAh(push, buf->address + offset);
 403       PUSH_DATA (push, buf->address + offset);
 404       BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_LIMIT_HIGH(b)), 2);
 405       PUSH_DATAh(push, buf->address + limit);
 406       PUSH_DATA (push, buf->address + limit);
 407
 408       BCTX_REFN(nvc0->bufctx_3d, VTX, buf, RD);
 409    }
 410    if (nvc0->vbo_user)
 411       nvc0_update_user_vbufs_shared(nvc0);
 412 }
 413
 414 void
 415 nvc0_vertex_arrays_validate(struct nvc0_context *nvc0)
 416 {
 417    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 418    struct nvc0_vertex_stateobj *vertex = nvc0->vertex;
 419    struct nvc0_vertex_element *ve;
 420    uint32_t const_vbos;
 421    unsigned i;
 422    uint8_t vbo_mode;
 423    bool update_vertex;
 424
 425    nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_VTX);
 426
 427    assert(vertex);
 428    if (unlikely(vertex->need_conversion) ||
 429        unlikely(nvc0->vertprog->vp.edgeflag < PIPE_MAX_ATTRIBS)) {
 430       vbo_mode = 3;
 431    } else {
 432       vbo_mode = (nvc0->vbo_user && nvc0->vbo_push_hint) ? 1 : 0;
 433    }
 434    const_vbos = vbo_mode ? 0 : nvc0->constant_vbos;
 435
 436    update_vertex = (nvc0->dirty & NVC0_NEW_VERTEX) ||
 437       (const_vbos != nvc0->state.constant_vbos) ||
 438       (vbo_mode != nvc0->state.vbo_mode);
 439
 440    if (update_vertex) {
 441       const unsigned n = MAX2(vertex->num_elements, nvc0->state.num_vtxelts);
 442
 443       nvc0->state.constant_vbos = const_vbos;
 444       nvc0->state.constant_elts = 0;
 445       nvc0->state.num_vtxelts = vertex->num_elements;
 446       nvc0->state.vbo_mode = vbo_mode;
 447
 448       if (unlikely(vbo_mode)) {
 449          if (unlikely(nvc0->state.instance_elts & 3)) {
 450             /* translate mode uses only 2 vertex buffers */
 451             nvc0->state.instance_elts &= ~3;
 452             PUSH_SPACE(push, 3);
 453             BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_PER_INSTANCE(0)), 2);
 454             PUSH_DATA (push, 0);
 455             PUSH_DATA (push, 0);
 456          }
 457
 458          PUSH_SPACE(push, n * 2 + 4);
 459
 460          BEGIN_NVC0(push, NVC0_3D(VERTEX_ATTRIB_FORMAT(0)), n);
 461          for (i = 0; i < vertex->num_elements; ++i)
 462             PUSH_DATA(push, vertex->element[i].state_alt);
 463          for (; i < n; ++i)
 464             PUSH_DATA(push, NVC0_3D_VERTEX_ATTRIB_INACTIVE);
 465
 466          BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(0)), 1);
 467          PUSH_DATA (push, (1 << 12) | vertex->size);
 468          for (i = 1; i < n; ++i)
 469             IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 0);
 470       } else {
 471          uint32_t *restrict data;
 472
 473          if (unlikely(vertex->instance_elts != nvc0->state.instance_elts)) {
 474             nvc0->state.instance_elts = vertex->instance_elts;
 475             assert(n); /* if (n == 0), both masks should be 0 */
 476             PUSH_SPACE(push, 3);
 477             BEGIN_NVC0(push, NVC0_3D(MACRO_VERTEX_ARRAY_PER_INSTANCE), 2);
 478             PUSH_DATA (push, n);
 479             PUSH_DATA (push, vertex->instance_elts);
 480          }
 481
 482          PUSH_SPACE(push, n * 2 + 1);
 483          BEGIN_NVC0(push, NVC0_3D(VERTEX_ATTRIB_FORMAT(0)), n);
 484          data = push->cur;
 485          push->cur += n;
 486          for (i = 0; i < vertex->num_elements; ++i) {
 487             ve = &vertex->element[i];
 488             data[i] = ve->state;
 489             if (unlikely(const_vbos & (1 << ve->pipe.vertex_buffer_index))) {
 490                nvc0->state.constant_elts |= 1 << i;
 491                data[i] |= NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST;
 492                IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 0);
 493             }
 494          }
 495          for (; i < n; ++i) {
 496             data[i] = NVC0_3D_VERTEX_ATTRIB_INACTIVE;
 497             IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 0);
 498          }
 499       }
 500    }
 501    if (nvc0->state.vbo_mode) /* using translate, don't set up arrays here */
 502       return;
 503
 504    if (vertex->shared_slots)
 505       nvc0_validate_vertex_buffers_shared(nvc0);
 506    else
 507       nvc0_validate_vertex_buffers(nvc0);
 508 }
 509
 510 void
 511 nvc0_idxbuf_validate(struct nvc0_context *nvc0)
 512 {
 513    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 514    struct nv04_resource *buf = nv04_resource(nvc0->idxbuf.buffer);
 515
 516    assert(buf);
 517    assert(nouveau_resource_mapped_by_gpu(&buf->base));
 518
 519    PUSH_SPACE(push, 6);
 520    BEGIN_NVC0(push, NVC0_3D(INDEX_ARRAY_START_HIGH), 5);
 521    PUSH_DATAh(push, buf->address + nvc0->idxbuf.offset);
 522    PUSH_DATA (push, buf->address + nvc0->idxbuf.offset);
 523    PUSH_DATAh(push, buf->address + buf->base.width0 - 1);
 524    PUSH_DATA (push, buf->address + buf->base.width0 - 1);
 525    PUSH_DATA (push, nvc0->idxbuf.index_size >> 1);
 526
 527    BCTX_REFN(nvc0->bufctx_3d, IDX, buf, RD);
 528 }
 529
 530 #define NVC0_PRIM_GL_CASE(n) \
 531    case PIPE_PRIM_##n: return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
 532
 533 static inline unsigned
 534 nvc0_prim_gl(unsigned prim)
 535 {
 536    switch (prim) {
 537    NVC0_PRIM_GL_CASE(POINTS);
 538    NVC0_PRIM_GL_CASE(LINES);
 539    NVC0_PRIM_GL_CASE(LINE_LOOP);
 540    NVC0_PRIM_GL_CASE(LINE_STRIP);
 541    NVC0_PRIM_GL_CASE(TRIANGLES);
 542    NVC0_PRIM_GL_CASE(TRIANGLE_STRIP);
 543    NVC0_PRIM_GL_CASE(TRIANGLE_FAN);
 544    NVC0_PRIM_GL_CASE(QUADS);
 545    NVC0_PRIM_GL_CASE(QUAD_STRIP);
 546    NVC0_PRIM_GL_CASE(POLYGON);
 547    NVC0_PRIM_GL_CASE(LINES_ADJACENCY);
 548    NVC0_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
 549    NVC0_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
 550    NVC0_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
 551    NVC0_PRIM_GL_CASE(PATCHES);
 552    default:
 553       return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
 554    }
 555 }
 556
 557 static void
 558 nvc0_draw_vbo_kick_notify(struct nouveau_pushbuf *push)
 559 {
 560    struct nvc0_screen *screen = push->user_priv;
 561
 562    nouveau_fence_update(&screen->base, true);
 563
 564    NOUVEAU_DRV_STAT(&screen->base, pushbuf_count, 1);
 565 }
 566
 567 static void
 568 nvc0_draw_arrays(struct nvc0_context *nvc0,
 569                  unsigned mode, unsigned start, unsigned count,
 570                  unsigned instance_count)
 571 {
 572    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 573    unsigned prim;
 574
 575    if (nvc0->state.index_bias) {
 576       /* index_bias is implied 0 if !info->indexed (really ?) */
 577       /* TODO: can we deactivate it for the VERTEX_BUFFER_FIRST command ? */
 578       PUSH_SPACE(push, 2);
 579       IMMED_NVC0(push, NVC0_3D(VB_ELEMENT_BASE), 0);
 580       IMMED_NVC0(push, NVC0_3D(VERTEX_ID_BASE), 0);
 581       nvc0->state.index_bias = 0;
 582    }
 583
 584    prim = nvc0_prim_gl(mode);
 585
 586    while (instance_count--) {
 587       PUSH_SPACE(push, 6);
 588       BEGIN_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), 1);
 589       PUSH_DATA (push, prim);
 590       BEGIN_NVC0(push, NVC0_3D(VERTEX_BUFFER_FIRST), 2);
 591       PUSH_DATA (push, start);
 592       PUSH_DATA (push, count);
 593       IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
 594
 595       prim |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 596    }
 597    NOUVEAU_DRV_STAT(&nvc0->screen->base, draw_calls_array, 1);
 598 }
 599
 600 static void
 601 nvc0_draw_elements_inline_u08(struct nouveau_pushbuf *push, const uint8_t *map,
 602                               unsigned start, unsigned count)
 603 {
 604    map += start;
 605
 606    if (count & 3) {
 607       unsigned i;
 608       PUSH_SPACE(push, 4);
 609       BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U32), count & 3);
 610       for (i = 0; i < (count & 3); ++i)
 611          PUSH_DATA(push, *map++);
 612       count &= ~3;
 613    }
 614    while (count) {
 615       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4;
 616
 617       PUSH_SPACE(push, nr + 1);
 618       BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U8), nr);
 619       for (i = 0; i < nr; ++i) {
 620          PUSH_DATA(push,
 621                   (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]);
 622          map += 4;
 623       }
 624       count -= nr * 4;
 625    }
 626 }
 627
 628 static void
 629 nvc0_draw_elements_inline_u16(struct nouveau_pushbuf *push, const uint16_t *map,
 630                               unsigned start, unsigned count)
 631 {
 632    map += start;
 633
 634    if (count & 1) {
 635       count &= ~1;
 636       PUSH_SPACE(push, 2);
 637       BEGIN_NVC0(push, NVC0_3D(VB_ELEMENT_U32), 1);
 638       PUSH_DATA (push, *map++);
 639    }
 640    while (count) {
 641       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
 642
 643       PUSH_SPACE(push, nr + 1);
 644       BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U16), nr);
 645       for (i = 0; i < nr; ++i) {
 646          PUSH_DATA(push, (map[1] << 16) | map[0]);
 647          map += 2;
 648       }
 649       count -= nr * 2;
 650    }
 651 }
 652
 653 static void
 654 nvc0_draw_elements_inline_u32(struct nouveau_pushbuf *push, const uint32_t *map,
 655                               unsigned start, unsigned count)
 656 {
 657    map += start;
 658
 659    while (count) {
 660       const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
 661
 662       PUSH_SPACE(push, nr + 1);
 663       BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U32), nr);
 664       PUSH_DATAp(push, map, nr);
 665
 666       map += nr;
 667       count -= nr;
 668    }
 669 }
 670
 671 static void
 672 nvc0_draw_elements_inline_u32_short(struct nouveau_pushbuf *push,
 673                                     const uint32_t *map,
 674                                     unsigned start, unsigned count)
 675 {
 676    map += start;
 677
 678    if (count & 1) {
 679       count--;
 680       PUSH_SPACE(push, 1);
 681       BEGIN_NVC0(push, NVC0_3D(VB_ELEMENT_U32), 1);
 682       PUSH_DATA (push, *map++);
 683    }
 684    while (count) {
 685       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
 686
 687       PUSH_SPACE(push, nr + 1);
 688       BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U16), nr);
 689       for (i = 0; i < nr; ++i) {
 690          PUSH_DATA(push, (map[1] << 16) | map[0]);
 691          map += 2;
 692       }
 693       count -= nr * 2;
 694    }
 695 }
 696
 697 static void
 698 nvc0_draw_elements(struct nvc0_context *nvc0, bool shorten,
 699                    unsigned mode, unsigned start, unsigned count,
 700                    unsigned instance_count, int32_t index_bias)
 701 {
 702    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 703    unsigned prim;
 704    const unsigned index_size = nvc0->idxbuf.index_size;
 705
 706    prim = nvc0_prim_gl(mode);
 707
 708    if (index_bias != nvc0->state.index_bias) {
 709       PUSH_SPACE(push, 4);
 710       BEGIN_NVC0(push, NVC0_3D(VB_ELEMENT_BASE), 1);
 711       PUSH_DATA (push, index_bias);
 712       BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_BASE), 1);
 713       PUSH_DATA (push, index_bias);
 714       nvc0->state.index_bias = index_bias;
 715    }
 716
 717    if (nvc0->idxbuf.buffer) {
 718       PUSH_SPACE(push, 1);
 719       IMMED_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), prim);
 720       do {
 721          PUSH_SPACE(push, 7);
 722          BEGIN_NVC0(push, NVC0_3D(INDEX_BATCH_FIRST), 2);
 723          PUSH_DATA (push, start);
 724          PUSH_DATA (push, count);
 725          if (--instance_count) {
 726             BEGIN_NVC0(push, NVC0_3D(VERTEX_END_GL), 2);
 727             PUSH_DATA (push, 0);
 728             PUSH_DATA (push, prim | NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT);
 729          }
 730       } while (instance_count);
 731       IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
 732    } else {
 733       const void *data = nvc0->idxbuf.user_buffer;
 734
 735       while (instance_count--) {
 736          PUSH_SPACE(push, 2);
 737          BEGIN_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), 1);
 738          PUSH_DATA (push, prim);
 739          switch (index_size) {
 740          case 1:
 741             nvc0_draw_elements_inline_u08(push, data, start, count);
 742             break;
 743          case 2:
 744             nvc0_draw_elements_inline_u16(push, data, start, count);
 745             break;
 746          case 4:
 747             if (shorten)
 748                nvc0_draw_elements_inline_u32_short(push, data, start, count);
 749             else
 750                nvc0_draw_elements_inline_u32(push, data, start, count);
 751             break;
 752          default:
 753             assert(0);
 754             return;
 755          }
 756          PUSH_SPACE(push, 1);
 757          IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
 758
 759          prim |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 760       }
 761    }
 762    NOUVEAU_DRV_STAT(&nvc0->screen->base, draw_calls_indexed, 1);
 763 }
 764
 765 static void
 766 nvc0_draw_stream_output(struct nvc0_context *nvc0,
 767                         const struct pipe_draw_info *info)
 768 {
 769    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 770    struct nvc0_so_target *so = nvc0_so_target(info->count_from_stream_output);
 771    struct nv04_resource *res = nv04_resource(so->pipe.buffer);
 772    unsigned mode = nvc0_prim_gl(info->mode);
 773    unsigned num_instances = info->instance_count;
 774
 775    if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
 776       res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
 777       PUSH_SPACE(push, 2);
 778       IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
 779       nvc0_hw_query_fifo_wait(push, nvc0_query(so->pq));
 780       if (nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
 781          IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FLUSH), 0);
 782
 783       NOUVEAU_DRV_STAT(&nvc0->screen->base, gpu_serialize_count, 1);
 784    }
 785
 786    while (num_instances--) {
 787       PUSH_SPACE(push, 8);
 788       BEGIN_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), 1);
 789       PUSH_DATA (push, mode);
 790       BEGIN_NVC0(push, NVC0_3D(DRAW_TFB_BASE), 1);
 791       PUSH_DATA (push, 0);
 792       BEGIN_NVC0(push, NVC0_3D(DRAW_TFB_STRIDE), 1);
 793       PUSH_DATA (push, so->stride);
 794       BEGIN_NVC0(push, NVC0_3D(DRAW_TFB_BYTES), 1);
 795       nvc0_hw_query_pushbuf_submit(push, nvc0_query(so->pq), 0x4);
 796       IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
 797
 798       mode |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 799    }
 800 }
 801
 802 static void
 803 nvc0_draw_indirect(struct nvc0_context *nvc0, const struct pipe_draw_info *info)
 804 {
 805    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 806    struct nv04_resource *buf = nv04_resource(info->indirect);
 807    unsigned size;
 808    const uint32_t offset = buf->offset + info->indirect_offset;
 809
 810    /* must make FIFO wait for engines idle before continuing to process */
 811    if (buf->fence_wr && !nouveau_fence_signalled(buf->fence_wr))
 812       IMMED_NVC0(push, SUBC_3D(NV10_SUBCHAN_REF_CNT), 0);
 813
 814    PUSH_SPACE(push, 8);
 815    if (info->indexed) {
 816       assert(nvc0->idxbuf.buffer);
 817       assert(nouveau_resource_mapped_by_gpu(nvc0->idxbuf.buffer));
 818       size = 5 * 4;
 819       BEGIN_1IC0(push, NVC0_3D(MACRO_DRAW_ELEMENTS_INDIRECT), 1 + size / 4);
 820    } else {
 821       if (nvc0->state.index_bias) {
 822          /* index_bias is implied 0 if !info->indexed (really ?) */
 823          IMMED_NVC0(push, NVC0_3D(VB_ELEMENT_BASE), 0);
 824          IMMED_NVC0(push, NVC0_3D(VERTEX_ID_BASE), 0);
 825          nvc0->state.index_bias = 0;
 826       }
 827       size = 4 * 4;
 828       BEGIN_1IC0(push, NVC0_3D(MACRO_DRAW_ARRAYS_INDIRECT), 1 + size / 4);
 829    }
 830    PUSH_DATA(push, nvc0_prim_gl(info->mode));
 831 #define NVC0_IB_ENTRY_1_NO_PREFETCH (1 << (31 - 8))
 832    PUSH_REFN(push, buf->bo, NOUVEAU_BO_RD | buf->domain);
 833    nouveau_pushbuf_space(push, 0, 0, 1);
 834    nouveau_pushbuf_data(push,
 835                         buf->bo, offset, NVC0_IB_ENTRY_1_NO_PREFETCH | size);
 836 }
 837
 838 static inline void
 839 nvc0_update_prim_restart(struct nvc0_context *nvc0, bool en, uint32_t index)
 840 {
 841    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 842
 843    if (en != nvc0->state.prim_restart) {
 844       if (en) {
 845          BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_ENABLE), 2);
 846          PUSH_DATA (push, 1);
 847          PUSH_DATA (push, index);
 848       } else {
 849          IMMED_NVC0(push, NVC0_3D(PRIM_RESTART_ENABLE), 0);
 850       }
 851       nvc0->state.prim_restart = en;
 852    } else
 853    if (en) {
 854       BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_INDEX), 1);
 855       PUSH_DATA (push, index);
 856    }
 857 }
 858
 859 void
 860 nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 861 {
 862    struct nvc0_context *nvc0 = nvc0_context(pipe);
 863    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 864    int i, s;
 865
 866    /* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */
 867    nvc0->vb_elt_first = info->min_index + info->index_bias;
 868    nvc0->vb_elt_limit = info->max_index - info->min_index;
 869    nvc0->instance_off = info->start_instance;
 870    nvc0->instance_max = info->instance_count - 1;
 871
 872    /* For picking only a few vertices from a large user buffer, push is better,
 873     * if index count is larger and we expect repeated vertices, suggest upload.
 874     */
 875    nvc0->vbo_push_hint =
 876       info->indexed && (nvc0->vb_elt_limit >= (info->count * 2));
 877
 878    /* Check whether we want to switch vertex-submission mode. */
 879    if (nvc0->vbo_user && !(nvc0->dirty & (NVC0_NEW_ARRAYS | NVC0_NEW_VERTEX))) {
 880       if (nvc0->vbo_push_hint != !!nvc0->state.vbo_mode)
 881          if (nvc0->state.vbo_mode != 3)
 882             nvc0->dirty |= NVC0_NEW_ARRAYS;
 883
 884       if (!(nvc0->dirty & NVC0_NEW_ARRAYS) && nvc0->state.vbo_mode == 0) {
 885          if (nvc0->vertex->shared_slots)
 886             nvc0_update_user_vbufs_shared(nvc0);
 887          else
 888             nvc0_update_user_vbufs(nvc0);
 889       }
 890    }
 891
 892    if (info->mode == PIPE_PRIM_PATCHES &&
 893        nvc0->state.patch_vertices != info->vertices_per_patch) {
 894       nvc0->state.patch_vertices = info->vertices_per_patch;
 895       IMMED_NVC0(push, NVC0_3D(PATCH_VERTICES), nvc0->state.patch_vertices);
 896    }
 897
 898    /* 8 as minimum to avoid immediate double validation of new buffers */
 899    nvc0_state_validate(nvc0, ~0, 8);
 900
 901    push->kick_notify = nvc0_draw_vbo_kick_notify;
 902
 903    /* TODO: Instead of iterating over all the buffer resources looking for
 904     * coherent buffers, keep track of a context-wide count.
 905     */
 906    for (s = 0; s < 5 && !nvc0->cb_dirty; ++s) {
 907       uint32_t valid = nvc0->constbuf_valid[s];
 908
 909       while (valid && !nvc0->cb_dirty) {
 910          const unsigned i = ffs(valid) - 1;
 911          struct pipe_resource *res;
 912
 913          valid &= ~(1 << i);
 914          if (nvc0->constbuf[s][i].user)
 915             continue;
 916
 917          res = nvc0->constbuf[s][i].u.buf;
 918          if (!res)
 919             continue;
 920
 921          if (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
 922             nvc0->cb_dirty = true;
 923       }
 924    }
 925
 926    if (nvc0->cb_dirty) {
 927       IMMED_NVC0(push, NVC0_3D(MEM_BARRIER), 0x1011);
 928       nvc0->cb_dirty = false;
 929    }
 930
 931    for (s = 0; s < 5; ++s) {
 932       for (int i = 0; i < nvc0->num_textures[s]; ++i) {
 933          struct nv50_tic_entry *tic = nv50_tic_entry(nvc0->textures[s][i]);
 934          struct pipe_resource *res;
 935          if (!tic)
 936             continue;
 937          res = nvc0->textures[s][i]->texture;
 938          if (res->target != PIPE_BUFFER ||
 939              !(res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
 940             continue;
 941
 942          BEGIN_NVC0(push, NVC0_3D(TEX_CACHE_CTL), 1);
 943          PUSH_DATA (push, (tic->id << 4) | 1);
 944          NOUVEAU_DRV_STAT(&nvc0->screen->base, tex_cache_flush_count, 1);
 945       }
 946    }
 947
 948    if (nvc0->state.vbo_mode) {
 949       nvc0_push_vbo(nvc0, info);
 950       push->kick_notify = nvc0_default_kick_notify;
 951       nouveau_pushbuf_bufctx(push, NULL);
 952       return;
 953    }
 954
 955    /* space for base instance, flush, and prim restart */
 956    PUSH_SPACE(push, 8);
 957
 958    if (nvc0->state.instance_base != info->start_instance) {
 959       nvc0->state.instance_base = info->start_instance;
 960       /* NOTE: this does not affect the shader input, should it ? */
 961       BEGIN_NVC0(push, NVC0_3D(VB_INSTANCE_BASE), 1);
 962       PUSH_DATA (push, info->start_instance);
 963    }
 964
 965    for (i = 0; i < nvc0->num_vtxbufs && !nvc0->base.vbo_dirty; ++i) {
 966       if (!nvc0->vtxbuf[i].buffer)
 967          continue;
 968       if (nvc0->vtxbuf[i].buffer->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
 969          nvc0->base.vbo_dirty = true;
 970    }
 971
 972    if (!nvc0->base.vbo_dirty && nvc0->idxbuf.buffer &&
 973        nvc0->idxbuf.buffer->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
 974       nvc0->base.vbo_dirty = true;
 975
 976    nvc0_update_prim_restart(nvc0, info->primitive_restart, info->restart_index);
 977
 978    if (nvc0->base.vbo_dirty) {
 979       if (nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
 980          IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FLUSH), 0);
 981       nvc0->base.vbo_dirty = false;
 982    }
 983
 984    if (unlikely(info->indirect)) {
 985       nvc0_draw_indirect(nvc0, info);
 986    } else
 987    if (unlikely(info->count_from_stream_output)) {
 988       nvc0_draw_stream_output(nvc0, info);
 989    } else
 990    if (info->indexed) {
 991       bool shorten = info->max_index <= 65535;
 992
 993       if (info->primitive_restart && info->restart_index > 65535)
 994          shorten = false;
 995
 996       nvc0_draw_elements(nvc0, shorten,
 997                          info->mode, info->start, info->count,
 998                          info->instance_count, info->index_bias);
 999    } else {
1000       nvc0_draw_arrays(nvc0,
1001                        info->mode, info->start, info->count,
1002                        info->instance_count);
1003    }
1004    push->kick_notify = nvc0_default_kick_notify;
1005
1006    nvc0_release_user_vbufs(nvc0);
1007
1008    nouveau_pushbuf_bufctx(push, NULL);
1009 }