src/gallium/drivers/nouveau/nvc0/nvc0_video_bsp.c

   1 /*
   2  * Copyright 2011-2013 Maarten Lankhorst
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "nvc0/nvc0_video.h"
  24
  25 #if NOUVEAU_VP3_DEBUG_FENCE
  26 static void dump_comm_bsp(struct comm *comm)
  27 {
  28    unsigned idx = comm->bsp_cur_index & 0xf;
  29    debug_printf("Cur seq: %x, bsp byte ofs: %x\n", comm->bsp_cur_index, comm->byte_ofs);
  30    debug_printf("Status: %08x, pos: %08x\n", comm->status[idx], comm->pos[idx]);
  31 }
  32 #endif
  33
  34 unsigned
  35 nvc0_decoder_bsp_begin(struct nouveau_vp3_decoder *dec, unsigned comm_seq)
  36 {
  37    struct nouveau_bo *bsp_bo = dec->bsp_bo[comm_seq % NOUVEAU_VP3_VIDEO_QDEPTH];
  38    unsigned ret = 0;
  39
  40    ret = nouveau_bo_map(bsp_bo, NOUVEAU_BO_WR, dec->client);
  41    if (ret) {
  42       debug_printf("map failed: %i %s\n", ret, strerror(-ret));
  43       return -1;
  44    }
  45
  46    nouveau_vp3_bsp_begin(dec);
  47
  48    return 2;
  49 }
  50
  51 unsigned
  52 nvc0_decoder_bsp_next(struct nouveau_vp3_decoder *dec,
  53                       unsigned comm_seq, unsigned num_buffers,
  54                       const void *const *data, const unsigned *num_bytes)
  55 {
  56    struct nouveau_bo *bsp_bo = dec->bsp_bo[comm_seq % NOUVEAU_VP3_VIDEO_QDEPTH];
  57    struct nouveau_bo *inter_bo = dec->inter_bo[comm_seq & 1];
  58    uint32_t bsp_size = 0;
  59    uint32_t i = 0;
  60    unsigned ret = 0;
  61
  62    bsp_size = dec->bsp_ptr - (char *)bsp_bo->map;
  63    for (i = 0; i < num_buffers; i++)
  64       bsp_size += num_bytes[i];
  65    bsp_size += 256; /* the 4 end markers */
  66
  67    if (bsp_size > bsp_bo->size) {
  68       union nouveau_bo_config cfg;
  69       struct nouveau_bo *tmp_bo = NULL;
  70
  71       cfg.nvc0.tile_mode = 0x10;
  72       cfg.nvc0.memtype = 0xfe;
  73
  74       /* round up to the nearest mb */
  75       bsp_size += (1 << 20) - 1;
  76       bsp_size &= ~((1 << 20) - 1);
  77
  78       ret = nouveau_bo_new(dec->client->device, NOUVEAU_BO_VRAM, 0, bsp_size, &cfg, &tmp_bo);
  79       if (ret) {
  80          debug_printf("reallocating bsp %u -> %u failed with %i\n",
  81                       bsp_bo ? (unsigned)bsp_bo->size : 0, bsp_size, ret);
  82          return -1;
  83       }
  84
  85       ret = nouveau_bo_map(tmp_bo, NOUVEAU_BO_WR, dec->client);
  86       if (ret) {
  87          debug_printf("map failed: %i %s\n", ret, strerror(-ret));
  88          return -1;
  89       }
  90
  91       /* Preserve previous buffer. */
  92       /* TODO: offload this copy to the GPU, as otherwise we're reading and
  93        * writing to VRAM. */
  94       memcpy(tmp_bo->map, bsp_bo->map, bsp_bo->size);
  95
  96       /* update position to current chunk */
  97       dec->bsp_ptr = tmp_bo->map + (dec->bsp_ptr - (char *)bsp_bo->map);
  98
  99       nouveau_bo_ref(NULL, &bsp_bo);
 100       dec->bsp_bo[comm_seq % NOUVEAU_VP3_VIDEO_QDEPTH] = bsp_bo = tmp_bo;
 101    }
 102
 103    if (!inter_bo || bsp_bo->size * 4 > inter_bo->size) {
 104       union nouveau_bo_config cfg;
 105       struct nouveau_bo *tmp_bo = NULL;
 106
 107       cfg.nvc0.tile_mode = 0x10;
 108       cfg.nvc0.memtype = 0xfe;
 109
 110       ret = nouveau_bo_new(dec->client->device, NOUVEAU_BO_VRAM, 0, bsp_bo->size * 4, &cfg, &tmp_bo);
 111       if (ret) {
 112          debug_printf("reallocating inter %u -> %u failed with %i\n",
 113                       inter_bo ? (unsigned)inter_bo->size : 0, (unsigned)bsp_bo->size * 4, ret);
 114          return -1;
 115       }
 116
 117       ret = nouveau_bo_map(tmp_bo, NOUVEAU_BO_WR, dec->client);
 118       if (ret) {
 119          debug_printf("map failed: %i %s\n", ret, strerror(-ret));
 120          return -1;
 121       }
 122
 123       nouveau_bo_ref(NULL, &inter_bo);
 124       dec->inter_bo[comm_seq & 1] = inter_bo = tmp_bo;
 125    }
 126
 127    nouveau_vp3_bsp_next(dec, num_buffers, data, num_bytes);
 128
 129    return 2;
 130 }
 131
 132
 133 unsigned
 134 nvc0_decoder_bsp_end(struct nouveau_vp3_decoder *dec, union pipe_desc desc,
 135                      struct nouveau_vp3_video_buffer *target, unsigned comm_seq,
 136                      unsigned *vp_caps, unsigned *is_ref,
 137                      struct nouveau_vp3_video_buffer *refs[16])
 138 {
 139    struct nouveau_pushbuf *push = dec->pushbuf[0];
 140    enum pipe_video_format codec = u_reduce_video_profile(dec->base.profile);
 141    uint32_t bsp_addr, comm_addr, inter_addr;
 142    uint32_t slice_size, bucket_size, ring_size;
 143    uint32_t caps;
 144    struct nouveau_bo *bsp_bo = dec->bsp_bo[comm_seq % NOUVEAU_VP3_VIDEO_QDEPTH];
 145    struct nouveau_bo *inter_bo = dec->inter_bo[comm_seq & 1];
 146    struct nouveau_pushbuf_refn bo_refs[] = {
 147       { bsp_bo, NOUVEAU_BO_RD | NOUVEAU_BO_VRAM },
 148       { inter_bo, NOUVEAU_BO_WR | NOUVEAU_BO_VRAM },
 149 #if NOUVEAU_VP3_DEBUG_FENCE
 150       { dec->fence_bo, NOUVEAU_BO_WR | NOUVEAU_BO_GART },
 151 #endif
 152       { dec->bitplane_bo, NOUVEAU_BO_RDWR | NOUVEAU_BO_VRAM },
 153    };
 154    int num_refs = ARRAY_SIZE(bo_refs);
 155
 156    if (!dec->bitplane_bo)
 157       num_refs--;
 158
 159    caps = nouveau_vp3_bsp_end(dec, desc);
 160
 161    nouveau_vp3_vp_caps(dec, desc, target, comm_seq, vp_caps, is_ref, refs);
 162
 163    nouveau_pushbuf_space(push, 32, num_refs, 0);
 164    nouveau_pushbuf_refn(push, bo_refs, num_refs);
 165
 166    bsp_addr = bsp_bo->offset >> 8;
 167    inter_addr = inter_bo->offset >> 8;
 168
 169 #if NOUVEAU_VP3_DEBUG_FENCE
 170    memset(dec->comm, 0, 0x200);
 171    comm_addr = (dec->fence_bo->offset + COMM_OFFSET) >> 8;
 172 #else
 173    comm_addr = bsp_addr + (COMM_OFFSET>>8);
 174 #endif
 175
 176    BEGIN_NVC0(push, SUBC_BSP(0x700), 5);
 177    PUSH_DATA (push, caps); // 700 cmd
 178    PUSH_DATA (push, bsp_addr + 1); // 704 strparm_bsp
 179    PUSH_DATA (push, bsp_addr + 7); // 708 str addr
 180    PUSH_DATA (push, comm_addr); // 70c comm
 181    PUSH_DATA (push, comm_seq); // 710 seq
 182
 183    if (codec != PIPE_VIDEO_FORMAT_MPEG4_AVC) {
 184       u32 bitplane_addr;
 185
 186       bitplane_addr = dec->bitplane_bo->offset >> 8;
 187
 188       nouveau_vp3_inter_sizes(dec, 1, &slice_size, &bucket_size, &ring_size);
 189       BEGIN_NVC0(push, SUBC_BSP(0x400), 6);
 190       PUSH_DATA (push, bsp_addr); // 400 picparm addr
 191       PUSH_DATA (push, inter_addr); // 404 interparm addr
 192       PUSH_DATA (push, inter_addr + slice_size + bucket_size); // 408 interdata addr
 193       PUSH_DATA (push, ring_size << 8); // 40c interdata_size
 194       PUSH_DATA (push, bitplane_addr); // 410 BITPLANE_DATA
 195       PUSH_DATA (push, 0x400); // 414 BITPLANE_DATA_SIZE
 196    } else {
 197       nouveau_vp3_inter_sizes(dec, desc.h264->slice_count, &slice_size, &bucket_size, &ring_size);
 198       BEGIN_NVC0(push, SUBC_BSP(0x400), 8);
 199       PUSH_DATA (push, bsp_addr); // 400 picparm addr
 200       PUSH_DATA (push, inter_addr); // 404 interparm addr
 201       PUSH_DATA (push, slice_size << 8); // 408 interparm size?
 202       PUSH_DATA (push, inter_addr + slice_size + bucket_size); // 40c interdata addr
 203       PUSH_DATA (push, ring_size << 8); // 410 interdata size
 204       PUSH_DATA (push, inter_addr + slice_size); // 414 bucket?
 205       PUSH_DATA (push, bucket_size << 8); // 418 bucket size? unshifted..
 206       PUSH_DATA (push, 0); // 41c targets
 207       // TODO: Double check 414 / 418 with nvidia trace
 208    }
 209
 210 #if NOUVEAU_VP3_DEBUG_FENCE
 211    BEGIN_NVC0(push, SUBC_BSP(0x240), 3);
 212    PUSH_DATAh(push, dec->fence_bo->offset);
 213    PUSH_DATA (push, dec->fence_bo->offset);
 214    PUSH_DATA (push, dec->fence_seq);
 215
 216    BEGIN_NVC0(push, SUBC_BSP(0x300), 1);
 217    PUSH_DATA (push, 1);
 218    PUSH_KICK (push);
 219
 220    {
 221       unsigned spin = 0;
 222       do {
 223          usleep(100);
 224          if ((spin++ & 0xff) == 0xff) {
 225             debug_printf("b%u: %u\n", dec->fence_seq, dec->fence_map[0]);
 226             dump_comm_bsp(dec->comm);
 227          }
 228       } while (dec->fence_seq > dec->fence_map[0]);
 229    }
 230
 231    dump_comm_bsp(dec->comm);
 232    return dec->comm->status[comm_seq & 0xf];
 233 #else
 234    BEGIN_NVC0(push, SUBC_BSP(0x300), 1);
 235    PUSH_DATA (push, 0);
 236    PUSH_KICK (push);
 237    return 2;
 238 #endif
 239 }