src/gallium/drivers/nouveau/nvc0/nve4_compute.c

   1 /*
   2  * Copyright 2012 Nouveau Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Christoph Bumiller
  23  */
  24
  25 #include "nvc0/nvc0_context.h"
  26 #include "nvc0/nvc0_compute.h"
  27 #include "nvc0/nve4_compute.h"
  28
  29 #include "codegen/nv50_ir_driver.h"
  30
  31 #ifdef DEBUG
  32 static void nve4_compute_dump_launch_desc(const struct nve4_cp_launch_desc *);
  33 #endif
  34
  35
  36 int
  37 nve4_screen_compute_setup(struct nvc0_screen *screen,
  38                           struct nouveau_pushbuf *push)
  39 {
  40    struct nouveau_device *dev = screen->base.device;
  41    struct nouveau_object *chan = screen->base.channel;
  42    int i;
  43    int ret;
  44    uint32_t obj_class;
  45
  46    switch (dev->chipset & ~0xf) {
  47    case 0x100:
  48    case 0xf0:
  49       obj_class = NVF0_COMPUTE_CLASS; /* GK110 */
  50       break;
  51    case 0xe0:
  52       obj_class = NVE4_COMPUTE_CLASS; /* GK104 */
  53       break;
  54    case 0x110:
  55       obj_class = GM107_COMPUTE_CLASS;
  56       break;
  57    default:
  58       NOUVEAU_ERR("unsupported chipset: NV%02x\n", dev->chipset);
  59       return -1;
  60    }
  61
  62    ret = nouveau_object_new(chan, 0xbeef00c0, obj_class, NULL, 0,
  63                             &screen->compute);
  64    if (ret) {
  65       NOUVEAU_ERR("Failed to allocate compute object: %d\n", ret);
  66       return ret;
  67    }
  68
  69    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 0, NVE4_CP_PARAM_SIZE, NULL,
  70                         &screen->parm);
  71    if (ret)
  72       return ret;
  73
  74    BEGIN_NVC0(push, SUBC_COMPUTE(NV01_SUBCHAN_OBJECT), 1);
  75    PUSH_DATA (push, screen->compute->oclass);
  76
  77    BEGIN_NVC0(push, NVE4_COMPUTE(TEMP_ADDRESS_HIGH), 2);
  78    PUSH_DATAh(push, screen->tls->offset);
  79    PUSH_DATA (push, screen->tls->offset);
  80    /* No idea why there are 2. Divide size by 2 to be safe.
  81     * Actually this might be per-MP TEMP size and looks like I'm only using
  82     * 2 MPs instead of all 8.
  83     */
  84    BEGIN_NVC0(push, NVE4_COMPUTE(MP_TEMP_SIZE_HIGH(0)), 3);
  85    PUSH_DATAh(push, screen->tls->size / screen->mp_count);
  86    PUSH_DATA (push, (screen->tls->size / screen->mp_count) & ~0x7fff);
  87    PUSH_DATA (push, 0xff);
  88    BEGIN_NVC0(push, NVE4_COMPUTE(MP_TEMP_SIZE_HIGH(1)), 3);
  89    PUSH_DATAh(push, screen->tls->size / screen->mp_count);
  90    PUSH_DATA (push, (screen->tls->size / screen->mp_count) & ~0x7fff);
  91    PUSH_DATA (push, 0xff);
  92
  93    /* Unified address space ? Who needs that ? Certainly not OpenCL.
  94     *
  95     * FATAL: Buffers with addresses inside [0x1000000, 0x3000000] will NOT be
  96     *  accessible. We cannot prevent that at the moment, so expect failure.
  97     */
  98    BEGIN_NVC0(push, NVE4_COMPUTE(LOCAL_BASE), 1);
  99    PUSH_DATA (push, 1 << 24);
 100    BEGIN_NVC0(push, NVE4_COMPUTE(SHARED_BASE), 1);
 101    PUSH_DATA (push, 2 << 24);
 102
 103    BEGIN_NVC0(push, NVE4_COMPUTE(CODE_ADDRESS_HIGH), 2);
 104    PUSH_DATAh(push, screen->text->offset);
 105    PUSH_DATA (push, screen->text->offset);
 106
 107    BEGIN_NVC0(push, SUBC_COMPUTE(0x0310), 1);
 108    PUSH_DATA (push, (obj_class >= NVF0_COMPUTE_CLASS) ? 0x400 : 0x300);
 109
 110    /* NOTE: these do not affect the state used by the 3D object */
 111    BEGIN_NVC0(push, NVE4_COMPUTE(TIC_ADDRESS_HIGH), 3);
 112    PUSH_DATAh(push, screen->txc->offset);
 113    PUSH_DATA (push, screen->txc->offset);
 114    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
 115    BEGIN_NVC0(push, NVE4_COMPUTE(TSC_ADDRESS_HIGH), 3);
 116    PUSH_DATAh(push, screen->txc->offset + 65536);
 117    PUSH_DATA (push, screen->txc->offset + 65536);
 118    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
 119
 120    if (obj_class >= NVF0_COMPUTE_CLASS) {
 121       /* The blob calls GK110_COMPUTE.FIRMWARE[0x6], along with the args (0x1)
 122        * passed with GK110_COMPUTE.GRAPH.SCRATCH[0x2]. This is currently
 123        * disabled because our firmware doesn't support these commands and the
 124        * GPU hangs if they are used. */
 125       BEGIN_NIC0(push, SUBC_COMPUTE(0x0248), 64);
 126       for (i = 63; i >= 0; i--)
 127          PUSH_DATA(push, 0x38000 | i);
 128       IMMED_NVC0(push, SUBC_COMPUTE(NV50_GRAPH_SERIALIZE), 0);
 129    }
 130
 131    BEGIN_NVC0(push, NVE4_COMPUTE(TEX_CB_INDEX), 1);
 132    PUSH_DATA (push, 0); /* does not interefere with 3D */
 133
 134    if (obj_class == NVF0_COMPUTE_CLASS)
 135       IMMED_NVC0(push, SUBC_COMPUTE(0x02c4), 1);
 136
 137    /* MS sample coordinate offsets: these do not work with _ALT modes ! */
 138    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
 139    PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_MS_OFFSETS);
 140    PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_MS_OFFSETS);
 141    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
 142    PUSH_DATA (push, 64);
 143    PUSH_DATA (push, 1);
 144    BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 17);
 145    PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
 146    PUSH_DATA (push, 0); /* 0 */
 147    PUSH_DATA (push, 0);
 148    PUSH_DATA (push, 1); /* 1 */
 149    PUSH_DATA (push, 0);
 150    PUSH_DATA (push, 0); /* 2 */
 151    PUSH_DATA (push, 1);
 152    PUSH_DATA (push, 1); /* 3 */
 153    PUSH_DATA (push, 1);
 154    PUSH_DATA (push, 2); /* 4 */
 155    PUSH_DATA (push, 0);
 156    PUSH_DATA (push, 3); /* 5 */
 157    PUSH_DATA (push, 0);
 158    PUSH_DATA (push, 2); /* 6 */
 159    PUSH_DATA (push, 1);
 160    PUSH_DATA (push, 3); /* 7 */
 161    PUSH_DATA (push, 1);
 162
 163 #ifdef DEBUG
 164    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
 165    PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_TRAP_INFO_PTR);
 166    PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_TRAP_INFO_PTR);
 167    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
 168    PUSH_DATA (push, 28);
 169    PUSH_DATA (push, 1);
 170    BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 8);
 171    PUSH_DATA (push, 1);
 172    PUSH_DATA (push, screen->parm->offset + NVE4_CP_PARAM_TRAP_INFO);
 173    PUSH_DATAh(push, screen->parm->offset + NVE4_CP_PARAM_TRAP_INFO);
 174    PUSH_DATA (push, screen->tls->offset);
 175    PUSH_DATAh(push, screen->tls->offset);
 176    PUSH_DATA (push, screen->tls->size / 2); /* MP TEMP block size */
 177    PUSH_DATA (push, screen->tls->size / 2 / 64); /* warp TEMP block size */
 178    PUSH_DATA (push, 0); /* warp cfstack size */
 179 #endif
 180
 181    BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
 182    PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
 183
 184    return 0;
 185 }
 186
 187
 188 static void
 189 nve4_compute_validate_surfaces(struct nvc0_context *nvc0)
 190 {
 191    struct nvc0_screen *screen = nvc0->screen;
 192    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 193    struct nv50_surface *sf;
 194    struct nv04_resource *res;
 195    uint32_t mask;
 196    unsigned i;
 197    const unsigned t = 1;
 198
 199    mask = nvc0->surfaces_dirty[t];
 200    while (mask) {
 201       i = ffs(mask) - 1;
 202       mask &= ~(1 << i);
 203
 204       /*
 205        * NVE4's surface load/store instructions receive all the information
 206        * directly instead of via binding points, so we have to supply them.
 207        */
 208       BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
 209       PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_SUF(i));
 210       PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_SUF(i));
 211       BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
 212       PUSH_DATA (push, 64);
 213       PUSH_DATA (push, 1);
 214       BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 17);
 215       PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
 216
 217       nve4_set_surface_info(push, nvc0->surfaces[t][i], screen);
 218
 219       sf = nv50_surface(nvc0->surfaces[t][i]);
 220       if (sf) {
 221          res = nv04_resource(sf->base.texture);
 222
 223          if (sf->base.writable)
 224             BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RDWR);
 225          else
 226             BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RD);
 227       }
 228    }
 229    if (nvc0->surfaces_dirty[t]) {
 230       BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
 231       PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
 232    }
 233
 234    /* re-reference non-dirty surfaces */
 235    mask = nvc0->surfaces_valid[t] & ~nvc0->surfaces_dirty[t];
 236    while (mask) {
 237       i = ffs(mask) - 1;
 238       mask &= ~(1 << i);
 239
 240       sf = nv50_surface(nvc0->surfaces[t][i]);
 241       res = nv04_resource(sf->base.texture);
 242
 243       if (sf->base.writable)
 244          BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RDWR);
 245       else
 246          BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RD);
 247    }
 248
 249    nvc0->surfaces_dirty[t] = 0;
 250 }
 251
 252
 253 /* Thankfully, textures with samplers follow the normal rules. */
 254 static void
 255 nve4_compute_validate_samplers(struct nvc0_context *nvc0)
 256 {
 257    bool need_flush = nve4_validate_tsc(nvc0, 5);
 258    if (need_flush) {
 259       BEGIN_NVC0(nvc0->base.pushbuf, NVE4_COMPUTE(TSC_FLUSH), 1);
 260       PUSH_DATA (nvc0->base.pushbuf, 0);
 261    }
 262 }
 263 /* (Code duplicated at bottom for various non-convincing reasons.
 264  *  E.g. we might want to use the COMPUTE subchannel to upload TIC/TSC
 265  *  entries to avoid a subchannel switch.
 266  *  Same for texture cache flushes.
 267  *  Also, the bufctx differs, and more IFs in the 3D version looks ugly.)
 268  */
 269 static void nve4_compute_validate_textures(struct nvc0_context *);
 270
 271 static void
 272 nve4_compute_set_tex_handles(struct nvc0_context *nvc0)
 273 {
 274    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 275    uint64_t address;
 276    const unsigned s = nvc0_shader_stage(PIPE_SHADER_COMPUTE);
 277    unsigned i, n;
 278    uint32_t dirty = nvc0->textures_dirty[s] | nvc0->samplers_dirty[s];
 279
 280    if (!dirty)
 281       return;
 282    i = ffs(dirty) - 1;
 283    n = util_logbase2(dirty) + 1 - i;
 284    assert(n);
 285
 286    address = nvc0->screen->parm->offset + NVE4_CP_INPUT_TEX(i);
 287
 288    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
 289    PUSH_DATAh(push, address);
 290    PUSH_DATA (push, address);
 291    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
 292    PUSH_DATA (push, n * 4);
 293    PUSH_DATA (push, 0x1);
 294    BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + n);
 295    PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
 296    PUSH_DATAp(push, &nvc0->tex_handles[s][i], n);
 297
 298    BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
 299    PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
 300
 301    nvc0->textures_dirty[s] = 0;
 302    nvc0->samplers_dirty[s] = 0;
 303 }
 304
 305
 306 static bool
 307 nve4_compute_state_validate(struct nvc0_context *nvc0)
 308 {
 309    if (!nvc0_compute_validate_program(nvc0))
 310       return false;
 311    if (nvc0->dirty_cp & NVC0_NEW_CP_TEXTURES)
 312       nve4_compute_validate_textures(nvc0);
 313    if (nvc0->dirty_cp & NVC0_NEW_CP_SAMPLERS)
 314       nve4_compute_validate_samplers(nvc0);
 315    if (nvc0->dirty_cp & (NVC0_NEW_CP_TEXTURES | NVC0_NEW_CP_SAMPLERS))
 316        nve4_compute_set_tex_handles(nvc0);
 317    if (nvc0->dirty_cp & NVC0_NEW_CP_SURFACES)
 318       nve4_compute_validate_surfaces(nvc0);
 319    if (nvc0->dirty_cp & NVC0_NEW_CP_GLOBALS)
 320       nvc0_validate_global_residents(nvc0,
 321                                      nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL);
 322
 323    nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, false);
 324
 325    nouveau_pushbuf_bufctx(nvc0->base.pushbuf, nvc0->bufctx_cp);
 326    if (unlikely(nouveau_pushbuf_validate(nvc0->base.pushbuf)))
 327       return false;
 328    if (unlikely(nvc0->state.flushed))
 329       nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, true);
 330
 331    return true;
 332 }
 333
 334
 335 static void
 336 nve4_compute_upload_input(struct nvc0_context *nvc0, const void *input,
 337                           const uint *block_layout,
 338                           const uint *grid_layout)
 339 {
 340    struct nvc0_screen *screen = nvc0->screen;
 341    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 342    struct nvc0_program *cp = nvc0->compprog;
 343
 344    if (cp->parm_size) {
 345       BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
 346       PUSH_DATAh(push, screen->parm->offset);
 347       PUSH_DATA (push, screen->parm->offset);
 348       BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
 349       PUSH_DATA (push, cp->parm_size);
 350       PUSH_DATA (push, 0x1);
 351       BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + (cp->parm_size / 4));
 352       PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
 353       PUSH_DATAp(push, input, cp->parm_size / 4);
 354    }
 355    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
 356    PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_GRID_INFO(0));
 357    PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_GRID_INFO(0));
 358    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
 359    PUSH_DATA (push, 7 * 4);
 360    PUSH_DATA (push, 0x1);
 361    BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + 7);
 362    PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
 363    PUSH_DATAp(push, block_layout, 3);
 364    PUSH_DATAp(push, grid_layout, 3);
 365    PUSH_DATA (push, 0);
 366
 367    BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
 368    PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
 369 }
 370
 371 static inline uint8_t
 372 nve4_compute_derive_cache_split(struct nvc0_context *nvc0, uint32_t shared_size)
 373 {
 374    if (shared_size > (32 << 10))
 375       return NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1;
 376    if (shared_size > (16 << 10))
 377       return NVE4_3D_CACHE_SPLIT_32K_SHARED_32K_L1;
 378    return NVC1_3D_CACHE_SPLIT_16K_SHARED_48K_L1;
 379 }
 380
 381 static void
 382 nve4_compute_setup_launch_desc(struct nvc0_context *nvc0,
 383                                struct nve4_cp_launch_desc *desc,
 384                                uint32_t label,
 385                                const uint *block_layout,
 386                                const uint *grid_layout)
 387 {
 388    const struct nvc0_screen *screen = nvc0->screen;
 389    const struct nvc0_program *cp = nvc0->compprog;
 390    unsigned i;
 391
 392    nve4_cp_launch_desc_init_default(desc);
 393
 394    desc->entry = nvc0_program_symbol_offset(cp, label);
 395
 396    desc->griddim_x = grid_layout[0];
 397    desc->griddim_y = grid_layout[1];
 398    desc->griddim_z = grid_layout[2];
 399    desc->blockdim_x = block_layout[0];
 400    desc->blockdim_y = block_layout[1];
 401    desc->blockdim_z = block_layout[2];
 402
 403    desc->shared_size = align(cp->cp.smem_size, 0x100);
 404    desc->local_size_p = align(cp->cp.lmem_size, 0x10);
 405    desc->local_size_n = 0;
 406    desc->cstack_size = 0x800;
 407    desc->cache_split = nve4_compute_derive_cache_split(nvc0, cp->cp.smem_size);
 408
 409    desc->gpr_alloc = cp->num_gprs;
 410    desc->bar_alloc = cp->num_barriers;
 411
 412    for (i = 0; i < 7; ++i) {
 413       const unsigned s = 5;
 414       if (nvc0->constbuf[s][i].u.buf)
 415          nve4_cp_launch_desc_set_ctx_cb(desc, i + 1, &nvc0->constbuf[s][i]);
 416    }
 417    nve4_cp_launch_desc_set_cb(desc, 0, screen->parm, 0, NVE4_CP_INPUT_SIZE);
 418 }
 419
 420 static inline struct nve4_cp_launch_desc *
 421 nve4_compute_alloc_launch_desc(struct nouveau_context *nv,
 422                                struct nouveau_bo **pbo, uint64_t *pgpuaddr)
 423 {
 424    uint8_t *ptr = nouveau_scratch_get(nv, 512, pgpuaddr, pbo);
 425    if (!ptr)
 426       return NULL;
 427    if (*pgpuaddr & 255) {
 428       unsigned adj = 256 - (*pgpuaddr & 255);
 429       ptr += adj;
 430       *pgpuaddr += adj;
 431    }
 432    return (struct nve4_cp_launch_desc *)ptr;
 433 }
 434
 435 void
 436 nve4_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
 437 {
 438    struct nvc0_context *nvc0 = nvc0_context(pipe);
 439    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 440    struct nve4_cp_launch_desc *desc;
 441    uint64_t desc_gpuaddr;
 442    struct nouveau_bo *desc_bo;
 443    int ret;
 444
 445    desc = nve4_compute_alloc_launch_desc(&nvc0->base, &desc_bo, &desc_gpuaddr);
 446    if (!desc) {
 447       ret = -1;
 448       goto out;
 449    }
 450    BCTX_REFN_bo(nvc0->bufctx_cp, CP_DESC, NOUVEAU_BO_GART | NOUVEAU_BO_RD,
 451                 desc_bo);
 452
 453    ret = !nve4_compute_state_validate(nvc0);
 454    if (ret)
 455       goto out;
 456
 457    nve4_compute_setup_launch_desc(nvc0, desc, info->pc,
 458                                   info->block, info->grid);
 459 #ifdef DEBUG
 460    if (debug_get_num_option("NV50_PROG_DEBUG", 0))
 461       nve4_compute_dump_launch_desc(desc);
 462 #endif
 463
 464    nve4_compute_upload_input(nvc0, info->input, info->block, info->grid);
 465
 466    /* upload descriptor and flush */
 467 #if 0
 468    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
 469    PUSH_DATAh(push, desc_gpuaddr);
 470    PUSH_DATA (push, desc_gpuaddr);
 471    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
 472    PUSH_DATA (push, 256);
 473    PUSH_DATA (push, 1);
 474    BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + (256 / 4));
 475    PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x08 << 1));
 476    PUSH_DATAp(push, (const uint32_t *)desc, 256 / 4);
 477    BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
 478    PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB | NVE4_COMPUTE_FLUSH_CODE);
 479 #endif
 480    BEGIN_NVC0(push, NVE4_COMPUTE(LAUNCH_DESC_ADDRESS), 1);
 481    PUSH_DATA (push, desc_gpuaddr >> 8);
 482    BEGIN_NVC0(push, NVE4_COMPUTE(LAUNCH), 1);
 483    PUSH_DATA (push, 0x3);
 484    BEGIN_NVC0(push, SUBC_COMPUTE(NV50_GRAPH_SERIALIZE), 1);
 485    PUSH_DATA (push, 0);
 486
 487 out:
 488    if (ret)
 489       NOUVEAU_ERR("Failed to launch grid !\n");
 490    nouveau_scratch_done(&nvc0->base);
 491    nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_DESC);
 492 }
 493
 494
 495 #define NVE4_TIC_ENTRY_INVALID 0x000fffff
 496
 497 static void
 498 nve4_compute_validate_textures(struct nvc0_context *nvc0)
 499 {
 500    struct nouveau_bo *txc = nvc0->screen->txc;
 501    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 502    const unsigned s = 5;
 503    unsigned i;
 504    uint32_t commands[2][NVE4_CP_INPUT_TEX_MAX];
 505    unsigned n[2] = { 0, 0 };
 506
 507    for (i = 0; i < nvc0->num_textures[s]; ++i) {
 508       struct nv50_tic_entry *tic = nv50_tic_entry(nvc0->textures[s][i]);
 509       struct nv04_resource *res;
 510       const bool dirty = !!(nvc0->textures_dirty[s] & (1 << i));
 511
 512       if (!tic) {
 513          nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID;
 514          continue;
 515       }
 516       res = nv04_resource(tic->pipe.texture);
 517
 518       if (tic->id < 0) {
 519          tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
 520
 521          PUSH_SPACE(push, 16);
 522          BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
 523          PUSH_DATAh(push, txc->offset + (tic->id * 32));
 524          PUSH_DATA (push, txc->offset + (tic->id * 32));
 525          BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
 526          PUSH_DATA (push, 32);
 527          PUSH_DATA (push, 1);
 528          BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 9);
 529          PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
 530          PUSH_DATAp(push, &tic->tic[0], 8);
 531
 532          commands[0][n[0]++] = (tic->id << 4) | 1;
 533       } else
 534       if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
 535          commands[1][n[1]++] = (tic->id << 4) | 1;
 536       }
 537       nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
 538
 539       res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
 540       res->status |=  NOUVEAU_BUFFER_STATUS_GPU_READING;
 541
 542       nvc0->tex_handles[s][i] &= ~NVE4_TIC_ENTRY_INVALID;
 543       nvc0->tex_handles[s][i] |= tic->id;
 544       if (dirty)
 545          BCTX_REFN(nvc0->bufctx_cp, CP_TEX(i), res, RD);
 546    }
 547    for (; i < nvc0->state.num_textures[s]; ++i)
 548       nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID;
 549
 550    if (n[0]) {
 551       BEGIN_NIC0(push, NVE4_COMPUTE(TIC_FLUSH), n[0]);
 552       PUSH_DATAp(push, commands[0], n[0]);
 553    }
 554    if (n[1]) {
 555       BEGIN_NIC0(push, NVE4_COMPUTE(TEX_CACHE_CTL), n[1]);
 556       PUSH_DATAp(push, commands[1], n[1]);
 557    }
 558
 559    nvc0->state.num_textures[s] = nvc0->num_textures[s];
 560 }
 561
 562
 563 #ifdef DEBUG
 564 static const char *nve4_cache_split_name(unsigned value)
 565 {
 566    switch (value) {
 567    case NVC1_3D_CACHE_SPLIT_16K_SHARED_48K_L1: return "16K_SHARED_48K_L1";
 568    case NVE4_3D_CACHE_SPLIT_32K_SHARED_32K_L1: return "32K_SHARED_32K_L1";
 569    case NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1: return "48K_SHARED_16K_L1";
 570    default:
 571       return "(invalid)";
 572    }
 573 }
 574
 575 static void
 576 nve4_compute_dump_launch_desc(const struct nve4_cp_launch_desc *desc)
 577 {
 578    const uint32_t *data = (const uint32_t *)desc;
 579    unsigned i;
 580    bool zero = false;
 581
 582    debug_printf("COMPUTE LAUNCH DESCRIPTOR:\n");
 583
 584    for (i = 0; i < sizeof(*desc); i += 4) {
 585       if (data[i / 4]) {
 586          debug_printf("[%x]: 0x%08x\n", i, data[i / 4]);
 587          zero = false;
 588       } else
 589       if (!zero) {
 590          debug_printf("...\n");
 591          zero = true;
 592       }
 593    }
 594
 595    debug_printf("entry = 0x%x\n", desc->entry);
 596    debug_printf("grid dimensions = %ux%ux%u\n",
 597                 desc->griddim_x, desc->griddim_y, desc->griddim_z);
 598    debug_printf("block dimensions = %ux%ux%u\n",
 599                 desc->blockdim_x, desc->blockdim_y, desc->blockdim_z);
 600    debug_printf("s[] size: 0x%x\n", desc->shared_size);
 601    debug_printf("l[] size: -0x%x / +0x%x\n",
 602                 desc->local_size_n, desc->local_size_p);
 603    debug_printf("stack size: 0x%x\n", desc->cstack_size);
 604    debug_printf("barrier count: %u\n", desc->bar_alloc);
 605    debug_printf("$r count: %u\n", desc->gpr_alloc);
 606    debug_printf("cache split: %s\n", nve4_cache_split_name(desc->cache_split));
 607
 608    for (i = 0; i < 8; ++i) {
 609       uint64_t address;
 610       uint32_t size = desc->cb[i].size;
 611       bool valid = !!(desc->cb_mask & (1 << i));
 612
 613       address = ((uint64_t)desc->cb[i].address_h << 32) | desc->cb[i].address_l;
 614
 615       if (!valid && !address && !size)
 616          continue;
 617       debug_printf("CB[%u]: address = 0x%"PRIx64", size 0x%x%s\n",
 618                    i, address, size, valid ? "" : "  (invalid)");
 619    }
 620 }
 621 #endif
 622
 623 #ifdef NOUVEAU_NVE4_MP_TRAP_HANDLER
 624 static void
 625 nve4_compute_trap_info(struct nvc0_context *nvc0)
 626 {
 627    struct nvc0_screen *screen = nvc0->screen;
 628    struct nouveau_bo *bo = screen->parm;
 629    int ret, i;
 630    volatile struct nve4_mp_trap_info *info;
 631    uint8_t *map;
 632
 633    ret = nouveau_bo_map(bo, NOUVEAU_BO_RDWR, nvc0->base.client);
 634    if (ret)
 635       return;
 636    map = (uint8_t *)bo->map;
 637    info = (volatile struct nve4_mp_trap_info *)(map + NVE4_CP_PARAM_TRAP_INFO);
 638
 639    if (info->lock) {
 640       debug_printf("trapstat = %08x\n", info->trapstat);
 641       debug_printf("warperr = %08x\n", info->warperr);
 642       debug_printf("PC = %x\n", info->pc);
 643       debug_printf("tid = %u %u %u\n",
 644                    info->tid[0], info->tid[1], info->tid[2]);
 645       debug_printf("ctaid = %u %u %u\n",
 646                    info->ctaid[0], info->ctaid[1], info->ctaid[2]);
 647       for (i = 0; i <= 63; ++i)
 648          debug_printf("$r%i = %08x\n", i, info->r[i]);
 649       for (i = 0; i <= 6; ++i)
 650          debug_printf("$p%i = %i\n", i, (info->flags >> i) & 1);
 651       debug_printf("$c = %x\n", info->flags >> 12);
 652    }
 653    info->lock = 0;
 654 }
 655 #endif