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nvc0: add a new bin for the code segment
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nve4_compute.c
1 /*
2 * Copyright 2012 Nouveau Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Christoph Bumiller
23 */
24
25 #include "nvc0/nvc0_context.h"
26 #include "nvc0/nve4_compute.h"
27
28 #include "codegen/nv50_ir_driver.h"
29
30 #ifdef DEBUG
31 static void nve4_compute_dump_launch_desc(const struct nve4_cp_launch_desc *);
32 #endif
33
34
35 int
36 nve4_screen_compute_setup(struct nvc0_screen *screen,
37 struct nouveau_pushbuf *push)
38 {
39 struct nouveau_device *dev = screen->base.device;
40 struct nouveau_object *chan = screen->base.channel;
41 int i;
42 int ret;
43 uint32_t obj_class;
44 uint64_t address;
45
46 switch (dev->chipset & ~0xf) {
47 case 0x100:
48 case 0xf0:
49 obj_class = NVF0_COMPUTE_CLASS; /* GK110 */
50 break;
51 case 0xe0:
52 obj_class = NVE4_COMPUTE_CLASS; /* GK104 */
53 break;
54 case 0x110:
55 obj_class = GM107_COMPUTE_CLASS;
56 break;
57 case 0x120:
58 obj_class = GM200_COMPUTE_CLASS;
59 break;
60 default:
61 NOUVEAU_ERR("unsupported chipset: NV%02x\n", dev->chipset);
62 return -1;
63 }
64
65 ret = nouveau_object_new(chan, 0xbeef00c0, obj_class, NULL, 0,
66 &screen->compute);
67 if (ret) {
68 NOUVEAU_ERR("Failed to allocate compute object: %d\n", ret);
69 return ret;
70 }
71
72 BEGIN_NVC0(push, SUBC_CP(NV01_SUBCHAN_OBJECT), 1);
73 PUSH_DATA (push, screen->compute->oclass);
74
75 BEGIN_NVC0(push, NVE4_CP(TEMP_ADDRESS_HIGH), 2);
76 PUSH_DATAh(push, screen->tls->offset);
77 PUSH_DATA (push, screen->tls->offset);
78 /* No idea why there are 2. Divide size by 2 to be safe.
79 * Actually this might be per-MP TEMP size and looks like I'm only using
80 * 2 MPs instead of all 8.
81 */
82 BEGIN_NVC0(push, NVE4_CP(MP_TEMP_SIZE_HIGH(0)), 3);
83 PUSH_DATAh(push, screen->tls->size / screen->mp_count);
84 PUSH_DATA (push, (screen->tls->size / screen->mp_count) & ~0x7fff);
85 PUSH_DATA (push, 0xff);
86 BEGIN_NVC0(push, NVE4_CP(MP_TEMP_SIZE_HIGH(1)), 3);
87 PUSH_DATAh(push, screen->tls->size / screen->mp_count);
88 PUSH_DATA (push, (screen->tls->size / screen->mp_count) & ~0x7fff);
89 PUSH_DATA (push, 0xff);
90
91 /* Unified address space ? Who needs that ? Certainly not OpenCL.
92 *
93 * FATAL: Buffers with addresses inside [0x1000000, 0x3000000] will NOT be
94 * accessible. We cannot prevent that at the moment, so expect failure.
95 */
96 BEGIN_NVC0(push, NVE4_CP(LOCAL_BASE), 1);
97 PUSH_DATA (push, 0xff << 24);
98 BEGIN_NVC0(push, NVE4_CP(SHARED_BASE), 1);
99 PUSH_DATA (push, 0xfe << 24);
100
101 BEGIN_NVC0(push, NVE4_CP(CODE_ADDRESS_HIGH), 2);
102 PUSH_DATAh(push, screen->text->offset);
103 PUSH_DATA (push, screen->text->offset);
104
105 BEGIN_NVC0(push, SUBC_CP(0x0310), 1);
106 PUSH_DATA (push, (obj_class >= NVF0_COMPUTE_CLASS) ? 0x400 : 0x300);
107
108 /* NOTE: these do not affect the state used by the 3D object */
109 BEGIN_NVC0(push, NVE4_CP(TIC_ADDRESS_HIGH), 3);
110 PUSH_DATAh(push, screen->txc->offset);
111 PUSH_DATA (push, screen->txc->offset);
112 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
113 BEGIN_NVC0(push, NVE4_CP(TSC_ADDRESS_HIGH), 3);
114 PUSH_DATAh(push, screen->txc->offset + 65536);
115 PUSH_DATA (push, screen->txc->offset + 65536);
116 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
117
118 if (obj_class >= NVF0_COMPUTE_CLASS) {
119 /* The blob calls GK110_COMPUTE.FIRMWARE[0x6], along with the args (0x1)
120 * passed with GK110_COMPUTE.GRAPH.SCRATCH[0x2]. This is currently
121 * disabled because our firmware doesn't support these commands and the
122 * GPU hangs if they are used. */
123 BEGIN_NIC0(push, SUBC_CP(0x0248), 64);
124 for (i = 63; i >= 0; i--)
125 PUSH_DATA(push, 0x38000 | i);
126 IMMED_NVC0(push, SUBC_CP(NV50_GRAPH_SERIALIZE), 0);
127 }
128
129 BEGIN_NVC0(push, NVE4_CP(TEX_CB_INDEX), 1);
130 PUSH_DATA (push, 7); /* does not interfere with 3D */
131
132 /* Disabling this UNK command avoid a read fault when using texelFetch()
133 * from a compute shader for weird reasons.
134 if (obj_class == NVF0_COMPUTE_CLASS)
135 IMMED_NVC0(push, SUBC_CP(0x02c4), 1);
136 */
137
138 address = screen->uniform_bo->offset + NVC0_CB_AUX_INFO(5);
139
140 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
141 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
142 PUSH_DATAh(push, address + NVC0_CB_AUX_MS_INFO);
143 PUSH_DATA (push, address + NVC0_CB_AUX_MS_INFO);
144 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
145 PUSH_DATA (push, 64);
146 PUSH_DATA (push, 1);
147 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 17);
148 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
149 PUSH_DATA (push, 0); /* 0 */
150 PUSH_DATA (push, 0);
151 PUSH_DATA (push, 1); /* 1 */
152 PUSH_DATA (push, 0);
153 PUSH_DATA (push, 0); /* 2 */
154 PUSH_DATA (push, 1);
155 PUSH_DATA (push, 1); /* 3 */
156 PUSH_DATA (push, 1);
157 PUSH_DATA (push, 2); /* 4 */
158 PUSH_DATA (push, 0);
159 PUSH_DATA (push, 3); /* 5 */
160 PUSH_DATA (push, 0);
161 PUSH_DATA (push, 2); /* 6 */
162 PUSH_DATA (push, 1);
163 PUSH_DATA (push, 3); /* 7 */
164 PUSH_DATA (push, 1);
165
166 #ifdef NOUVEAU_NVE4_MP_TRAP_HANDLER
167 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
168 PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_TRAP_INFO_PTR);
169 PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_TRAP_INFO_PTR);
170 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
171 PUSH_DATA (push, 28);
172 PUSH_DATA (push, 1);
173 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 8);
174 PUSH_DATA (push, 1);
175 PUSH_DATA (push, screen->parm->offset + NVE4_CP_PARAM_TRAP_INFO);
176 PUSH_DATAh(push, screen->parm->offset + NVE4_CP_PARAM_TRAP_INFO);
177 PUSH_DATA (push, screen->tls->offset);
178 PUSH_DATAh(push, screen->tls->offset);
179 PUSH_DATA (push, screen->tls->size / 2); /* MP TEMP block size */
180 PUSH_DATA (push, screen->tls->size / 2 / 64); /* warp TEMP block size */
181 PUSH_DATA (push, 0); /* warp cfstack size */
182 #endif
183
184 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
185 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
186
187 return 0;
188 }
189
190 static void
191 gm107_compute_validate_surfaces(struct nvc0_context *nvc0,
192 struct pipe_image_view *view, int slot)
193 {
194 struct nv04_resource *res = nv04_resource(view->resource);
195 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
196 struct nvc0_screen *screen = nvc0->screen;
197 struct nouveau_bo *txc = nvc0->screen->txc;
198 struct nv50_tic_entry *tic;
199 uint64_t address;
200 const int s = 5;
201
202 tic = nv50_tic_entry(nvc0->images_tic[s][slot]);
203
204 res = nv04_resource(tic->pipe.texture);
205 nvc0_update_tic(nvc0, tic, res);
206
207 if (tic->id < 0) {
208 tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
209
210 /* upload the texture view */
211 PUSH_SPACE(push, 16);
212 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
213 PUSH_DATAh(push, txc->offset + (tic->id * 32));
214 PUSH_DATA (push, txc->offset + (tic->id * 32));
215 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
216 PUSH_DATA (push, 32);
217 PUSH_DATA (push, 1);
218 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 9);
219 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
220 PUSH_DATAp(push, &tic->tic[0], 8);
221
222 BEGIN_NIC0(push, NVE4_CP(TIC_FLUSH), 1);
223 PUSH_DATA (push, (tic->id << 4) | 1);
224 } else
225 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
226 BEGIN_NIC0(push, NVE4_CP(TEX_CACHE_CTL), 1);
227 PUSH_DATA (push, (tic->id << 4) | 1);
228 }
229 nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
230
231 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
232 res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
233
234 BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RD);
235
236 address = screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
237
238 /* upload the texture handle */
239 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
240 PUSH_DATAh(push, address + NVC0_CB_AUX_TEX_INFO(slot + 32));
241 PUSH_DATA (push, address + NVC0_CB_AUX_TEX_INFO(slot + 32));
242 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
243 PUSH_DATA (push, 4);
244 PUSH_DATA (push, 0x1);
245 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 2);
246 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
247 PUSH_DATA (push, tic->id);
248
249 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
250 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
251 }
252
253 static void
254 nve4_compute_validate_surfaces(struct nvc0_context *nvc0)
255 {
256 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
257 uint64_t address;
258 const int s = 5;
259 int i, j;
260
261 if (!nvc0->images_dirty[s])
262 return;
263
264 address = nvc0->screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
265
266 for (i = 0; i < NVC0_MAX_IMAGES; ++i) {
267 struct pipe_image_view *view = &nvc0->images[s][i];
268
269 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
270 PUSH_DATAh(push, address + NVC0_CB_AUX_SU_INFO(i));
271 PUSH_DATA (push, address + NVC0_CB_AUX_SU_INFO(i));
272 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
273 PUSH_DATA (push, 16 * 4);
274 PUSH_DATA (push, 0x1);
275 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 16);
276 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
277
278 if (view->resource) {
279 struct nv04_resource *res = nv04_resource(view->resource);
280
281 if (res->base.target == PIPE_BUFFER) {
282 if (view->access & PIPE_IMAGE_ACCESS_WRITE)
283 nvc0_mark_image_range_valid(view);
284 }
285
286 nve4_set_surface_info(push, view, nvc0);
287 BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RDWR);
288
289 if (nvc0->screen->base.class_3d >= GM107_3D_CLASS)
290 gm107_compute_validate_surfaces(nvc0, view, i);
291 } else {
292 for (j = 0; j < 16; j++)
293 PUSH_DATA(push, 0);
294 }
295 }
296 }
297
298 /* Thankfully, textures with samplers follow the normal rules. */
299 static void
300 nve4_compute_validate_samplers(struct nvc0_context *nvc0)
301 {
302 bool need_flush = nve4_validate_tsc(nvc0, 5);
303 if (need_flush) {
304 BEGIN_NVC0(nvc0->base.pushbuf, NVE4_CP(TSC_FLUSH), 1);
305 PUSH_DATA (nvc0->base.pushbuf, 0);
306 }
307
308 /* Invalidate all 3D samplers because they are aliased. */
309 for (int s = 0; s < 5; s++)
310 nvc0->samplers_dirty[s] = ~0;
311 nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLERS;
312 }
313
314 /* (Code duplicated at bottom for various non-convincing reasons.
315 * E.g. we might want to use the COMPUTE subchannel to upload TIC/TSC
316 * entries to avoid a subchannel switch.
317 * Same for texture cache flushes.
318 * Also, the bufctx differs, and more IFs in the 3D version looks ugly.)
319 */
320 static void nve4_compute_validate_textures(struct nvc0_context *);
321
322 static void
323 nve4_compute_set_tex_handles(struct nvc0_context *nvc0)
324 {
325 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
326 struct nvc0_screen *screen = nvc0->screen;
327 uint64_t address;
328 const unsigned s = nvc0_shader_stage(PIPE_SHADER_COMPUTE);
329 unsigned i, n;
330 uint32_t dirty = nvc0->textures_dirty[s] | nvc0->samplers_dirty[s];
331
332 if (!dirty)
333 return;
334 i = ffs(dirty) - 1;
335 n = util_logbase2(dirty) + 1 - i;
336 assert(n);
337
338 address = screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
339
340 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
341 PUSH_DATAh(push, address + NVC0_CB_AUX_TEX_INFO(i));
342 PUSH_DATA (push, address + NVC0_CB_AUX_TEX_INFO(i));
343 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
344 PUSH_DATA (push, n * 4);
345 PUSH_DATA (push, 0x1);
346 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + n);
347 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
348 PUSH_DATAp(push, &nvc0->tex_handles[s][i], n);
349
350 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
351 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
352
353 nvc0->textures_dirty[s] = 0;
354 nvc0->samplers_dirty[s] = 0;
355 }
356
357 static void
358 nve4_compute_validate_constbufs(struct nvc0_context *nvc0)
359 {
360 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
361 const int s = 5;
362
363 while (nvc0->constbuf_dirty[s]) {
364 int i = ffs(nvc0->constbuf_dirty[s]) - 1;
365 nvc0->constbuf_dirty[s] &= ~(1 << i);
366
367 if (nvc0->constbuf[s][i].user) {
368 struct nouveau_bo *bo = nvc0->screen->uniform_bo;
369 const unsigned base = NVC0_CB_USR_INFO(s);
370 const unsigned size = nvc0->constbuf[s][0].size;
371 assert(i == 0); /* we really only want OpenGL uniforms here */
372 assert(nvc0->constbuf[s][0].u.data);
373
374 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
375 PUSH_DATAh(push, bo->offset + base);
376 PUSH_DATA (push, bo->offset + base);
377 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
378 PUSH_DATA (push, size);
379 PUSH_DATA (push, 0x1);
380 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (size / 4));
381 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
382 PUSH_DATAp(push, nvc0->constbuf[s][0].u.data, size / 4);
383 }
384 else {
385 struct nv04_resource *res =
386 nv04_resource(nvc0->constbuf[s][i].u.buf);
387 if (res) {
388 uint64_t address
389 = nvc0->screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
390
391 assert(i > 0); /* we really only want uniform buffer objects */
392
393 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
394 PUSH_DATAh(push, address + NVC0_CB_AUX_UBO_INFO(i - 1));
395 PUSH_DATA (push, address + NVC0_CB_AUX_UBO_INFO(i - 1));
396 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
397 PUSH_DATA (push, 4 * 4);
398 PUSH_DATA (push, 0x1);
399 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 4);
400 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
401
402 PUSH_DATA (push, res->address + nvc0->constbuf[s][i].offset);
403 PUSH_DATAh(push, res->address + nvc0->constbuf[s][i].offset);
404 PUSH_DATA (push, nvc0->constbuf[5][i].size);
405 PUSH_DATA (push, 0);
406 BCTX_REFN(nvc0->bufctx_cp, CP_CB(i), res, RD);
407
408 res->cb_bindings[s] |= 1 << i;
409 }
410 }
411 }
412
413 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
414 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
415 }
416
417 static void
418 nve4_compute_validate_buffers(struct nvc0_context *nvc0)
419 {
420 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
421 uint64_t address;
422 const int s = 5;
423 int i;
424
425 address = nvc0->screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
426
427 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
428 PUSH_DATAh(push, address + NVC0_CB_AUX_BUF_INFO(0));
429 PUSH_DATA (push, address + NVC0_CB_AUX_BUF_INFO(0));
430 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
431 PUSH_DATA (push, 4 * NVC0_MAX_BUFFERS * 4);
432 PUSH_DATA (push, 0x1);
433 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 4 * NVC0_MAX_BUFFERS);
434 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
435
436 for (i = 0; i < NVC0_MAX_BUFFERS; i++) {
437 if (nvc0->buffers[s][i].buffer) {
438 struct nv04_resource *res =
439 nv04_resource(nvc0->buffers[s][i].buffer);
440 PUSH_DATA (push, res->address + nvc0->buffers[s][i].buffer_offset);
441 PUSH_DATAh(push, res->address + nvc0->buffers[s][i].buffer_offset);
442 PUSH_DATA (push, nvc0->buffers[s][i].buffer_size);
443 PUSH_DATA (push, 0);
444 BCTX_REFN(nvc0->bufctx_cp, CP_BUF, res, RDWR);
445 util_range_add(&res->valid_buffer_range,
446 nvc0->buffers[s][i].buffer_offset,
447 nvc0->buffers[s][i].buffer_size);
448 } else {
449 PUSH_DATA (push, 0);
450 PUSH_DATA (push, 0);
451 PUSH_DATA (push, 0);
452 PUSH_DATA (push, 0);
453 }
454 }
455 }
456
457 static struct nvc0_state_validate
458 validate_list_cp[] = {
459 { nvc0_compprog_validate, NVC0_NEW_CP_PROGRAM },
460 { nve4_compute_validate_textures, NVC0_NEW_CP_TEXTURES },
461 { nve4_compute_validate_samplers, NVC0_NEW_CP_SAMPLERS },
462 { nve4_compute_set_tex_handles, NVC0_NEW_CP_TEXTURES |
463 NVC0_NEW_CP_SAMPLERS },
464 { nve4_compute_validate_surfaces, NVC0_NEW_CP_SURFACES },
465 { nvc0_compute_validate_globals, NVC0_NEW_CP_GLOBALS },
466 { nve4_compute_validate_buffers, NVC0_NEW_CP_BUFFERS },
467 { nve4_compute_validate_constbufs, NVC0_NEW_CP_CONSTBUF },
468 };
469
470 static bool
471 nve4_state_validate_cp(struct nvc0_context *nvc0, uint32_t mask)
472 {
473 bool ret;
474
475 ret = nvc0_state_validate(nvc0, mask, validate_list_cp,
476 ARRAY_SIZE(validate_list_cp), &nvc0->dirty_cp,
477 nvc0->bufctx_cp);
478
479 if (unlikely(nvc0->state.flushed))
480 nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, true);
481 return ret;
482 }
483
484 static void
485 nve4_compute_upload_input(struct nvc0_context *nvc0,
486 const struct pipe_grid_info *info)
487 {
488 struct nvc0_screen *screen = nvc0->screen;
489 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
490 struct nvc0_program *cp = nvc0->compprog;
491 uint64_t address;
492
493 address = screen->uniform_bo->offset + NVC0_CB_AUX_INFO(5);
494
495 if (cp->parm_size) {
496 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
497 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_USR_INFO(5));
498 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_USR_INFO(5));
499 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
500 PUSH_DATA (push, cp->parm_size);
501 PUSH_DATA (push, 0x1);
502 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (cp->parm_size / 4));
503 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
504 PUSH_DATAp(push, info->input, cp->parm_size / 4);
505 }
506 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
507 PUSH_DATAh(push, address + NVC0_CB_AUX_GRID_INFO(0));
508 PUSH_DATA (push, address + NVC0_CB_AUX_GRID_INFO(0));
509 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
510 PUSH_DATA (push, 8 * 4);
511 PUSH_DATA (push, 0x1);
512
513 if (unlikely(info->indirect)) {
514 struct nv04_resource *res = nv04_resource(info->indirect);
515 uint32_t offset = res->offset + info->indirect_offset;
516
517 nouveau_pushbuf_space(push, 16, 0, 1);
518 PUSH_REFN(push, res->bo, NOUVEAU_BO_RD | res->domain);
519
520 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 8);
521 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
522 PUSH_DATAp(push, info->block, 3);
523 nouveau_pushbuf_data(push, res->bo, offset,
524 NVC0_IB_ENTRY_1_NO_PREFETCH | 3 * 4);
525 } else {
526 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 8);
527 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
528 PUSH_DATAp(push, info->block, 3);
529 PUSH_DATAp(push, info->grid, 3);
530 }
531 PUSH_DATA (push, 0);
532 PUSH_DATA (push, info->work_dim);
533
534 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
535 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
536 }
537
538 static inline uint8_t
539 nve4_compute_derive_cache_split(struct nvc0_context *nvc0, uint32_t shared_size)
540 {
541 if (shared_size > (32 << 10))
542 return NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1;
543 if (shared_size > (16 << 10))
544 return NVE4_3D_CACHE_SPLIT_32K_SHARED_32K_L1;
545 return NVC1_3D_CACHE_SPLIT_16K_SHARED_48K_L1;
546 }
547
548 static void
549 nve4_compute_setup_launch_desc(struct nvc0_context *nvc0,
550 struct nve4_cp_launch_desc *desc,
551 const struct pipe_grid_info *info)
552 {
553 const struct nvc0_screen *screen = nvc0->screen;
554 const struct nvc0_program *cp = nvc0->compprog;
555
556 nve4_cp_launch_desc_init_default(desc);
557
558 desc->entry = nvc0_program_symbol_offset(cp, info->pc);
559
560 desc->griddim_x = info->grid[0];
561 desc->griddim_y = info->grid[1];
562 desc->griddim_z = info->grid[2];
563 desc->blockdim_x = info->block[0];
564 desc->blockdim_y = info->block[1];
565 desc->blockdim_z = info->block[2];
566
567 desc->shared_size = align(cp->cp.smem_size, 0x100);
568 desc->local_size_p = (cp->hdr[1] & 0xfffff0) + align(cp->cp.lmem_size, 0x10);
569 desc->local_size_n = 0;
570 desc->cstack_size = 0x800;
571 desc->cache_split = nve4_compute_derive_cache_split(nvc0, cp->cp.smem_size);
572
573 desc->gpr_alloc = cp->num_gprs;
574 desc->bar_alloc = cp->num_barriers;
575
576 // Only bind user uniforms and the driver constant buffer through the
577 // launch descriptor because UBOs are sticked to the driver cb to avoid the
578 // limitation of 8 CBs.
579 if (nvc0->constbuf[5][0].user || cp->parm_size) {
580 nve4_cp_launch_desc_set_cb(desc, 0, screen->uniform_bo,
581 NVC0_CB_USR_INFO(5), 1 << 16);
582 }
583 nve4_cp_launch_desc_set_cb(desc, 7, screen->uniform_bo,
584 NVC0_CB_AUX_INFO(5), 1 << 11);
585 }
586
587 static inline struct nve4_cp_launch_desc *
588 nve4_compute_alloc_launch_desc(struct nouveau_context *nv,
589 struct nouveau_bo **pbo, uint64_t *pgpuaddr)
590 {
591 uint8_t *ptr = nouveau_scratch_get(nv, 512, pgpuaddr, pbo);
592 if (!ptr)
593 return NULL;
594 if (*pgpuaddr & 255) {
595 unsigned adj = 256 - (*pgpuaddr & 255);
596 ptr += adj;
597 *pgpuaddr += adj;
598 }
599 return (struct nve4_cp_launch_desc *)ptr;
600 }
601
602 void
603 nve4_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
604 {
605 struct nvc0_context *nvc0 = nvc0_context(pipe);
606 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
607 struct nve4_cp_launch_desc *desc;
608 uint64_t desc_gpuaddr;
609 struct nouveau_bo *desc_bo;
610 int ret;
611
612 desc = nve4_compute_alloc_launch_desc(&nvc0->base, &desc_bo, &desc_gpuaddr);
613 if (!desc) {
614 ret = -1;
615 goto out;
616 }
617 BCTX_REFN_bo(nvc0->bufctx_cp, CP_DESC, NOUVEAU_BO_GART | NOUVEAU_BO_RD,
618 desc_bo);
619
620 ret = !nve4_state_validate_cp(nvc0, ~0);
621 if (ret)
622 goto out;
623
624 nve4_compute_setup_launch_desc(nvc0, desc, info);
625
626 nve4_compute_upload_input(nvc0, info);
627
628 #ifdef DEBUG
629 if (debug_get_num_option("NV50_PROG_DEBUG", 0))
630 nve4_compute_dump_launch_desc(desc);
631 #endif
632
633 if (unlikely(info->indirect)) {
634 struct nv04_resource *res = nv04_resource(info->indirect);
635 uint32_t offset = res->offset + info->indirect_offset;
636
637 /* upload the descriptor */
638 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
639 PUSH_DATAh(push, desc_gpuaddr);
640 PUSH_DATA (push, desc_gpuaddr);
641 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
642 PUSH_DATA (push, 256);
643 PUSH_DATA (push, 1);
644 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (256 / 4));
645 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x08 << 1));
646 PUSH_DATAp(push, (const uint32_t *)desc, 256 / 4);
647
648 /* overwrite griddim_x and griddim_y as two 32-bits integers even
649 * if griddim_y must be a 16-bits integer */
650 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
651 PUSH_DATAh(push, desc_gpuaddr + 48);
652 PUSH_DATA (push, desc_gpuaddr + 48);
653 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
654 PUSH_DATA (push, 8);
655 PUSH_DATA (push, 1);
656
657 nouveau_pushbuf_space(push, 16, 0, 1);
658 PUSH_REFN(push, res->bo, NOUVEAU_BO_RD | res->domain);
659
660 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (8 / 4));
661 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x08 << 1));
662 nouveau_pushbuf_data(push, res->bo, offset,
663 NVC0_IB_ENTRY_1_NO_PREFETCH | 2 * 4);
664
665 /* overwrite the 16 high bits of griddim_y with griddim_z because
666 * we need (z << 16) | x */
667 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
668 PUSH_DATAh(push, desc_gpuaddr + 54);
669 PUSH_DATA (push, desc_gpuaddr + 54);
670 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
671 PUSH_DATA (push, 4);
672 PUSH_DATA (push, 1);
673 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (4 / 4));
674 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x08 << 1));
675 nouveau_pushbuf_data(push, res->bo, offset + 8,
676 NVC0_IB_ENTRY_1_NO_PREFETCH | 1 * 4);
677 }
678
679 /* upload descriptor and flush */
680 BEGIN_NVC0(push, NVE4_CP(LAUNCH_DESC_ADDRESS), 1);
681 PUSH_DATA (push, desc_gpuaddr >> 8);
682 BEGIN_NVC0(push, NVE4_CP(LAUNCH), 1);
683 PUSH_DATA (push, 0x3);
684 BEGIN_NVC0(push, SUBC_CP(NV50_GRAPH_SERIALIZE), 1);
685 PUSH_DATA (push, 0);
686
687 out:
688 if (ret)
689 NOUVEAU_ERR("Failed to launch grid !\n");
690 nouveau_scratch_done(&nvc0->base);
691 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_DESC);
692 }
693
694
695 #define NVE4_TIC_ENTRY_INVALID 0x000fffff
696
697 static void
698 nve4_compute_validate_textures(struct nvc0_context *nvc0)
699 {
700 struct nouveau_bo *txc = nvc0->screen->txc;
701 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
702 const unsigned s = 5;
703 unsigned i;
704 uint32_t commands[2][32];
705 unsigned n[2] = { 0, 0 };
706
707 for (i = 0; i < nvc0->num_textures[s]; ++i) {
708 struct nv50_tic_entry *tic = nv50_tic_entry(nvc0->textures[s][i]);
709 struct nv04_resource *res;
710 const bool dirty = !!(nvc0->textures_dirty[s] & (1 << i));
711
712 if (!tic) {
713 nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID;
714 continue;
715 }
716 res = nv04_resource(tic->pipe.texture);
717 nvc0_update_tic(nvc0, tic, res);
718
719 if (tic->id < 0) {
720 tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
721
722 PUSH_SPACE(push, 16);
723 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
724 PUSH_DATAh(push, txc->offset + (tic->id * 32));
725 PUSH_DATA (push, txc->offset + (tic->id * 32));
726 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
727 PUSH_DATA (push, 32);
728 PUSH_DATA (push, 1);
729 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 9);
730 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
731 PUSH_DATAp(push, &tic->tic[0], 8);
732
733 commands[0][n[0]++] = (tic->id << 4) | 1;
734 } else
735 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
736 commands[1][n[1]++] = (tic->id << 4) | 1;
737 }
738 nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
739
740 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
741 res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
742
743 nvc0->tex_handles[s][i] &= ~NVE4_TIC_ENTRY_INVALID;
744 nvc0->tex_handles[s][i] |= tic->id;
745 if (dirty)
746 BCTX_REFN(nvc0->bufctx_cp, CP_TEX(i), res, RD);
747 }
748 for (; i < nvc0->state.num_textures[s]; ++i) {
749 nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID;
750 nvc0->textures_dirty[s] |= 1 << i;
751 }
752
753 if (n[0]) {
754 BEGIN_NIC0(push, NVE4_CP(TIC_FLUSH), n[0]);
755 PUSH_DATAp(push, commands[0], n[0]);
756 }
757 if (n[1]) {
758 BEGIN_NIC0(push, NVE4_CP(TEX_CACHE_CTL), n[1]);
759 PUSH_DATAp(push, commands[1], n[1]);
760 }
761
762 nvc0->state.num_textures[s] = nvc0->num_textures[s];
763
764 /* Invalidate all 3D textures because they are aliased. */
765 for (int s = 0; s < 5; s++) {
766 for (int i = 0; i < nvc0->num_textures[s]; i++)
767 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
768 nvc0->textures_dirty[s] = ~0;
769 }
770 nvc0->dirty_3d |= NVC0_NEW_3D_TEXTURES;
771 }
772
773
774 #ifdef DEBUG
775 static const char *nve4_cache_split_name(unsigned value)
776 {
777 switch (value) {
778 case NVC1_3D_CACHE_SPLIT_16K_SHARED_48K_L1: return "16K_SHARED_48K_L1";
779 case NVE4_3D_CACHE_SPLIT_32K_SHARED_32K_L1: return "32K_SHARED_32K_L1";
780 case NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1: return "48K_SHARED_16K_L1";
781 default:
782 return "(invalid)";
783 }
784 }
785
786 static void
787 nve4_compute_dump_launch_desc(const struct nve4_cp_launch_desc *desc)
788 {
789 const uint32_t *data = (const uint32_t *)desc;
790 unsigned i;
791 bool zero = false;
792
793 debug_printf("COMPUTE LAUNCH DESCRIPTOR:\n");
794
795 for (i = 0; i < sizeof(*desc); i += 4) {
796 if (data[i / 4]) {
797 debug_printf("[%x]: 0x%08x\n", i, data[i / 4]);
798 zero = false;
799 } else
800 if (!zero) {
801 debug_printf("...\n");
802 zero = true;
803 }
804 }
805
806 debug_printf("entry = 0x%x\n", desc->entry);
807 debug_printf("grid dimensions = %ux%ux%u\n",
808 desc->griddim_x, desc->griddim_y, desc->griddim_z);
809 debug_printf("block dimensions = %ux%ux%u\n",
810 desc->blockdim_x, desc->blockdim_y, desc->blockdim_z);
811 debug_printf("s[] size: 0x%x\n", desc->shared_size);
812 debug_printf("l[] size: -0x%x / +0x%x\n",
813 desc->local_size_n, desc->local_size_p);
814 debug_printf("stack size: 0x%x\n", desc->cstack_size);
815 debug_printf("barrier count: %u\n", desc->bar_alloc);
816 debug_printf("$r count: %u\n", desc->gpr_alloc);
817 debug_printf("cache split: %s\n", nve4_cache_split_name(desc->cache_split));
818
819 for (i = 0; i < 8; ++i) {
820 uint64_t address;
821 uint32_t size = desc->cb[i].size;
822 bool valid = !!(desc->cb_mask & (1 << i));
823
824 address = ((uint64_t)desc->cb[i].address_h << 32) | desc->cb[i].address_l;
825
826 if (!valid && !address && !size)
827 continue;
828 debug_printf("CB[%u]: address = 0x%"PRIx64", size 0x%x%s\n",
829 i, address, size, valid ? "" : " (invalid)");
830 }
831 }
832 #endif
833
834 #ifdef NOUVEAU_NVE4_MP_TRAP_HANDLER
835 static void
836 nve4_compute_trap_info(struct nvc0_context *nvc0)
837 {
838 struct nvc0_screen *screen = nvc0->screen;
839 struct nouveau_bo *bo = screen->parm;
840 int ret, i;
841 volatile struct nve4_mp_trap_info *info;
842 uint8_t *map;
843
844 ret = nouveau_bo_map(bo, NOUVEAU_BO_RDWR, nvc0->base.client);
845 if (ret)
846 return;
847 map = (uint8_t *)bo->map;
848 info = (volatile struct nve4_mp_trap_info *)(map + NVE4_CP_PARAM_TRAP_INFO);
849
850 if (info->lock) {
851 debug_printf("trapstat = %08x\n", info->trapstat);
852 debug_printf("warperr = %08x\n", info->warperr);
853 debug_printf("PC = %x\n", info->pc);
854 debug_printf("tid = %u %u %u\n",
855 info->tid[0], info->tid[1], info->tid[2]);
856 debug_printf("ctaid = %u %u %u\n",
857 info->ctaid[0], info->ctaid[1], info->ctaid[2]);
858 for (i = 0; i <= 63; ++i)
859 debug_printf("$r%i = %08x\n", i, info->r[i]);
860 for (i = 0; i <= 6; ++i)
861 debug_printf("$p%i = %i\n", i, (info->flags >> i) & 1);
862 debug_printf("$c = %x\n", info->flags >> 12);
863 }
864 info->lock = 0;
865 }
866 #endif