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gallium: add a cap for VIEWPORT_SUBPIXEL_BITS (v2)
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nve4_compute.c
1 /*
2 * Copyright 2012 Nouveau Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Christoph Bumiller
23 */
24
25 #include "nvc0/nvc0_context.h"
26 #include "nvc0/nve4_compute.h"
27
28 #include "codegen/nv50_ir_driver.h"
29
30 #ifdef DEBUG
31 static void nve4_compute_dump_launch_desc(const struct nve4_cp_launch_desc *);
32 #endif
33
34
35 int
36 nve4_screen_compute_setup(struct nvc0_screen *screen,
37 struct nouveau_pushbuf *push)
38 {
39 struct nouveau_device *dev = screen->base.device;
40 struct nouveau_object *chan = screen->base.channel;
41 int i;
42 int ret;
43 uint32_t obj_class;
44 uint64_t address;
45
46 switch (dev->chipset & ~0xf) {
47 case 0x100:
48 case 0xf0:
49 obj_class = NVF0_COMPUTE_CLASS; /* GK110 */
50 break;
51 case 0xe0:
52 obj_class = NVE4_COMPUTE_CLASS; /* GK104 */
53 break;
54 case 0x110:
55 obj_class = GM107_COMPUTE_CLASS;
56 break;
57 case 0x120:
58 obj_class = GM200_COMPUTE_CLASS;
59 break;
60 default:
61 NOUVEAU_ERR("unsupported chipset: NV%02x\n", dev->chipset);
62 return -1;
63 }
64
65 ret = nouveau_object_new(chan, 0xbeef00c0, obj_class, NULL, 0,
66 &screen->compute);
67 if (ret) {
68 NOUVEAU_ERR("Failed to allocate compute object: %d\n", ret);
69 return ret;
70 }
71
72 BEGIN_NVC0(push, SUBC_CP(NV01_SUBCHAN_OBJECT), 1);
73 PUSH_DATA (push, screen->compute->oclass);
74
75 BEGIN_NVC0(push, NVE4_CP(TEMP_ADDRESS_HIGH), 2);
76 PUSH_DATAh(push, screen->tls->offset);
77 PUSH_DATA (push, screen->tls->offset);
78 /* No idea why there are 2. Divide size by 2 to be safe.
79 * Actually this might be per-MP TEMP size and looks like I'm only using
80 * 2 MPs instead of all 8.
81 */
82 BEGIN_NVC0(push, NVE4_CP(MP_TEMP_SIZE_HIGH(0)), 3);
83 PUSH_DATAh(push, screen->tls->size / screen->mp_count);
84 PUSH_DATA (push, (screen->tls->size / screen->mp_count) & ~0x7fff);
85 PUSH_DATA (push, 0xff);
86 BEGIN_NVC0(push, NVE4_CP(MP_TEMP_SIZE_HIGH(1)), 3);
87 PUSH_DATAh(push, screen->tls->size / screen->mp_count);
88 PUSH_DATA (push, (screen->tls->size / screen->mp_count) & ~0x7fff);
89 PUSH_DATA (push, 0xff);
90
91 /* Unified address space ? Who needs that ? Certainly not OpenCL.
92 *
93 * FATAL: Buffers with addresses inside [0x1000000, 0x3000000] will NOT be
94 * accessible. We cannot prevent that at the moment, so expect failure.
95 */
96 BEGIN_NVC0(push, NVE4_CP(LOCAL_BASE), 1);
97 PUSH_DATA (push, 0xff << 24);
98 BEGIN_NVC0(push, NVE4_CP(SHARED_BASE), 1);
99 PUSH_DATA (push, 0xfe << 24);
100
101 BEGIN_NVC0(push, NVE4_CP(CODE_ADDRESS_HIGH), 2);
102 PUSH_DATAh(push, screen->text->offset);
103 PUSH_DATA (push, screen->text->offset);
104
105 BEGIN_NVC0(push, SUBC_CP(0x0310), 1);
106 PUSH_DATA (push, (obj_class >= NVF0_COMPUTE_CLASS) ? 0x400 : 0x300);
107
108 /* NOTE: these do not affect the state used by the 3D object */
109 BEGIN_NVC0(push, NVE4_CP(TIC_ADDRESS_HIGH), 3);
110 PUSH_DATAh(push, screen->txc->offset);
111 PUSH_DATA (push, screen->txc->offset);
112 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
113 BEGIN_NVC0(push, NVE4_CP(TSC_ADDRESS_HIGH), 3);
114 PUSH_DATAh(push, screen->txc->offset + 65536);
115 PUSH_DATA (push, screen->txc->offset + 65536);
116 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
117
118 if (obj_class >= NVF0_COMPUTE_CLASS) {
119 /* The blob calls GK110_COMPUTE.FIRMWARE[0x6], along with the args (0x1)
120 * passed with GK110_COMPUTE.GRAPH.SCRATCH[0x2]. This is currently
121 * disabled because our firmware doesn't support these commands and the
122 * GPU hangs if they are used. */
123 BEGIN_NIC0(push, SUBC_CP(0x0248), 64);
124 for (i = 63; i >= 0; i--)
125 PUSH_DATA(push, 0x38000 | i);
126 IMMED_NVC0(push, SUBC_CP(NV50_GRAPH_SERIALIZE), 0);
127 }
128
129 BEGIN_NVC0(push, NVE4_CP(TEX_CB_INDEX), 1);
130 PUSH_DATA (push, 7); /* does not interfere with 3D */
131
132 /* Disabling this UNK command avoid a read fault when using texelFetch()
133 * from a compute shader for weird reasons.
134 if (obj_class == NVF0_COMPUTE_CLASS)
135 IMMED_NVC0(push, SUBC_CP(0x02c4), 1);
136 */
137
138 address = screen->uniform_bo->offset + NVC0_CB_AUX_INFO(5);
139
140 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
141 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
142 PUSH_DATAh(push, address + NVC0_CB_AUX_MS_INFO);
143 PUSH_DATA (push, address + NVC0_CB_AUX_MS_INFO);
144 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
145 PUSH_DATA (push, 64);
146 PUSH_DATA (push, 1);
147 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 17);
148 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
149 PUSH_DATA (push, 0); /* 0 */
150 PUSH_DATA (push, 0);
151 PUSH_DATA (push, 1); /* 1 */
152 PUSH_DATA (push, 0);
153 PUSH_DATA (push, 0); /* 2 */
154 PUSH_DATA (push, 1);
155 PUSH_DATA (push, 1); /* 3 */
156 PUSH_DATA (push, 1);
157 PUSH_DATA (push, 2); /* 4 */
158 PUSH_DATA (push, 0);
159 PUSH_DATA (push, 3); /* 5 */
160 PUSH_DATA (push, 0);
161 PUSH_DATA (push, 2); /* 6 */
162 PUSH_DATA (push, 1);
163 PUSH_DATA (push, 3); /* 7 */
164 PUSH_DATA (push, 1);
165
166 #ifdef NOUVEAU_NVE4_MP_TRAP_HANDLER
167 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
168 PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_TRAP_INFO_PTR);
169 PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_TRAP_INFO_PTR);
170 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
171 PUSH_DATA (push, 28);
172 PUSH_DATA (push, 1);
173 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 8);
174 PUSH_DATA (push, 1);
175 PUSH_DATA (push, screen->parm->offset + NVE4_CP_PARAM_TRAP_INFO);
176 PUSH_DATAh(push, screen->parm->offset + NVE4_CP_PARAM_TRAP_INFO);
177 PUSH_DATA (push, screen->tls->offset);
178 PUSH_DATAh(push, screen->tls->offset);
179 PUSH_DATA (push, screen->tls->size / 2); /* MP TEMP block size */
180 PUSH_DATA (push, screen->tls->size / 2 / 64); /* warp TEMP block size */
181 PUSH_DATA (push, 0); /* warp cfstack size */
182 #endif
183
184 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
185 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
186
187 return 0;
188 }
189
190 static void
191 gm107_compute_validate_surfaces(struct nvc0_context *nvc0,
192 struct pipe_image_view *view, int slot)
193 {
194 struct nv04_resource *res = nv04_resource(view->resource);
195 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
196 struct nvc0_screen *screen = nvc0->screen;
197 struct nouveau_bo *txc = nvc0->screen->txc;
198 struct nv50_tic_entry *tic;
199 uint64_t address;
200 const int s = 5;
201
202 tic = nv50_tic_entry(nvc0->images_tic[s][slot]);
203
204 res = nv04_resource(tic->pipe.texture);
205 nvc0_update_tic(nvc0, tic, res);
206
207 if (tic->id < 0) {
208 tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
209
210 /* upload the texture view */
211 PUSH_SPACE(push, 16);
212 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
213 PUSH_DATAh(push, txc->offset + (tic->id * 32));
214 PUSH_DATA (push, txc->offset + (tic->id * 32));
215 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
216 PUSH_DATA (push, 32);
217 PUSH_DATA (push, 1);
218 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 9);
219 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
220 PUSH_DATAp(push, &tic->tic[0], 8);
221
222 BEGIN_NIC0(push, NVE4_CP(TIC_FLUSH), 1);
223 PUSH_DATA (push, (tic->id << 4) | 1);
224 } else
225 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
226 BEGIN_NIC0(push, NVE4_CP(TEX_CACHE_CTL), 1);
227 PUSH_DATA (push, (tic->id << 4) | 1);
228 }
229 nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
230
231 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
232 res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
233
234 BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RD);
235
236 address = screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
237
238 /* upload the texture handle */
239 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
240 PUSH_DATAh(push, address + NVC0_CB_AUX_TEX_INFO(slot + 32));
241 PUSH_DATA (push, address + NVC0_CB_AUX_TEX_INFO(slot + 32));
242 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
243 PUSH_DATA (push, 4);
244 PUSH_DATA (push, 0x1);
245 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 2);
246 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
247 PUSH_DATA (push, tic->id);
248
249 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
250 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
251 }
252
253 static void
254 nve4_compute_validate_surfaces(struct nvc0_context *nvc0)
255 {
256 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
257 uint64_t address;
258 const int s = 5;
259 int i, j;
260
261 if (!nvc0->images_dirty[s])
262 return;
263
264 address = nvc0->screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
265
266 for (i = 0; i < NVC0_MAX_IMAGES; ++i) {
267 struct pipe_image_view *view = &nvc0->images[s][i];
268
269 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
270 PUSH_DATAh(push, address + NVC0_CB_AUX_SU_INFO(i));
271 PUSH_DATA (push, address + NVC0_CB_AUX_SU_INFO(i));
272 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
273 PUSH_DATA (push, 16 * 4);
274 PUSH_DATA (push, 0x1);
275 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 16);
276 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
277
278 if (view->resource) {
279 struct nv04_resource *res = nv04_resource(view->resource);
280
281 if (res->base.target == PIPE_BUFFER) {
282 if (view->access & PIPE_IMAGE_ACCESS_WRITE)
283 nvc0_mark_image_range_valid(view);
284 }
285
286 nve4_set_surface_info(push, view, nvc0);
287 BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RDWR);
288
289 if (nvc0->screen->base.class_3d >= GM107_3D_CLASS)
290 gm107_compute_validate_surfaces(nvc0, view, i);
291 } else {
292 for (j = 0; j < 16; j++)
293 PUSH_DATA(push, 0);
294 }
295 }
296 }
297
298 /* Thankfully, textures with samplers follow the normal rules. */
299 static void
300 nve4_compute_validate_samplers(struct nvc0_context *nvc0)
301 {
302 bool need_flush = nve4_validate_tsc(nvc0, 5);
303 if (need_flush) {
304 BEGIN_NVC0(nvc0->base.pushbuf, NVE4_CP(TSC_FLUSH), 1);
305 PUSH_DATA (nvc0->base.pushbuf, 0);
306 }
307 }
308 /* (Code duplicated at bottom for various non-convincing reasons.
309 * E.g. we might want to use the COMPUTE subchannel to upload TIC/TSC
310 * entries to avoid a subchannel switch.
311 * Same for texture cache flushes.
312 * Also, the bufctx differs, and more IFs in the 3D version looks ugly.)
313 */
314 static void nve4_compute_validate_textures(struct nvc0_context *);
315
316 static void
317 nve4_compute_set_tex_handles(struct nvc0_context *nvc0)
318 {
319 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
320 struct nvc0_screen *screen = nvc0->screen;
321 uint64_t address;
322 const unsigned s = nvc0_shader_stage(PIPE_SHADER_COMPUTE);
323 unsigned i, n;
324 uint32_t dirty = nvc0->textures_dirty[s] | nvc0->samplers_dirty[s];
325
326 if (!dirty)
327 return;
328 i = ffs(dirty) - 1;
329 n = util_logbase2(dirty) + 1 - i;
330 assert(n);
331
332 address = screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
333
334 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
335 PUSH_DATAh(push, address + NVC0_CB_AUX_TEX_INFO(i));
336 PUSH_DATA (push, address + NVC0_CB_AUX_TEX_INFO(i));
337 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
338 PUSH_DATA (push, n * 4);
339 PUSH_DATA (push, 0x1);
340 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + n);
341 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
342 PUSH_DATAp(push, &nvc0->tex_handles[s][i], n);
343
344 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
345 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
346
347 nvc0->textures_dirty[s] = 0;
348 nvc0->samplers_dirty[s] = 0;
349 }
350
351 static void
352 nve4_compute_validate_constbufs(struct nvc0_context *nvc0)
353 {
354 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
355 const int s = 5;
356
357 while (nvc0->constbuf_dirty[s]) {
358 int i = ffs(nvc0->constbuf_dirty[s]) - 1;
359 nvc0->constbuf_dirty[s] &= ~(1 << i);
360
361 if (nvc0->constbuf[s][i].user) {
362 struct nouveau_bo *bo = nvc0->screen->uniform_bo;
363 const unsigned base = NVC0_CB_USR_INFO(s);
364 const unsigned size = nvc0->constbuf[s][0].size;
365 assert(i == 0); /* we really only want OpenGL uniforms here */
366 assert(nvc0->constbuf[s][0].u.data);
367
368 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
369 PUSH_DATAh(push, bo->offset + base);
370 PUSH_DATA (push, bo->offset + base);
371 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
372 PUSH_DATA (push, size);
373 PUSH_DATA (push, 0x1);
374 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (size / 4));
375 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
376 PUSH_DATAp(push, nvc0->constbuf[s][0].u.data, size / 4);
377 }
378 else {
379 struct nv04_resource *res =
380 nv04_resource(nvc0->constbuf[s][i].u.buf);
381 if (res) {
382 uint64_t address
383 = nvc0->screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
384
385 assert(i > 0); /* we really only want uniform buffer objects */
386
387 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
388 PUSH_DATAh(push, address + NVC0_CB_AUX_UBO_INFO(i - 1));
389 PUSH_DATA (push, address + NVC0_CB_AUX_UBO_INFO(i - 1));
390 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
391 PUSH_DATA (push, 4 * 4);
392 PUSH_DATA (push, 0x1);
393 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 4);
394 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
395
396 PUSH_DATA (push, res->address + nvc0->constbuf[s][i].offset);
397 PUSH_DATAh(push, res->address + nvc0->constbuf[s][i].offset);
398 PUSH_DATA (push, nvc0->constbuf[5][i].size);
399 PUSH_DATA (push, 0);
400 BCTX_REFN(nvc0->bufctx_cp, CP_CB(i), res, RD);
401
402 res->cb_bindings[s] |= 1 << i;
403 }
404 }
405 }
406
407 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
408 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
409 }
410
411 static void
412 nve4_compute_validate_buffers(struct nvc0_context *nvc0)
413 {
414 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
415 uint64_t address;
416 const int s = 5;
417 int i;
418
419 address = nvc0->screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
420
421 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
422 PUSH_DATAh(push, address + NVC0_CB_AUX_BUF_INFO(0));
423 PUSH_DATA (push, address + NVC0_CB_AUX_BUF_INFO(0));
424 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
425 PUSH_DATA (push, 4 * NVC0_MAX_BUFFERS * 4);
426 PUSH_DATA (push, 0x1);
427 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 4 * NVC0_MAX_BUFFERS);
428 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
429
430 for (i = 0; i < NVC0_MAX_BUFFERS; i++) {
431 if (nvc0->buffers[s][i].buffer) {
432 struct nv04_resource *res =
433 nv04_resource(nvc0->buffers[s][i].buffer);
434 PUSH_DATA (push, res->address + nvc0->buffers[s][i].buffer_offset);
435 PUSH_DATAh(push, res->address + nvc0->buffers[s][i].buffer_offset);
436 PUSH_DATA (push, nvc0->buffers[s][i].buffer_size);
437 PUSH_DATA (push, 0);
438 BCTX_REFN(nvc0->bufctx_cp, CP_BUF, res, RDWR);
439 util_range_add(&res->valid_buffer_range,
440 nvc0->buffers[s][i].buffer_offset,
441 nvc0->buffers[s][i].buffer_size);
442 } else {
443 PUSH_DATA (push, 0);
444 PUSH_DATA (push, 0);
445 PUSH_DATA (push, 0);
446 PUSH_DATA (push, 0);
447 }
448 }
449 }
450
451 static struct nvc0_state_validate
452 validate_list_cp[] = {
453 { nvc0_compprog_validate, NVC0_NEW_CP_PROGRAM },
454 { nve4_compute_validate_textures, NVC0_NEW_CP_TEXTURES },
455 { nve4_compute_validate_samplers, NVC0_NEW_CP_SAMPLERS },
456 { nve4_compute_set_tex_handles, NVC0_NEW_CP_TEXTURES |
457 NVC0_NEW_CP_SAMPLERS },
458 { nve4_compute_validate_surfaces, NVC0_NEW_CP_SURFACES },
459 { nvc0_compute_validate_globals, NVC0_NEW_CP_GLOBALS },
460 { nve4_compute_validate_buffers, NVC0_NEW_CP_BUFFERS },
461 { nve4_compute_validate_constbufs, NVC0_NEW_CP_CONSTBUF },
462 };
463
464 static bool
465 nve4_state_validate_cp(struct nvc0_context *nvc0, uint32_t mask)
466 {
467 bool ret;
468
469 ret = nvc0_state_validate(nvc0, mask, validate_list_cp,
470 ARRAY_SIZE(validate_list_cp), &nvc0->dirty_cp,
471 nvc0->bufctx_cp);
472
473 if (unlikely(nvc0->state.flushed))
474 nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, true);
475 return ret;
476 }
477
478 static void
479 nve4_compute_upload_input(struct nvc0_context *nvc0,
480 const struct pipe_grid_info *info)
481 {
482 struct nvc0_screen *screen = nvc0->screen;
483 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
484 struct nvc0_program *cp = nvc0->compprog;
485 uint64_t address;
486
487 address = screen->uniform_bo->offset + NVC0_CB_AUX_INFO(5);
488
489 if (cp->parm_size) {
490 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
491 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_USR_INFO(5));
492 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_USR_INFO(5));
493 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
494 PUSH_DATA (push, cp->parm_size);
495 PUSH_DATA (push, 0x1);
496 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (cp->parm_size / 4));
497 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
498 PUSH_DATAp(push, info->input, cp->parm_size / 4);
499 }
500 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
501 PUSH_DATAh(push, address + NVC0_CB_AUX_GRID_INFO(0));
502 PUSH_DATA (push, address + NVC0_CB_AUX_GRID_INFO(0));
503 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
504 PUSH_DATA (push, 8 * 4);
505 PUSH_DATA (push, 0x1);
506
507 if (unlikely(info->indirect)) {
508 struct nv04_resource *res = nv04_resource(info->indirect);
509 uint32_t offset = res->offset + info->indirect_offset;
510
511 nouveau_pushbuf_space(push, 16, 0, 1);
512 PUSH_REFN(push, res->bo, NOUVEAU_BO_RD | res->domain);
513
514 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 8);
515 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
516 PUSH_DATAp(push, info->block, 3);
517 nouveau_pushbuf_data(push, res->bo, offset,
518 NVC0_IB_ENTRY_1_NO_PREFETCH | 3 * 4);
519 } else {
520 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 8);
521 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
522 PUSH_DATAp(push, info->block, 3);
523 PUSH_DATAp(push, info->grid, 3);
524 }
525 PUSH_DATA (push, 0);
526 PUSH_DATA (push, info->work_dim);
527
528 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
529 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
530 }
531
532 static inline uint8_t
533 nve4_compute_derive_cache_split(struct nvc0_context *nvc0, uint32_t shared_size)
534 {
535 if (shared_size > (32 << 10))
536 return NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1;
537 if (shared_size > (16 << 10))
538 return NVE4_3D_CACHE_SPLIT_32K_SHARED_32K_L1;
539 return NVC1_3D_CACHE_SPLIT_16K_SHARED_48K_L1;
540 }
541
542 static void
543 nve4_compute_setup_launch_desc(struct nvc0_context *nvc0,
544 struct nve4_cp_launch_desc *desc,
545 const struct pipe_grid_info *info)
546 {
547 const struct nvc0_screen *screen = nvc0->screen;
548 const struct nvc0_program *cp = nvc0->compprog;
549
550 nve4_cp_launch_desc_init_default(desc);
551
552 desc->entry = nvc0_program_symbol_offset(cp, info->pc);
553
554 desc->griddim_x = info->grid[0];
555 desc->griddim_y = info->grid[1];
556 desc->griddim_z = info->grid[2];
557 desc->blockdim_x = info->block[0];
558 desc->blockdim_y = info->block[1];
559 desc->blockdim_z = info->block[2];
560
561 desc->shared_size = align(cp->cp.smem_size, 0x100);
562 desc->local_size_p = (cp->hdr[1] & 0xfffff0) + align(cp->cp.lmem_size, 0x10);
563 desc->local_size_n = 0;
564 desc->cstack_size = 0x800;
565 desc->cache_split = nve4_compute_derive_cache_split(nvc0, cp->cp.smem_size);
566
567 desc->gpr_alloc = cp->num_gprs;
568 desc->bar_alloc = cp->num_barriers;
569
570 // Only bind user uniforms and the driver constant buffer through the
571 // launch descriptor because UBOs are sticked to the driver cb to avoid the
572 // limitation of 8 CBs.
573 if (nvc0->constbuf[5][0].user || cp->parm_size) {
574 nve4_cp_launch_desc_set_cb(desc, 0, screen->uniform_bo,
575 NVC0_CB_USR_INFO(5), 1 << 16);
576 }
577 nve4_cp_launch_desc_set_cb(desc, 7, screen->uniform_bo,
578 NVC0_CB_AUX_INFO(5), 1 << 11);
579 }
580
581 static inline struct nve4_cp_launch_desc *
582 nve4_compute_alloc_launch_desc(struct nouveau_context *nv,
583 struct nouveau_bo **pbo, uint64_t *pgpuaddr)
584 {
585 uint8_t *ptr = nouveau_scratch_get(nv, 512, pgpuaddr, pbo);
586 if (!ptr)
587 return NULL;
588 if (*pgpuaddr & 255) {
589 unsigned adj = 256 - (*pgpuaddr & 255);
590 ptr += adj;
591 *pgpuaddr += adj;
592 }
593 return (struct nve4_cp_launch_desc *)ptr;
594 }
595
596 void
597 nve4_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
598 {
599 struct nvc0_context *nvc0 = nvc0_context(pipe);
600 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
601 struct nve4_cp_launch_desc *desc;
602 uint64_t desc_gpuaddr;
603 struct nouveau_bo *desc_bo;
604 int ret;
605
606 desc = nve4_compute_alloc_launch_desc(&nvc0->base, &desc_bo, &desc_gpuaddr);
607 if (!desc) {
608 ret = -1;
609 goto out;
610 }
611 BCTX_REFN_bo(nvc0->bufctx_cp, CP_DESC, NOUVEAU_BO_GART | NOUVEAU_BO_RD,
612 desc_bo);
613
614 ret = !nve4_state_validate_cp(nvc0, ~0);
615 if (ret)
616 goto out;
617
618 nve4_compute_setup_launch_desc(nvc0, desc, info);
619
620 nve4_compute_upload_input(nvc0, info);
621
622 #ifdef DEBUG
623 if (debug_get_num_option("NV50_PROG_DEBUG", 0))
624 nve4_compute_dump_launch_desc(desc);
625 #endif
626
627 if (unlikely(info->indirect)) {
628 struct nv04_resource *res = nv04_resource(info->indirect);
629 uint32_t offset = res->offset + info->indirect_offset;
630
631 /* upload the descriptor */
632 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
633 PUSH_DATAh(push, desc_gpuaddr);
634 PUSH_DATA (push, desc_gpuaddr);
635 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
636 PUSH_DATA (push, 256);
637 PUSH_DATA (push, 1);
638 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (256 / 4));
639 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x08 << 1));
640 PUSH_DATAp(push, (const uint32_t *)desc, 256 / 4);
641
642 /* overwrite griddim_x and griddim_y as two 32-bits integers even
643 * if griddim_y must be a 16-bits integer */
644 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
645 PUSH_DATAh(push, desc_gpuaddr + 48);
646 PUSH_DATA (push, desc_gpuaddr + 48);
647 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
648 PUSH_DATA (push, 8);
649 PUSH_DATA (push, 1);
650
651 nouveau_pushbuf_space(push, 16, 0, 1);
652 PUSH_REFN(push, res->bo, NOUVEAU_BO_RD | res->domain);
653
654 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (8 / 4));
655 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x08 << 1));
656 nouveau_pushbuf_data(push, res->bo, offset,
657 NVC0_IB_ENTRY_1_NO_PREFETCH | 2 * 4);
658
659 /* overwrite the 16 high bits of griddim_y with griddim_z because
660 * we need (z << 16) | x */
661 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
662 PUSH_DATAh(push, desc_gpuaddr + 54);
663 PUSH_DATA (push, desc_gpuaddr + 54);
664 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
665 PUSH_DATA (push, 4);
666 PUSH_DATA (push, 1);
667 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (4 / 4));
668 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x08 << 1));
669 nouveau_pushbuf_data(push, res->bo, offset + 8,
670 NVC0_IB_ENTRY_1_NO_PREFETCH | 1 * 4);
671 }
672
673 /* upload descriptor and flush */
674 BEGIN_NVC0(push, NVE4_CP(LAUNCH_DESC_ADDRESS), 1);
675 PUSH_DATA (push, desc_gpuaddr >> 8);
676 BEGIN_NVC0(push, NVE4_CP(LAUNCH), 1);
677 PUSH_DATA (push, 0x3);
678 BEGIN_NVC0(push, SUBC_CP(NV50_GRAPH_SERIALIZE), 1);
679 PUSH_DATA (push, 0);
680
681 out:
682 if (ret)
683 NOUVEAU_ERR("Failed to launch grid !\n");
684 nouveau_scratch_done(&nvc0->base);
685 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_DESC);
686 }
687
688
689 #define NVE4_TIC_ENTRY_INVALID 0x000fffff
690
691 static void
692 nve4_compute_validate_textures(struct nvc0_context *nvc0)
693 {
694 struct nouveau_bo *txc = nvc0->screen->txc;
695 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
696 const unsigned s = 5;
697 unsigned i;
698 uint32_t commands[2][32];
699 unsigned n[2] = { 0, 0 };
700
701 for (i = 0; i < nvc0->num_textures[s]; ++i) {
702 struct nv50_tic_entry *tic = nv50_tic_entry(nvc0->textures[s][i]);
703 struct nv04_resource *res;
704 const bool dirty = !!(nvc0->textures_dirty[s] & (1 << i));
705
706 if (!tic) {
707 nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID;
708 continue;
709 }
710 res = nv04_resource(tic->pipe.texture);
711 nvc0_update_tic(nvc0, tic, res);
712
713 if (tic->id < 0) {
714 tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
715
716 PUSH_SPACE(push, 16);
717 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
718 PUSH_DATAh(push, txc->offset + (tic->id * 32));
719 PUSH_DATA (push, txc->offset + (tic->id * 32));
720 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
721 PUSH_DATA (push, 32);
722 PUSH_DATA (push, 1);
723 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 9);
724 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
725 PUSH_DATAp(push, &tic->tic[0], 8);
726
727 commands[0][n[0]++] = (tic->id << 4) | 1;
728 } else
729 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
730 commands[1][n[1]++] = (tic->id << 4) | 1;
731 }
732 nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
733
734 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
735 res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
736
737 nvc0->tex_handles[s][i] &= ~NVE4_TIC_ENTRY_INVALID;
738 nvc0->tex_handles[s][i] |= tic->id;
739 if (dirty)
740 BCTX_REFN(nvc0->bufctx_cp, CP_TEX(i), res, RD);
741 }
742 for (; i < nvc0->state.num_textures[s]; ++i) {
743 nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID;
744 nvc0->textures_dirty[s] |= 1 << i;
745 }
746
747 if (n[0]) {
748 BEGIN_NIC0(push, NVE4_CP(TIC_FLUSH), n[0]);
749 PUSH_DATAp(push, commands[0], n[0]);
750 }
751 if (n[1]) {
752 BEGIN_NIC0(push, NVE4_CP(TEX_CACHE_CTL), n[1]);
753 PUSH_DATAp(push, commands[1], n[1]);
754 }
755
756 nvc0->state.num_textures[s] = nvc0->num_textures[s];
757 }
758
759
760 #ifdef DEBUG
761 static const char *nve4_cache_split_name(unsigned value)
762 {
763 switch (value) {
764 case NVC1_3D_CACHE_SPLIT_16K_SHARED_48K_L1: return "16K_SHARED_48K_L1";
765 case NVE4_3D_CACHE_SPLIT_32K_SHARED_32K_L1: return "32K_SHARED_32K_L1";
766 case NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1: return "48K_SHARED_16K_L1";
767 default:
768 return "(invalid)";
769 }
770 }
771
772 static void
773 nve4_compute_dump_launch_desc(const struct nve4_cp_launch_desc *desc)
774 {
775 const uint32_t *data = (const uint32_t *)desc;
776 unsigned i;
777 bool zero = false;
778
779 debug_printf("COMPUTE LAUNCH DESCRIPTOR:\n");
780
781 for (i = 0; i < sizeof(*desc); i += 4) {
782 if (data[i / 4]) {
783 debug_printf("[%x]: 0x%08x\n", i, data[i / 4]);
784 zero = false;
785 } else
786 if (!zero) {
787 debug_printf("...\n");
788 zero = true;
789 }
790 }
791
792 debug_printf("entry = 0x%x\n", desc->entry);
793 debug_printf("grid dimensions = %ux%ux%u\n",
794 desc->griddim_x, desc->griddim_y, desc->griddim_z);
795 debug_printf("block dimensions = %ux%ux%u\n",
796 desc->blockdim_x, desc->blockdim_y, desc->blockdim_z);
797 debug_printf("s[] size: 0x%x\n", desc->shared_size);
798 debug_printf("l[] size: -0x%x / +0x%x\n",
799 desc->local_size_n, desc->local_size_p);
800 debug_printf("stack size: 0x%x\n", desc->cstack_size);
801 debug_printf("barrier count: %u\n", desc->bar_alloc);
802 debug_printf("$r count: %u\n", desc->gpr_alloc);
803 debug_printf("cache split: %s\n", nve4_cache_split_name(desc->cache_split));
804
805 for (i = 0; i < 8; ++i) {
806 uint64_t address;
807 uint32_t size = desc->cb[i].size;
808 bool valid = !!(desc->cb_mask & (1 << i));
809
810 address = ((uint64_t)desc->cb[i].address_h << 32) | desc->cb[i].address_l;
811
812 if (!valid && !address && !size)
813 continue;
814 debug_printf("CB[%u]: address = 0x%"PRIx64", size 0x%x%s\n",
815 i, address, size, valid ? "" : " (invalid)");
816 }
817 }
818 #endif
819
820 #ifdef NOUVEAU_NVE4_MP_TRAP_HANDLER
821 static void
822 nve4_compute_trap_info(struct nvc0_context *nvc0)
823 {
824 struct nvc0_screen *screen = nvc0->screen;
825 struct nouveau_bo *bo = screen->parm;
826 int ret, i;
827 volatile struct nve4_mp_trap_info *info;
828 uint8_t *map;
829
830 ret = nouveau_bo_map(bo, NOUVEAU_BO_RDWR, nvc0->base.client);
831 if (ret)
832 return;
833 map = (uint8_t *)bo->map;
834 info = (volatile struct nve4_mp_trap_info *)(map + NVE4_CP_PARAM_TRAP_INFO);
835
836 if (info->lock) {
837 debug_printf("trapstat = %08x\n", info->trapstat);
838 debug_printf("warperr = %08x\n", info->warperr);
839 debug_printf("PC = %x\n", info->pc);
840 debug_printf("tid = %u %u %u\n",
841 info->tid[0], info->tid[1], info->tid[2]);
842 debug_printf("ctaid = %u %u %u\n",
843 info->ctaid[0], info->ctaid[1], info->ctaid[2]);
844 for (i = 0; i <= 63; ++i)
845 debug_printf("$r%i = %08x\n", i, info->r[i]);
846 for (i = 0; i <= 6; ++i)
847 debug_printf("$p%i = %i\n", i, (info->flags >> i) & 1);
848 debug_printf("$c = %x\n", info->flags >> 12);
849 }
850 info->lock = 0;
851 }
852 #endif