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nvc0: add support for handling indirect draws with attrib conversion
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nve4_compute.c
1 /*
2 * Copyright 2012 Nouveau Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Christoph Bumiller
23 */
24
25 #include "nvc0/nvc0_context.h"
26 #include "nvc0/nve4_compute.h"
27
28 #include "codegen/nv50_ir_driver.h"
29
30 #ifdef DEBUG
31 static void nve4_compute_dump_launch_desc(const struct nve4_cp_launch_desc *);
32 static void gp100_compute_dump_launch_desc(const struct gp100_cp_launch_desc *);
33 #endif
34
35
36 int
37 nve4_screen_compute_setup(struct nvc0_screen *screen,
38 struct nouveau_pushbuf *push)
39 {
40 struct nouveau_device *dev = screen->base.device;
41 struct nouveau_object *chan = screen->base.channel;
42 int i;
43 int ret;
44 uint32_t obj_class;
45 uint64_t address;
46
47 switch (dev->chipset & ~0xf) {
48 case 0x100:
49 case 0xf0:
50 obj_class = NVF0_COMPUTE_CLASS; /* GK110 */
51 break;
52 case 0xe0:
53 obj_class = NVE4_COMPUTE_CLASS; /* GK104 */
54 break;
55 case 0x110:
56 obj_class = GM107_COMPUTE_CLASS;
57 break;
58 case 0x120:
59 obj_class = GM200_COMPUTE_CLASS;
60 break;
61 case 0x130:
62 obj_class = (dev->chipset == 0x130 || dev->chipset == 0x13b) ?
63 GP100_COMPUTE_CLASS : GP104_COMPUTE_CLASS;
64 break;
65 default:
66 NOUVEAU_ERR("unsupported chipset: NV%02x\n", dev->chipset);
67 return -1;
68 }
69
70 ret = nouveau_object_new(chan, 0xbeef00c0, obj_class, NULL, 0,
71 &screen->compute);
72 if (ret) {
73 NOUVEAU_ERR("Failed to allocate compute object: %d\n", ret);
74 return ret;
75 }
76
77 BEGIN_NVC0(push, SUBC_CP(NV01_SUBCHAN_OBJECT), 1);
78 PUSH_DATA (push, screen->compute->oclass);
79
80 BEGIN_NVC0(push, NVE4_CP(TEMP_ADDRESS_HIGH), 2);
81 PUSH_DATAh(push, screen->tls->offset);
82 PUSH_DATA (push, screen->tls->offset);
83 /* No idea why there are 2. Divide size by 2 to be safe.
84 * Actually this might be per-MP TEMP size and looks like I'm only using
85 * 2 MPs instead of all 8.
86 */
87 BEGIN_NVC0(push, NVE4_CP(MP_TEMP_SIZE_HIGH(0)), 3);
88 PUSH_DATAh(push, screen->tls->size / screen->mp_count);
89 PUSH_DATA (push, (screen->tls->size / screen->mp_count) & ~0x7fff);
90 PUSH_DATA (push, 0xff);
91 BEGIN_NVC0(push, NVE4_CP(MP_TEMP_SIZE_HIGH(1)), 3);
92 PUSH_DATAh(push, screen->tls->size / screen->mp_count);
93 PUSH_DATA (push, (screen->tls->size / screen->mp_count) & ~0x7fff);
94 PUSH_DATA (push, 0xff);
95
96 /* Unified address space ? Who needs that ? Certainly not OpenCL.
97 *
98 * FATAL: Buffers with addresses inside [0x1000000, 0x3000000] will NOT be
99 * accessible. We cannot prevent that at the moment, so expect failure.
100 */
101 BEGIN_NVC0(push, NVE4_CP(LOCAL_BASE), 1);
102 PUSH_DATA (push, 0xff << 24);
103 BEGIN_NVC0(push, NVE4_CP(SHARED_BASE), 1);
104 PUSH_DATA (push, 0xfe << 24);
105
106 BEGIN_NVC0(push, NVE4_CP(CODE_ADDRESS_HIGH), 2);
107 PUSH_DATAh(push, screen->text->offset);
108 PUSH_DATA (push, screen->text->offset);
109
110 BEGIN_NVC0(push, SUBC_CP(0x0310), 1);
111 PUSH_DATA (push, (obj_class >= NVF0_COMPUTE_CLASS) ? 0x400 : 0x300);
112
113 /* NOTE: these do not affect the state used by the 3D object */
114 BEGIN_NVC0(push, NVE4_CP(TIC_ADDRESS_HIGH), 3);
115 PUSH_DATAh(push, screen->txc->offset);
116 PUSH_DATA (push, screen->txc->offset);
117 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
118 BEGIN_NVC0(push, NVE4_CP(TSC_ADDRESS_HIGH), 3);
119 PUSH_DATAh(push, screen->txc->offset + 65536);
120 PUSH_DATA (push, screen->txc->offset + 65536);
121 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
122
123 if (obj_class >= NVF0_COMPUTE_CLASS) {
124 /* The blob calls GK110_COMPUTE.FIRMWARE[0x6], along with the args (0x1)
125 * passed with GK110_COMPUTE.GRAPH.SCRATCH[0x2]. This is currently
126 * disabled because our firmware doesn't support these commands and the
127 * GPU hangs if they are used. */
128 BEGIN_NIC0(push, SUBC_CP(0x0248), 64);
129 for (i = 63; i >= 0; i--)
130 PUSH_DATA(push, 0x38000 | i);
131 IMMED_NVC0(push, SUBC_CP(NV50_GRAPH_SERIALIZE), 0);
132 }
133
134 BEGIN_NVC0(push, NVE4_CP(TEX_CB_INDEX), 1);
135 PUSH_DATA (push, 7); /* does not interfere with 3D */
136
137 /* Disabling this UNK command avoid a read fault when using texelFetch()
138 * from a compute shader for weird reasons.
139 if (obj_class == NVF0_COMPUTE_CLASS)
140 IMMED_NVC0(push, SUBC_CP(0x02c4), 1);
141 */
142
143 address = screen->uniform_bo->offset + NVC0_CB_AUX_INFO(5);
144
145 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
146 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
147 PUSH_DATAh(push, address + NVC0_CB_AUX_MS_INFO);
148 PUSH_DATA (push, address + NVC0_CB_AUX_MS_INFO);
149 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
150 PUSH_DATA (push, 64);
151 PUSH_DATA (push, 1);
152 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 17);
153 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
154 PUSH_DATA (push, 0); /* 0 */
155 PUSH_DATA (push, 0);
156 PUSH_DATA (push, 1); /* 1 */
157 PUSH_DATA (push, 0);
158 PUSH_DATA (push, 0); /* 2 */
159 PUSH_DATA (push, 1);
160 PUSH_DATA (push, 1); /* 3 */
161 PUSH_DATA (push, 1);
162 PUSH_DATA (push, 2); /* 4 */
163 PUSH_DATA (push, 0);
164 PUSH_DATA (push, 3); /* 5 */
165 PUSH_DATA (push, 0);
166 PUSH_DATA (push, 2); /* 6 */
167 PUSH_DATA (push, 1);
168 PUSH_DATA (push, 3); /* 7 */
169 PUSH_DATA (push, 1);
170
171 #ifdef NOUVEAU_NVE4_MP_TRAP_HANDLER
172 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
173 PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_TRAP_INFO_PTR);
174 PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_TRAP_INFO_PTR);
175 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
176 PUSH_DATA (push, 28);
177 PUSH_DATA (push, 1);
178 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 8);
179 PUSH_DATA (push, 1);
180 PUSH_DATA (push, screen->parm->offset + NVE4_CP_PARAM_TRAP_INFO);
181 PUSH_DATAh(push, screen->parm->offset + NVE4_CP_PARAM_TRAP_INFO);
182 PUSH_DATA (push, screen->tls->offset);
183 PUSH_DATAh(push, screen->tls->offset);
184 PUSH_DATA (push, screen->tls->size / 2); /* MP TEMP block size */
185 PUSH_DATA (push, screen->tls->size / 2 / 64); /* warp TEMP block size */
186 PUSH_DATA (push, 0); /* warp cfstack size */
187 #endif
188
189 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
190 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
191
192 return 0;
193 }
194
195 static void
196 gm107_compute_validate_surfaces(struct nvc0_context *nvc0,
197 struct pipe_image_view *view, int slot)
198 {
199 struct nv04_resource *res = nv04_resource(view->resource);
200 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
201 struct nvc0_screen *screen = nvc0->screen;
202 struct nouveau_bo *txc = nvc0->screen->txc;
203 struct nv50_tic_entry *tic;
204 uint64_t address;
205 const int s = 5;
206
207 tic = nv50_tic_entry(nvc0->images_tic[s][slot]);
208
209 res = nv04_resource(tic->pipe.texture);
210 nvc0_update_tic(nvc0, tic, res);
211
212 if (tic->id < 0) {
213 tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
214
215 /* upload the texture view */
216 PUSH_SPACE(push, 16);
217 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
218 PUSH_DATAh(push, txc->offset + (tic->id * 32));
219 PUSH_DATA (push, txc->offset + (tic->id * 32));
220 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
221 PUSH_DATA (push, 32);
222 PUSH_DATA (push, 1);
223 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 9);
224 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
225 PUSH_DATAp(push, &tic->tic[0], 8);
226
227 BEGIN_NIC0(push, NVE4_CP(TIC_FLUSH), 1);
228 PUSH_DATA (push, (tic->id << 4) | 1);
229 } else
230 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
231 BEGIN_NIC0(push, NVE4_CP(TEX_CACHE_CTL), 1);
232 PUSH_DATA (push, (tic->id << 4) | 1);
233 }
234 nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
235
236 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
237 res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
238
239 BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RD);
240
241 address = screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
242
243 /* upload the texture handle */
244 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
245 PUSH_DATAh(push, address + NVC0_CB_AUX_TEX_INFO(slot + 32));
246 PUSH_DATA (push, address + NVC0_CB_AUX_TEX_INFO(slot + 32));
247 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
248 PUSH_DATA (push, 4);
249 PUSH_DATA (push, 0x1);
250 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 2);
251 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
252 PUSH_DATA (push, tic->id);
253
254 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
255 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
256 }
257
258 static void
259 nve4_compute_validate_surfaces(struct nvc0_context *nvc0)
260 {
261 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
262 uint64_t address;
263 const int s = 5;
264 int i, j;
265
266 if (!nvc0->images_dirty[s])
267 return;
268
269 address = nvc0->screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
270
271 for (i = 0; i < NVC0_MAX_IMAGES; ++i) {
272 struct pipe_image_view *view = &nvc0->images[s][i];
273
274 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
275 PUSH_DATAh(push, address + NVC0_CB_AUX_SU_INFO(i));
276 PUSH_DATA (push, address + NVC0_CB_AUX_SU_INFO(i));
277 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
278 PUSH_DATA (push, 16 * 4);
279 PUSH_DATA (push, 0x1);
280 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 16);
281 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
282
283 if (view->resource) {
284 struct nv04_resource *res = nv04_resource(view->resource);
285
286 if (res->base.target == PIPE_BUFFER) {
287 if (view->access & PIPE_IMAGE_ACCESS_WRITE)
288 nvc0_mark_image_range_valid(view);
289 }
290
291 nve4_set_surface_info(push, view, nvc0);
292 BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RDWR);
293
294 if (nvc0->screen->base.class_3d >= GM107_3D_CLASS)
295 gm107_compute_validate_surfaces(nvc0, view, i);
296 } else {
297 for (j = 0; j < 16; j++)
298 PUSH_DATA(push, 0);
299 }
300 }
301 }
302
303 /* Thankfully, textures with samplers follow the normal rules. */
304 static void
305 nve4_compute_validate_samplers(struct nvc0_context *nvc0)
306 {
307 bool need_flush = nve4_validate_tsc(nvc0, 5);
308 if (need_flush) {
309 BEGIN_NVC0(nvc0->base.pushbuf, NVE4_CP(TSC_FLUSH), 1);
310 PUSH_DATA (nvc0->base.pushbuf, 0);
311 }
312
313 /* Invalidate all 3D samplers because they are aliased. */
314 for (int s = 0; s < 5; s++)
315 nvc0->samplers_dirty[s] = ~0;
316 nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLERS;
317 }
318
319 /* (Code duplicated at bottom for various non-convincing reasons.
320 * E.g. we might want to use the COMPUTE subchannel to upload TIC/TSC
321 * entries to avoid a subchannel switch.
322 * Same for texture cache flushes.
323 * Also, the bufctx differs, and more IFs in the 3D version looks ugly.)
324 */
325 static void nve4_compute_validate_textures(struct nvc0_context *);
326
327 static void
328 nve4_compute_set_tex_handles(struct nvc0_context *nvc0)
329 {
330 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
331 struct nvc0_screen *screen = nvc0->screen;
332 uint64_t address;
333 const unsigned s = nvc0_shader_stage(PIPE_SHADER_COMPUTE);
334 unsigned i, n;
335 uint32_t dirty = nvc0->textures_dirty[s] | nvc0->samplers_dirty[s];
336
337 if (!dirty)
338 return;
339 i = ffs(dirty) - 1;
340 n = util_logbase2(dirty) + 1 - i;
341 assert(n);
342
343 address = screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
344
345 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
346 PUSH_DATAh(push, address + NVC0_CB_AUX_TEX_INFO(i));
347 PUSH_DATA (push, address + NVC0_CB_AUX_TEX_INFO(i));
348 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
349 PUSH_DATA (push, n * 4);
350 PUSH_DATA (push, 0x1);
351 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + n);
352 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
353 PUSH_DATAp(push, &nvc0->tex_handles[s][i], n);
354
355 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
356 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
357
358 nvc0->textures_dirty[s] = 0;
359 nvc0->samplers_dirty[s] = 0;
360 }
361
362 static void
363 nve4_compute_validate_constbufs(struct nvc0_context *nvc0)
364 {
365 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
366 const int s = 5;
367
368 while (nvc0->constbuf_dirty[s]) {
369 int i = ffs(nvc0->constbuf_dirty[s]) - 1;
370 nvc0->constbuf_dirty[s] &= ~(1 << i);
371
372 if (nvc0->constbuf[s][i].user) {
373 struct nouveau_bo *bo = nvc0->screen->uniform_bo;
374 const unsigned base = NVC0_CB_USR_INFO(s);
375 const unsigned size = nvc0->constbuf[s][0].size;
376 assert(i == 0); /* we really only want OpenGL uniforms here */
377 assert(nvc0->constbuf[s][0].u.data);
378
379 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
380 PUSH_DATAh(push, bo->offset + base);
381 PUSH_DATA (push, bo->offset + base);
382 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
383 PUSH_DATA (push, size);
384 PUSH_DATA (push, 0x1);
385 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (size / 4));
386 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
387 PUSH_DATAp(push, nvc0->constbuf[s][0].u.data, size / 4);
388 }
389 else {
390 struct nv04_resource *res =
391 nv04_resource(nvc0->constbuf[s][i].u.buf);
392 if (res) {
393 uint64_t address
394 = nvc0->screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
395
396 assert(i > 0); /* we really only want uniform buffer objects */
397
398 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
399 PUSH_DATAh(push, address + NVC0_CB_AUX_UBO_INFO(i - 1));
400 PUSH_DATA (push, address + NVC0_CB_AUX_UBO_INFO(i - 1));
401 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
402 PUSH_DATA (push, 4 * 4);
403 PUSH_DATA (push, 0x1);
404 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 4);
405 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
406
407 PUSH_DATA (push, res->address + nvc0->constbuf[s][i].offset);
408 PUSH_DATAh(push, res->address + nvc0->constbuf[s][i].offset);
409 PUSH_DATA (push, nvc0->constbuf[5][i].size);
410 PUSH_DATA (push, 0);
411 BCTX_REFN(nvc0->bufctx_cp, CP_CB(i), res, RD);
412
413 res->cb_bindings[s] |= 1 << i;
414 }
415 }
416 }
417
418 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
419 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
420 }
421
422 static void
423 nve4_compute_validate_buffers(struct nvc0_context *nvc0)
424 {
425 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
426 uint64_t address;
427 const int s = 5;
428 int i;
429
430 address = nvc0->screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
431
432 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
433 PUSH_DATAh(push, address + NVC0_CB_AUX_BUF_INFO(0));
434 PUSH_DATA (push, address + NVC0_CB_AUX_BUF_INFO(0));
435 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
436 PUSH_DATA (push, 4 * NVC0_MAX_BUFFERS * 4);
437 PUSH_DATA (push, 0x1);
438 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 4 * NVC0_MAX_BUFFERS);
439 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
440
441 for (i = 0; i < NVC0_MAX_BUFFERS; i++) {
442 if (nvc0->buffers[s][i].buffer) {
443 struct nv04_resource *res =
444 nv04_resource(nvc0->buffers[s][i].buffer);
445 PUSH_DATA (push, res->address + nvc0->buffers[s][i].buffer_offset);
446 PUSH_DATAh(push, res->address + nvc0->buffers[s][i].buffer_offset);
447 PUSH_DATA (push, nvc0->buffers[s][i].buffer_size);
448 PUSH_DATA (push, 0);
449 BCTX_REFN(nvc0->bufctx_cp, CP_BUF, res, RDWR);
450 util_range_add(&res->valid_buffer_range,
451 nvc0->buffers[s][i].buffer_offset,
452 nvc0->buffers[s][i].buffer_offset +
453 nvc0->buffers[s][i].buffer_size);
454 } else {
455 PUSH_DATA (push, 0);
456 PUSH_DATA (push, 0);
457 PUSH_DATA (push, 0);
458 PUSH_DATA (push, 0);
459 }
460 }
461 }
462
463 static struct nvc0_state_validate
464 validate_list_cp[] = {
465 { nvc0_compprog_validate, NVC0_NEW_CP_PROGRAM },
466 { nve4_compute_validate_textures, NVC0_NEW_CP_TEXTURES },
467 { nve4_compute_validate_samplers, NVC0_NEW_CP_SAMPLERS },
468 { nve4_compute_set_tex_handles, NVC0_NEW_CP_TEXTURES |
469 NVC0_NEW_CP_SAMPLERS },
470 { nve4_compute_validate_surfaces, NVC0_NEW_CP_SURFACES },
471 { nvc0_compute_validate_globals, NVC0_NEW_CP_GLOBALS },
472 { nve4_compute_validate_buffers, NVC0_NEW_CP_BUFFERS },
473 { nve4_compute_validate_constbufs, NVC0_NEW_CP_CONSTBUF },
474 };
475
476 static bool
477 nve4_state_validate_cp(struct nvc0_context *nvc0, uint32_t mask)
478 {
479 bool ret;
480
481 ret = nvc0_state_validate(nvc0, mask, validate_list_cp,
482 ARRAY_SIZE(validate_list_cp), &nvc0->dirty_cp,
483 nvc0->bufctx_cp);
484
485 if (unlikely(nvc0->state.flushed))
486 nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, true);
487 return ret;
488 }
489
490 static void
491 nve4_compute_upload_input(struct nvc0_context *nvc0,
492 const struct pipe_grid_info *info)
493 {
494 struct nvc0_screen *screen = nvc0->screen;
495 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
496 struct nvc0_program *cp = nvc0->compprog;
497 uint64_t address;
498
499 address = screen->uniform_bo->offset + NVC0_CB_AUX_INFO(5);
500
501 if (cp->parm_size) {
502 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
503 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_USR_INFO(5));
504 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_USR_INFO(5));
505 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
506 PUSH_DATA (push, cp->parm_size);
507 PUSH_DATA (push, 0x1);
508 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (cp->parm_size / 4));
509 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
510 PUSH_DATAp(push, info->input, cp->parm_size / 4);
511 }
512 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
513 PUSH_DATAh(push, address + NVC0_CB_AUX_GRID_INFO(0));
514 PUSH_DATA (push, address + NVC0_CB_AUX_GRID_INFO(0));
515 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
516 PUSH_DATA (push, 8 * 4);
517 PUSH_DATA (push, 0x1);
518
519 if (unlikely(info->indirect)) {
520 struct nv04_resource *res = nv04_resource(info->indirect);
521 uint32_t offset = res->offset + info->indirect_offset;
522
523 nouveau_pushbuf_space(push, 32, 0, 1);
524 PUSH_REFN(push, res->bo, NOUVEAU_BO_RD | res->domain);
525
526 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 8);
527 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
528 PUSH_DATAp(push, info->block, 3);
529 nouveau_pushbuf_data(push, res->bo, offset,
530 NVC0_IB_ENTRY_1_NO_PREFETCH | 3 * 4);
531 } else {
532 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 8);
533 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
534 PUSH_DATAp(push, info->block, 3);
535 PUSH_DATAp(push, info->grid, 3);
536 }
537 PUSH_DATA (push, 0);
538 PUSH_DATA (push, info->work_dim);
539
540 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
541 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
542 }
543
544 static inline uint8_t
545 nve4_compute_derive_cache_split(struct nvc0_context *nvc0, uint32_t shared_size)
546 {
547 if (shared_size > (32 << 10))
548 return NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1;
549 if (shared_size > (16 << 10))
550 return NVE4_3D_CACHE_SPLIT_32K_SHARED_32K_L1;
551 return NVC1_3D_CACHE_SPLIT_16K_SHARED_48K_L1;
552 }
553
554 static void
555 nve4_compute_setup_buf_cb(struct nvc0_context *nvc0, bool gp100, void *desc)
556 {
557 // only user constant buffers 1-6 can be put in the descriptor, the rest are
558 // loaded through global memory
559 for (int i = 1; i <= 6; i++) {
560 if (nvc0->constbuf[5][i].user || !nvc0->constbuf[5][i].u.buf)
561 continue;
562
563 struct nv04_resource *res =
564 nv04_resource(nvc0->constbuf[5][i].u.buf);
565
566 uint32_t base = res->offset + nvc0->constbuf[5][i].offset;
567 uint32_t size = nvc0->constbuf[5][i].size;
568 if (gp100)
569 gp100_cp_launch_desc_set_cb(desc, i, res->bo, base, size);
570 else
571 nve4_cp_launch_desc_set_cb(desc, i, res->bo, base, size);
572 }
573
574 // there is no need to do FLUSH(NVE4_COMPUTE_FLUSH_CB) because
575 // nve4_compute_upload_input() does it later
576 }
577
578 static void
579 nve4_compute_setup_launch_desc(struct nvc0_context *nvc0,
580 struct nve4_cp_launch_desc *desc,
581 const struct pipe_grid_info *info)
582 {
583 const struct nvc0_screen *screen = nvc0->screen;
584 const struct nvc0_program *cp = nvc0->compprog;
585
586 nve4_cp_launch_desc_init_default(desc);
587
588 desc->entry = nvc0_program_symbol_offset(cp, info->pc);
589
590 desc->griddim_x = info->grid[0];
591 desc->griddim_y = info->grid[1];
592 desc->griddim_z = info->grid[2];
593 desc->blockdim_x = info->block[0];
594 desc->blockdim_y = info->block[1];
595 desc->blockdim_z = info->block[2];
596
597 desc->shared_size = align(cp->cp.smem_size, 0x100);
598 desc->local_size_p = (cp->hdr[1] & 0xfffff0) + align(cp->cp.lmem_size, 0x10);
599 desc->local_size_n = 0;
600 desc->cstack_size = 0x800;
601 desc->cache_split = nve4_compute_derive_cache_split(nvc0, cp->cp.smem_size);
602
603 desc->gpr_alloc = cp->num_gprs;
604 desc->bar_alloc = cp->num_barriers;
605
606 // Only bind user uniforms and the driver constant buffer through the
607 // launch descriptor because UBOs are sticked to the driver cb to avoid the
608 // limitation of 8 CBs.
609 if (nvc0->constbuf[5][0].user || cp->parm_size) {
610 nve4_cp_launch_desc_set_cb(desc, 0, screen->uniform_bo,
611 NVC0_CB_USR_INFO(5), 1 << 16);
612 }
613 nve4_cp_launch_desc_set_cb(desc, 7, screen->uniform_bo,
614 NVC0_CB_AUX_INFO(5), 1 << 11);
615
616 nve4_compute_setup_buf_cb(nvc0, false, desc);
617 }
618
619 static void
620 gp100_compute_setup_launch_desc(struct nvc0_context *nvc0,
621 struct gp100_cp_launch_desc *desc,
622 const struct pipe_grid_info *info)
623 {
624 const struct nvc0_screen *screen = nvc0->screen;
625 const struct nvc0_program *cp = nvc0->compprog;
626
627 gp100_cp_launch_desc_init_default(desc);
628
629 desc->entry = nvc0_program_symbol_offset(cp, info->pc);
630
631 desc->griddim_x = info->grid[0];
632 desc->griddim_y = info->grid[1];
633 desc->griddim_z = info->grid[2];
634 desc->blockdim_x = info->block[0];
635 desc->blockdim_y = info->block[1];
636 desc->blockdim_z = info->block[2];
637
638 desc->shared_size = align(cp->cp.smem_size, 0x100);
639 desc->local_size_p = (cp->hdr[1] & 0xfffff0) + align(cp->cp.lmem_size, 0x10);
640 desc->local_size_n = 0;
641 desc->cstack_size = 0x800;
642
643 desc->gpr_alloc = cp->num_gprs;
644 desc->bar_alloc = cp->num_barriers;
645
646 // Only bind user uniforms and the driver constant buffer through the
647 // launch descriptor because UBOs are sticked to the driver cb to avoid the
648 // limitation of 8 CBs.
649 if (nvc0->constbuf[5][0].user || cp->parm_size) {
650 gp100_cp_launch_desc_set_cb(desc, 0, screen->uniform_bo,
651 NVC0_CB_USR_INFO(5), 1 << 16);
652 }
653 gp100_cp_launch_desc_set_cb(desc, 7, screen->uniform_bo,
654 NVC0_CB_AUX_INFO(5), 1 << 11);
655
656 nve4_compute_setup_buf_cb(nvc0, true, desc);
657 }
658
659 static inline void *
660 nve4_compute_alloc_launch_desc(struct nouveau_context *nv,
661 struct nouveau_bo **pbo, uint64_t *pgpuaddr)
662 {
663 uint8_t *ptr = nouveau_scratch_get(nv, 512, pgpuaddr, pbo);
664 if (!ptr)
665 return NULL;
666 if (*pgpuaddr & 255) {
667 unsigned adj = 256 - (*pgpuaddr & 255);
668 ptr += adj;
669 *pgpuaddr += adj;
670 }
671 return ptr;
672 }
673
674 static void
675 nve4_upload_indirect_desc(struct nouveau_pushbuf *push,
676 struct nv04_resource *res, uint64_t gpuaddr,
677 uint32_t length, uint32_t bo_offset)
678 {
679 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
680 PUSH_DATAh(push, gpuaddr);
681 PUSH_DATA (push, gpuaddr);
682 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
683 PUSH_DATA (push, length);
684 PUSH_DATA (push, 1);
685
686 nouveau_pushbuf_space(push, 32, 0, 1);
687 PUSH_REFN(push, res->bo, NOUVEAU_BO_RD | res->domain);
688
689 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (length / 4));
690 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x08 << 1));
691 nouveau_pushbuf_data(push, res->bo, bo_offset,
692 NVC0_IB_ENTRY_1_NO_PREFETCH | length);
693 }
694
695 void
696 nve4_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
697 {
698 struct nvc0_context *nvc0 = nvc0_context(pipe);
699 struct nvc0_screen *screen = nvc0->screen;
700 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
701 void *desc;
702 uint64_t desc_gpuaddr;
703 struct nouveau_bo *desc_bo;
704 int ret;
705
706 desc = nve4_compute_alloc_launch_desc(&nvc0->base, &desc_bo, &desc_gpuaddr);
707 if (!desc) {
708 ret = -1;
709 goto out;
710 }
711 BCTX_REFN_bo(nvc0->bufctx_cp, CP_DESC, NOUVEAU_BO_GART | NOUVEAU_BO_RD,
712 desc_bo);
713
714 list_for_each_entry(struct nvc0_resident, resident, &nvc0->tex_head, list) {
715 nvc0_add_resident(nvc0->bufctx_cp, NVC0_BIND_CP_BINDLESS, resident->buf,
716 resident->flags);
717 }
718
719 list_for_each_entry(struct nvc0_resident, resident, &nvc0->img_head, list) {
720 nvc0_add_resident(nvc0->bufctx_cp, NVC0_BIND_CP_BINDLESS, resident->buf,
721 resident->flags);
722 }
723
724 ret = !nve4_state_validate_cp(nvc0, ~0);
725 if (ret)
726 goto out;
727
728 if (nvc0->screen->compute->oclass >= GP100_COMPUTE_CLASS)
729 gp100_compute_setup_launch_desc(nvc0, desc, info);
730 else
731 nve4_compute_setup_launch_desc(nvc0, desc, info);
732
733 nve4_compute_upload_input(nvc0, info);
734
735 #ifdef DEBUG
736 if (debug_get_num_option("NV50_PROG_DEBUG", 0)) {
737 if (nvc0->screen->compute->oclass >= GP100_COMPUTE_CLASS)
738 gp100_compute_dump_launch_desc(desc);
739 else
740 nve4_compute_dump_launch_desc(desc);
741 }
742 #endif
743
744 if (unlikely(info->indirect)) {
745 struct nv04_resource *res = nv04_resource(info->indirect);
746 uint32_t offset = res->offset + info->indirect_offset;
747
748 /* upload the descriptor */
749 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
750 PUSH_DATAh(push, desc_gpuaddr);
751 PUSH_DATA (push, desc_gpuaddr);
752 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
753 PUSH_DATA (push, 256);
754 PUSH_DATA (push, 1);
755 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (256 / 4));
756 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x08 << 1));
757 PUSH_DATAp(push, (const uint32_t *)desc, 256 / 4);
758
759 if (nvc0->screen->compute->oclass >= GP100_COMPUTE_CLASS) {
760 nve4_upload_indirect_desc(push, res, desc_gpuaddr + 48, 12, offset);
761 } else {
762 /* overwrite griddim_x and griddim_y as two 32-bits integers even
763 * if griddim_y must be a 16-bits integer */
764 nve4_upload_indirect_desc(push, res, desc_gpuaddr + 48, 8, offset);
765
766 /* overwrite the 16 high bits of griddim_y with griddim_z because
767 * we need (z << 16) | x */
768 nve4_upload_indirect_desc(push, res, desc_gpuaddr + 54, 4, offset + 8);
769 }
770 }
771
772 /* upload descriptor and flush */
773 nouveau_pushbuf_space(push, 32, 1, 0);
774 PUSH_REFN(push, screen->text, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
775 BEGIN_NVC0(push, NVE4_CP(LAUNCH_DESC_ADDRESS), 1);
776 PUSH_DATA (push, desc_gpuaddr >> 8);
777 BEGIN_NVC0(push, NVE4_CP(LAUNCH), 1);
778 PUSH_DATA (push, 0x3);
779 BEGIN_NVC0(push, SUBC_CP(NV50_GRAPH_SERIALIZE), 1);
780 PUSH_DATA (push, 0);
781
782 out:
783 if (ret)
784 NOUVEAU_ERR("Failed to launch grid !\n");
785 nouveau_scratch_done(&nvc0->base);
786 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_DESC);
787 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_BINDLESS);
788 }
789
790
791 #define NVE4_TIC_ENTRY_INVALID 0x000fffff
792
793 static void
794 nve4_compute_validate_textures(struct nvc0_context *nvc0)
795 {
796 struct nouveau_bo *txc = nvc0->screen->txc;
797 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
798 const unsigned s = 5;
799 unsigned i;
800 uint32_t commands[2][32];
801 unsigned n[2] = { 0, 0 };
802
803 for (i = 0; i < nvc0->num_textures[s]; ++i) {
804 struct nv50_tic_entry *tic = nv50_tic_entry(nvc0->textures[s][i]);
805 struct nv04_resource *res;
806 const bool dirty = !!(nvc0->textures_dirty[s] & (1 << i));
807
808 if (!tic) {
809 nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID;
810 continue;
811 }
812 res = nv04_resource(tic->pipe.texture);
813 nvc0_update_tic(nvc0, tic, res);
814
815 if (tic->id < 0) {
816 tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
817
818 PUSH_SPACE(push, 16);
819 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
820 PUSH_DATAh(push, txc->offset + (tic->id * 32));
821 PUSH_DATA (push, txc->offset + (tic->id * 32));
822 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
823 PUSH_DATA (push, 32);
824 PUSH_DATA (push, 1);
825 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 9);
826 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
827 PUSH_DATAp(push, &tic->tic[0], 8);
828
829 commands[0][n[0]++] = (tic->id << 4) | 1;
830 } else
831 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
832 commands[1][n[1]++] = (tic->id << 4) | 1;
833 }
834 nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
835
836 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
837 res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
838
839 nvc0->tex_handles[s][i] &= ~NVE4_TIC_ENTRY_INVALID;
840 nvc0->tex_handles[s][i] |= tic->id;
841 if (dirty)
842 BCTX_REFN(nvc0->bufctx_cp, CP_TEX(i), res, RD);
843 }
844 for (; i < nvc0->state.num_textures[s]; ++i) {
845 nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID;
846 nvc0->textures_dirty[s] |= 1 << i;
847 }
848
849 if (n[0]) {
850 BEGIN_NIC0(push, NVE4_CP(TIC_FLUSH), n[0]);
851 PUSH_DATAp(push, commands[0], n[0]);
852 }
853 if (n[1]) {
854 BEGIN_NIC0(push, NVE4_CP(TEX_CACHE_CTL), n[1]);
855 PUSH_DATAp(push, commands[1], n[1]);
856 }
857
858 nvc0->state.num_textures[s] = nvc0->num_textures[s];
859
860 /* Invalidate all 3D textures because they are aliased. */
861 for (int s = 0; s < 5; s++) {
862 for (int i = 0; i < nvc0->num_textures[s]; i++)
863 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
864 nvc0->textures_dirty[s] = ~0;
865 }
866 nvc0->dirty_3d |= NVC0_NEW_3D_TEXTURES;
867 }
868
869
870 #ifdef DEBUG
871 static const char *nve4_cache_split_name(unsigned value)
872 {
873 switch (value) {
874 case NVC1_3D_CACHE_SPLIT_16K_SHARED_48K_L1: return "16K_SHARED_48K_L1";
875 case NVE4_3D_CACHE_SPLIT_32K_SHARED_32K_L1: return "32K_SHARED_32K_L1";
876 case NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1: return "48K_SHARED_16K_L1";
877 default:
878 return "(invalid)";
879 }
880 }
881
882 static void
883 nve4_compute_dump_launch_desc(const struct nve4_cp_launch_desc *desc)
884 {
885 const uint32_t *data = (const uint32_t *)desc;
886 unsigned i;
887 bool zero = false;
888
889 debug_printf("COMPUTE LAUNCH DESCRIPTOR:\n");
890
891 for (i = 0; i < sizeof(*desc); i += 4) {
892 if (data[i / 4]) {
893 debug_printf("[%x]: 0x%08x\n", i, data[i / 4]);
894 zero = false;
895 } else
896 if (!zero) {
897 debug_printf("...\n");
898 zero = true;
899 }
900 }
901
902 debug_printf("entry = 0x%x\n", desc->entry);
903 debug_printf("grid dimensions = %ux%ux%u\n",
904 desc->griddim_x, desc->griddim_y, desc->griddim_z);
905 debug_printf("block dimensions = %ux%ux%u\n",
906 desc->blockdim_x, desc->blockdim_y, desc->blockdim_z);
907 debug_printf("s[] size: 0x%x\n", desc->shared_size);
908 debug_printf("l[] size: -0x%x / +0x%x\n",
909 desc->local_size_n, desc->local_size_p);
910 debug_printf("stack size: 0x%x\n", desc->cstack_size);
911 debug_printf("barrier count: %u\n", desc->bar_alloc);
912 debug_printf("$r count: %u\n", desc->gpr_alloc);
913 debug_printf("cache split: %s\n", nve4_cache_split_name(desc->cache_split));
914 debug_printf("linked tsc: %d\n", desc->linked_tsc);
915
916 for (i = 0; i < 8; ++i) {
917 uint64_t address;
918 uint32_t size = desc->cb[i].size;
919 bool valid = !!(desc->cb_mask & (1 << i));
920
921 address = ((uint64_t)desc->cb[i].address_h << 32) | desc->cb[i].address_l;
922
923 if (!valid && !address && !size)
924 continue;
925 debug_printf("CB[%u]: address = 0x%"PRIx64", size 0x%x%s\n",
926 i, address, size, valid ? "" : " (invalid)");
927 }
928 }
929
930 static void
931 gp100_compute_dump_launch_desc(const struct gp100_cp_launch_desc *desc)
932 {
933 const uint32_t *data = (const uint32_t *)desc;
934 unsigned i;
935 bool zero = false;
936
937 debug_printf("COMPUTE LAUNCH DESCRIPTOR:\n");
938
939 for (i = 0; i < sizeof(*desc); i += 4) {
940 if (data[i / 4]) {
941 debug_printf("[%x]: 0x%08x\n", i, data[i / 4]);
942 zero = false;
943 } else
944 if (!zero) {
945 debug_printf("...\n");
946 zero = true;
947 }
948 }
949
950 debug_printf("entry = 0x%x\n", desc->entry);
951 debug_printf("grid dimensions = %ux%ux%u\n",
952 desc->griddim_x, desc->griddim_y, desc->griddim_z);
953 debug_printf("block dimensions = %ux%ux%u\n",
954 desc->blockdim_x, desc->blockdim_y, desc->blockdim_z);
955 debug_printf("s[] size: 0x%x\n", desc->shared_size);
956 debug_printf("l[] size: -0x%x / +0x%x\n",
957 desc->local_size_n, desc->local_size_p);
958 debug_printf("stack size: 0x%x\n", desc->cstack_size);
959 debug_printf("barrier count: %u\n", desc->bar_alloc);
960 debug_printf("$r count: %u\n", desc->gpr_alloc);
961 debug_printf("linked tsc: %d\n", desc->linked_tsc);
962
963 for (i = 0; i < 8; ++i) {
964 uint64_t address;
965 uint32_t size = desc->cb[i].size_sh4 << 4;
966 bool valid = !!(desc->cb_mask & (1 << i));
967
968 address = ((uint64_t)desc->cb[i].address_h << 32) | desc->cb[i].address_l;
969
970 if (!valid && !address && !size)
971 continue;
972 debug_printf("CB[%u]: address = 0x%"PRIx64", size 0x%x%s\n",
973 i, address, size, valid ? "" : " (invalid)");
974 }
975 }
976 #endif
977
978 #ifdef NOUVEAU_NVE4_MP_TRAP_HANDLER
979 static void
980 nve4_compute_trap_info(struct nvc0_context *nvc0)
981 {
982 struct nvc0_screen *screen = nvc0->screen;
983 struct nouveau_bo *bo = screen->parm;
984 int ret, i;
985 volatile struct nve4_mp_trap_info *info;
986 uint8_t *map;
987
988 ret = nouveau_bo_map(bo, NOUVEAU_BO_RDWR, nvc0->base.client);
989 if (ret)
990 return;
991 map = (uint8_t *)bo->map;
992 info = (volatile struct nve4_mp_trap_info *)(map + NVE4_CP_PARAM_TRAP_INFO);
993
994 if (info->lock) {
995 debug_printf("trapstat = %08x\n", info->trapstat);
996 debug_printf("warperr = %08x\n", info->warperr);
997 debug_printf("PC = %x\n", info->pc);
998 debug_printf("tid = %u %u %u\n",
999 info->tid[0], info->tid[1], info->tid[2]);
1000 debug_printf("ctaid = %u %u %u\n",
1001 info->ctaid[0], info->ctaid[1], info->ctaid[2]);
1002 for (i = 0; i <= 63; ++i)
1003 debug_printf("$r%i = %08x\n", i, info->r[i]);
1004 for (i = 0; i <= 6; ++i)
1005 debug_printf("$p%i = %i\n", i, (info->flags >> i) & 1);
1006 debug_printf("$c = %x\n", info->flags >> 12);
1007 }
1008 info->lock = 0;
1009 }
1010 #endif