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nvc0: Enable compute support for Pascal
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nve4_compute.c
1 /*
2 * Copyright 2012 Nouveau Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Christoph Bumiller
23 */
24
25 #include "nvc0/nvc0_context.h"
26 #include "nvc0/nve4_compute.h"
27
28 #include "codegen/nv50_ir_driver.h"
29
30 #ifdef DEBUG
31 static void nve4_compute_dump_launch_desc(const struct nve4_cp_launch_desc *);
32 static void gp100_compute_dump_launch_desc(const struct gp100_cp_launch_desc *);
33 #endif
34
35
36 int
37 nve4_screen_compute_setup(struct nvc0_screen *screen,
38 struct nouveau_pushbuf *push)
39 {
40 struct nouveau_device *dev = screen->base.device;
41 struct nouveau_object *chan = screen->base.channel;
42 int i;
43 int ret;
44 uint32_t obj_class;
45 uint64_t address;
46
47 switch (dev->chipset & ~0xf) {
48 case 0x100:
49 case 0xf0:
50 obj_class = NVF0_COMPUTE_CLASS; /* GK110 */
51 break;
52 case 0xe0:
53 obj_class = NVE4_COMPUTE_CLASS; /* GK104 */
54 break;
55 case 0x110:
56 obj_class = GM107_COMPUTE_CLASS;
57 break;
58 case 0x120:
59 obj_class = GM200_COMPUTE_CLASS;
60 break;
61 case 0x130:
62 obj_class = dev->chipset == 0x130 ? GP100_COMPUTE_CLASS : GP104_COMPUTE_CLASS;
63 break;
64 default:
65 NOUVEAU_ERR("unsupported chipset: NV%02x\n", dev->chipset);
66 return -1;
67 }
68
69 ret = nouveau_object_new(chan, 0xbeef00c0, obj_class, NULL, 0,
70 &screen->compute);
71 if (ret) {
72 NOUVEAU_ERR("Failed to allocate compute object: %d\n", ret);
73 return ret;
74 }
75
76 BEGIN_NVC0(push, SUBC_CP(NV01_SUBCHAN_OBJECT), 1);
77 PUSH_DATA (push, screen->compute->oclass);
78
79 BEGIN_NVC0(push, NVE4_CP(TEMP_ADDRESS_HIGH), 2);
80 PUSH_DATAh(push, screen->tls->offset);
81 PUSH_DATA (push, screen->tls->offset);
82 /* No idea why there are 2. Divide size by 2 to be safe.
83 * Actually this might be per-MP TEMP size and looks like I'm only using
84 * 2 MPs instead of all 8.
85 */
86 BEGIN_NVC0(push, NVE4_CP(MP_TEMP_SIZE_HIGH(0)), 3);
87 PUSH_DATAh(push, screen->tls->size / screen->mp_count);
88 PUSH_DATA (push, (screen->tls->size / screen->mp_count) & ~0x7fff);
89 PUSH_DATA (push, 0xff);
90 BEGIN_NVC0(push, NVE4_CP(MP_TEMP_SIZE_HIGH(1)), 3);
91 PUSH_DATAh(push, screen->tls->size / screen->mp_count);
92 PUSH_DATA (push, (screen->tls->size / screen->mp_count) & ~0x7fff);
93 PUSH_DATA (push, 0xff);
94
95 /* Unified address space ? Who needs that ? Certainly not OpenCL.
96 *
97 * FATAL: Buffers with addresses inside [0x1000000, 0x3000000] will NOT be
98 * accessible. We cannot prevent that at the moment, so expect failure.
99 */
100 BEGIN_NVC0(push, NVE4_CP(LOCAL_BASE), 1);
101 PUSH_DATA (push, 0xff << 24);
102 BEGIN_NVC0(push, NVE4_CP(SHARED_BASE), 1);
103 PUSH_DATA (push, 0xfe << 24);
104
105 BEGIN_NVC0(push, NVE4_CP(CODE_ADDRESS_HIGH), 2);
106 PUSH_DATAh(push, screen->text->offset);
107 PUSH_DATA (push, screen->text->offset);
108
109 BEGIN_NVC0(push, SUBC_CP(0x0310), 1);
110 PUSH_DATA (push, (obj_class >= NVF0_COMPUTE_CLASS) ? 0x400 : 0x300);
111
112 /* NOTE: these do not affect the state used by the 3D object */
113 BEGIN_NVC0(push, NVE4_CP(TIC_ADDRESS_HIGH), 3);
114 PUSH_DATAh(push, screen->txc->offset);
115 PUSH_DATA (push, screen->txc->offset);
116 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
117 BEGIN_NVC0(push, NVE4_CP(TSC_ADDRESS_HIGH), 3);
118 PUSH_DATAh(push, screen->txc->offset + 65536);
119 PUSH_DATA (push, screen->txc->offset + 65536);
120 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
121
122 if (obj_class >= NVF0_COMPUTE_CLASS) {
123 /* The blob calls GK110_COMPUTE.FIRMWARE[0x6], along with the args (0x1)
124 * passed with GK110_COMPUTE.GRAPH.SCRATCH[0x2]. This is currently
125 * disabled because our firmware doesn't support these commands and the
126 * GPU hangs if they are used. */
127 BEGIN_NIC0(push, SUBC_CP(0x0248), 64);
128 for (i = 63; i >= 0; i--)
129 PUSH_DATA(push, 0x38000 | i);
130 IMMED_NVC0(push, SUBC_CP(NV50_GRAPH_SERIALIZE), 0);
131 }
132
133 BEGIN_NVC0(push, NVE4_CP(TEX_CB_INDEX), 1);
134 PUSH_DATA (push, 7); /* does not interfere with 3D */
135
136 /* Disabling this UNK command avoid a read fault when using texelFetch()
137 * from a compute shader for weird reasons.
138 if (obj_class == NVF0_COMPUTE_CLASS)
139 IMMED_NVC0(push, SUBC_CP(0x02c4), 1);
140 */
141
142 address = screen->uniform_bo->offset + NVC0_CB_AUX_INFO(5);
143
144 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
145 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
146 PUSH_DATAh(push, address + NVC0_CB_AUX_MS_INFO);
147 PUSH_DATA (push, address + NVC0_CB_AUX_MS_INFO);
148 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
149 PUSH_DATA (push, 64);
150 PUSH_DATA (push, 1);
151 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 17);
152 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
153 PUSH_DATA (push, 0); /* 0 */
154 PUSH_DATA (push, 0);
155 PUSH_DATA (push, 1); /* 1 */
156 PUSH_DATA (push, 0);
157 PUSH_DATA (push, 0); /* 2 */
158 PUSH_DATA (push, 1);
159 PUSH_DATA (push, 1); /* 3 */
160 PUSH_DATA (push, 1);
161 PUSH_DATA (push, 2); /* 4 */
162 PUSH_DATA (push, 0);
163 PUSH_DATA (push, 3); /* 5 */
164 PUSH_DATA (push, 0);
165 PUSH_DATA (push, 2); /* 6 */
166 PUSH_DATA (push, 1);
167 PUSH_DATA (push, 3); /* 7 */
168 PUSH_DATA (push, 1);
169
170 #ifdef NOUVEAU_NVE4_MP_TRAP_HANDLER
171 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
172 PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_TRAP_INFO_PTR);
173 PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_TRAP_INFO_PTR);
174 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
175 PUSH_DATA (push, 28);
176 PUSH_DATA (push, 1);
177 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 8);
178 PUSH_DATA (push, 1);
179 PUSH_DATA (push, screen->parm->offset + NVE4_CP_PARAM_TRAP_INFO);
180 PUSH_DATAh(push, screen->parm->offset + NVE4_CP_PARAM_TRAP_INFO);
181 PUSH_DATA (push, screen->tls->offset);
182 PUSH_DATAh(push, screen->tls->offset);
183 PUSH_DATA (push, screen->tls->size / 2); /* MP TEMP block size */
184 PUSH_DATA (push, screen->tls->size / 2 / 64); /* warp TEMP block size */
185 PUSH_DATA (push, 0); /* warp cfstack size */
186 #endif
187
188 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
189 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
190
191 return 0;
192 }
193
194 static void
195 gm107_compute_validate_surfaces(struct nvc0_context *nvc0,
196 struct pipe_image_view *view, int slot)
197 {
198 struct nv04_resource *res = nv04_resource(view->resource);
199 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
200 struct nvc0_screen *screen = nvc0->screen;
201 struct nouveau_bo *txc = nvc0->screen->txc;
202 struct nv50_tic_entry *tic;
203 uint64_t address;
204 const int s = 5;
205
206 tic = nv50_tic_entry(nvc0->images_tic[s][slot]);
207
208 res = nv04_resource(tic->pipe.texture);
209 nvc0_update_tic(nvc0, tic, res);
210
211 if (tic->id < 0) {
212 tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
213
214 /* upload the texture view */
215 PUSH_SPACE(push, 16);
216 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
217 PUSH_DATAh(push, txc->offset + (tic->id * 32));
218 PUSH_DATA (push, txc->offset + (tic->id * 32));
219 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
220 PUSH_DATA (push, 32);
221 PUSH_DATA (push, 1);
222 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 9);
223 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
224 PUSH_DATAp(push, &tic->tic[0], 8);
225
226 BEGIN_NIC0(push, NVE4_CP(TIC_FLUSH), 1);
227 PUSH_DATA (push, (tic->id << 4) | 1);
228 } else
229 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
230 BEGIN_NIC0(push, NVE4_CP(TEX_CACHE_CTL), 1);
231 PUSH_DATA (push, (tic->id << 4) | 1);
232 }
233 nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
234
235 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
236 res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
237
238 BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RD);
239
240 address = screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
241
242 /* upload the texture handle */
243 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
244 PUSH_DATAh(push, address + NVC0_CB_AUX_TEX_INFO(slot + 32));
245 PUSH_DATA (push, address + NVC0_CB_AUX_TEX_INFO(slot + 32));
246 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
247 PUSH_DATA (push, 4);
248 PUSH_DATA (push, 0x1);
249 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 2);
250 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
251 PUSH_DATA (push, tic->id);
252
253 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
254 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
255 }
256
257 static void
258 nve4_compute_validate_surfaces(struct nvc0_context *nvc0)
259 {
260 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
261 uint64_t address;
262 const int s = 5;
263 int i, j;
264
265 if (!nvc0->images_dirty[s])
266 return;
267
268 address = nvc0->screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
269
270 for (i = 0; i < NVC0_MAX_IMAGES; ++i) {
271 struct pipe_image_view *view = &nvc0->images[s][i];
272
273 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
274 PUSH_DATAh(push, address + NVC0_CB_AUX_SU_INFO(i));
275 PUSH_DATA (push, address + NVC0_CB_AUX_SU_INFO(i));
276 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
277 PUSH_DATA (push, 16 * 4);
278 PUSH_DATA (push, 0x1);
279 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 16);
280 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
281
282 if (view->resource) {
283 struct nv04_resource *res = nv04_resource(view->resource);
284
285 if (res->base.target == PIPE_BUFFER) {
286 if (view->access & PIPE_IMAGE_ACCESS_WRITE)
287 nvc0_mark_image_range_valid(view);
288 }
289
290 nve4_set_surface_info(push, view, nvc0);
291 BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RDWR);
292
293 if (nvc0->screen->base.class_3d >= GM107_3D_CLASS)
294 gm107_compute_validate_surfaces(nvc0, view, i);
295 } else {
296 for (j = 0; j < 16; j++)
297 PUSH_DATA(push, 0);
298 }
299 }
300 }
301
302 /* Thankfully, textures with samplers follow the normal rules. */
303 static void
304 nve4_compute_validate_samplers(struct nvc0_context *nvc0)
305 {
306 bool need_flush = nve4_validate_tsc(nvc0, 5);
307 if (need_flush) {
308 BEGIN_NVC0(nvc0->base.pushbuf, NVE4_CP(TSC_FLUSH), 1);
309 PUSH_DATA (nvc0->base.pushbuf, 0);
310 }
311
312 /* Invalidate all 3D samplers because they are aliased. */
313 for (int s = 0; s < 5; s++)
314 nvc0->samplers_dirty[s] = ~0;
315 nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLERS;
316 }
317
318 /* (Code duplicated at bottom for various non-convincing reasons.
319 * E.g. we might want to use the COMPUTE subchannel to upload TIC/TSC
320 * entries to avoid a subchannel switch.
321 * Same for texture cache flushes.
322 * Also, the bufctx differs, and more IFs in the 3D version looks ugly.)
323 */
324 static void nve4_compute_validate_textures(struct nvc0_context *);
325
326 static void
327 nve4_compute_set_tex_handles(struct nvc0_context *nvc0)
328 {
329 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
330 struct nvc0_screen *screen = nvc0->screen;
331 uint64_t address;
332 const unsigned s = nvc0_shader_stage(PIPE_SHADER_COMPUTE);
333 unsigned i, n;
334 uint32_t dirty = nvc0->textures_dirty[s] | nvc0->samplers_dirty[s];
335
336 if (!dirty)
337 return;
338 i = ffs(dirty) - 1;
339 n = util_logbase2(dirty) + 1 - i;
340 assert(n);
341
342 address = screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
343
344 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
345 PUSH_DATAh(push, address + NVC0_CB_AUX_TEX_INFO(i));
346 PUSH_DATA (push, address + NVC0_CB_AUX_TEX_INFO(i));
347 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
348 PUSH_DATA (push, n * 4);
349 PUSH_DATA (push, 0x1);
350 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + n);
351 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
352 PUSH_DATAp(push, &nvc0->tex_handles[s][i], n);
353
354 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
355 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
356
357 nvc0->textures_dirty[s] = 0;
358 nvc0->samplers_dirty[s] = 0;
359 }
360
361 static void
362 nve4_compute_validate_constbufs(struct nvc0_context *nvc0)
363 {
364 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
365 const int s = 5;
366
367 while (nvc0->constbuf_dirty[s]) {
368 int i = ffs(nvc0->constbuf_dirty[s]) - 1;
369 nvc0->constbuf_dirty[s] &= ~(1 << i);
370
371 if (nvc0->constbuf[s][i].user) {
372 struct nouveau_bo *bo = nvc0->screen->uniform_bo;
373 const unsigned base = NVC0_CB_USR_INFO(s);
374 const unsigned size = nvc0->constbuf[s][0].size;
375 assert(i == 0); /* we really only want OpenGL uniforms here */
376 assert(nvc0->constbuf[s][0].u.data);
377
378 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
379 PUSH_DATAh(push, bo->offset + base);
380 PUSH_DATA (push, bo->offset + base);
381 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
382 PUSH_DATA (push, size);
383 PUSH_DATA (push, 0x1);
384 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (size / 4));
385 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
386 PUSH_DATAp(push, nvc0->constbuf[s][0].u.data, size / 4);
387 }
388 else {
389 struct nv04_resource *res =
390 nv04_resource(nvc0->constbuf[s][i].u.buf);
391 if (res) {
392 uint64_t address
393 = nvc0->screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
394
395 assert(i > 0); /* we really only want uniform buffer objects */
396
397 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
398 PUSH_DATAh(push, address + NVC0_CB_AUX_UBO_INFO(i - 1));
399 PUSH_DATA (push, address + NVC0_CB_AUX_UBO_INFO(i - 1));
400 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
401 PUSH_DATA (push, 4 * 4);
402 PUSH_DATA (push, 0x1);
403 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 4);
404 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
405
406 PUSH_DATA (push, res->address + nvc0->constbuf[s][i].offset);
407 PUSH_DATAh(push, res->address + nvc0->constbuf[s][i].offset);
408 PUSH_DATA (push, nvc0->constbuf[5][i].size);
409 PUSH_DATA (push, 0);
410 BCTX_REFN(nvc0->bufctx_cp, CP_CB(i), res, RD);
411
412 res->cb_bindings[s] |= 1 << i;
413 }
414 }
415 }
416
417 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
418 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
419 }
420
421 static void
422 nve4_compute_validate_buffers(struct nvc0_context *nvc0)
423 {
424 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
425 uint64_t address;
426 const int s = 5;
427 int i;
428
429 address = nvc0->screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
430
431 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
432 PUSH_DATAh(push, address + NVC0_CB_AUX_BUF_INFO(0));
433 PUSH_DATA (push, address + NVC0_CB_AUX_BUF_INFO(0));
434 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
435 PUSH_DATA (push, 4 * NVC0_MAX_BUFFERS * 4);
436 PUSH_DATA (push, 0x1);
437 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 4 * NVC0_MAX_BUFFERS);
438 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
439
440 for (i = 0; i < NVC0_MAX_BUFFERS; i++) {
441 if (nvc0->buffers[s][i].buffer) {
442 struct nv04_resource *res =
443 nv04_resource(nvc0->buffers[s][i].buffer);
444 PUSH_DATA (push, res->address + nvc0->buffers[s][i].buffer_offset);
445 PUSH_DATAh(push, res->address + nvc0->buffers[s][i].buffer_offset);
446 PUSH_DATA (push, nvc0->buffers[s][i].buffer_size);
447 PUSH_DATA (push, 0);
448 BCTX_REFN(nvc0->bufctx_cp, CP_BUF, res, RDWR);
449 util_range_add(&res->valid_buffer_range,
450 nvc0->buffers[s][i].buffer_offset,
451 nvc0->buffers[s][i].buffer_offset +
452 nvc0->buffers[s][i].buffer_size);
453 } else {
454 PUSH_DATA (push, 0);
455 PUSH_DATA (push, 0);
456 PUSH_DATA (push, 0);
457 PUSH_DATA (push, 0);
458 }
459 }
460 }
461
462 static struct nvc0_state_validate
463 validate_list_cp[] = {
464 { nvc0_compprog_validate, NVC0_NEW_CP_PROGRAM },
465 { nve4_compute_validate_textures, NVC0_NEW_CP_TEXTURES },
466 { nve4_compute_validate_samplers, NVC0_NEW_CP_SAMPLERS },
467 { nve4_compute_set_tex_handles, NVC0_NEW_CP_TEXTURES |
468 NVC0_NEW_CP_SAMPLERS },
469 { nve4_compute_validate_surfaces, NVC0_NEW_CP_SURFACES },
470 { nvc0_compute_validate_globals, NVC0_NEW_CP_GLOBALS },
471 { nve4_compute_validate_buffers, NVC0_NEW_CP_BUFFERS },
472 { nve4_compute_validate_constbufs, NVC0_NEW_CP_CONSTBUF },
473 };
474
475 static bool
476 nve4_state_validate_cp(struct nvc0_context *nvc0, uint32_t mask)
477 {
478 bool ret;
479
480 ret = nvc0_state_validate(nvc0, mask, validate_list_cp,
481 ARRAY_SIZE(validate_list_cp), &nvc0->dirty_cp,
482 nvc0->bufctx_cp);
483
484 if (unlikely(nvc0->state.flushed))
485 nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, true);
486 return ret;
487 }
488
489 static void
490 nve4_compute_upload_input(struct nvc0_context *nvc0,
491 const struct pipe_grid_info *info)
492 {
493 struct nvc0_screen *screen = nvc0->screen;
494 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
495 struct nvc0_program *cp = nvc0->compprog;
496 uint64_t address;
497
498 address = screen->uniform_bo->offset + NVC0_CB_AUX_INFO(5);
499
500 if (cp->parm_size) {
501 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
502 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_USR_INFO(5));
503 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_USR_INFO(5));
504 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
505 PUSH_DATA (push, cp->parm_size);
506 PUSH_DATA (push, 0x1);
507 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (cp->parm_size / 4));
508 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
509 PUSH_DATAp(push, info->input, cp->parm_size / 4);
510 }
511 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
512 PUSH_DATAh(push, address + NVC0_CB_AUX_GRID_INFO(0));
513 PUSH_DATA (push, address + NVC0_CB_AUX_GRID_INFO(0));
514 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
515 PUSH_DATA (push, 8 * 4);
516 PUSH_DATA (push, 0x1);
517
518 if (unlikely(info->indirect)) {
519 struct nv04_resource *res = nv04_resource(info->indirect);
520 uint32_t offset = res->offset + info->indirect_offset;
521
522 nouveau_pushbuf_space(push, 32, 0, 1);
523 PUSH_REFN(push, res->bo, NOUVEAU_BO_RD | res->domain);
524
525 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 8);
526 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
527 PUSH_DATAp(push, info->block, 3);
528 nouveau_pushbuf_data(push, res->bo, offset,
529 NVC0_IB_ENTRY_1_NO_PREFETCH | 3 * 4);
530 } else {
531 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 8);
532 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
533 PUSH_DATAp(push, info->block, 3);
534 PUSH_DATAp(push, info->grid, 3);
535 }
536 PUSH_DATA (push, 0);
537 PUSH_DATA (push, info->work_dim);
538
539 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
540 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
541 }
542
543 static inline uint8_t
544 nve4_compute_derive_cache_split(struct nvc0_context *nvc0, uint32_t shared_size)
545 {
546 if (shared_size > (32 << 10))
547 return NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1;
548 if (shared_size > (16 << 10))
549 return NVE4_3D_CACHE_SPLIT_32K_SHARED_32K_L1;
550 return NVC1_3D_CACHE_SPLIT_16K_SHARED_48K_L1;
551 }
552
553 static void
554 nve4_compute_setup_launch_desc(struct nvc0_context *nvc0,
555 struct nve4_cp_launch_desc *desc,
556 const struct pipe_grid_info *info)
557 {
558 const struct nvc0_screen *screen = nvc0->screen;
559 const struct nvc0_program *cp = nvc0->compprog;
560
561 nve4_cp_launch_desc_init_default(desc);
562
563 desc->entry = nvc0_program_symbol_offset(cp, info->pc);
564
565 desc->griddim_x = info->grid[0];
566 desc->griddim_y = info->grid[1];
567 desc->griddim_z = info->grid[2];
568 desc->blockdim_x = info->block[0];
569 desc->blockdim_y = info->block[1];
570 desc->blockdim_z = info->block[2];
571
572 desc->shared_size = align(cp->cp.smem_size, 0x100);
573 desc->local_size_p = (cp->hdr[1] & 0xfffff0) + align(cp->cp.lmem_size, 0x10);
574 desc->local_size_n = 0;
575 desc->cstack_size = 0x800;
576 desc->cache_split = nve4_compute_derive_cache_split(nvc0, cp->cp.smem_size);
577
578 desc->gpr_alloc = cp->num_gprs;
579 desc->bar_alloc = cp->num_barriers;
580
581 // Only bind user uniforms and the driver constant buffer through the
582 // launch descriptor because UBOs are sticked to the driver cb to avoid the
583 // limitation of 8 CBs.
584 if (nvc0->constbuf[5][0].user || cp->parm_size) {
585 nve4_cp_launch_desc_set_cb(desc, 0, screen->uniform_bo,
586 NVC0_CB_USR_INFO(5), 1 << 16);
587 }
588 nve4_cp_launch_desc_set_cb(desc, 7, screen->uniform_bo,
589 NVC0_CB_AUX_INFO(5), 1 << 11);
590 }
591
592 static void
593 gp100_compute_setup_launch_desc(struct nvc0_context *nvc0,
594 struct gp100_cp_launch_desc *desc,
595 const struct pipe_grid_info *info)
596 {
597 const struct nvc0_screen *screen = nvc0->screen;
598 const struct nvc0_program *cp = nvc0->compprog;
599
600 gp100_cp_launch_desc_init_default(desc);
601
602 desc->entry = nvc0_program_symbol_offset(cp, info->pc);
603
604 desc->griddim_x = info->grid[0];
605 desc->griddim_y = info->grid[1];
606 desc->griddim_z = info->grid[2];
607 desc->blockdim_x = info->block[0];
608 desc->blockdim_y = info->block[1];
609 desc->blockdim_z = info->block[2];
610
611 desc->shared_size = align(cp->cp.smem_size, 0x100);
612 desc->local_size_p = (cp->hdr[1] & 0xfffff0) + align(cp->cp.lmem_size, 0x10);
613 desc->local_size_n = 0;
614 desc->cstack_size = 0x800;
615
616 desc->gpr_alloc = cp->num_gprs;
617 desc->bar_alloc = cp->num_barriers;
618
619 // Only bind user uniforms and the driver constant buffer through the
620 // launch descriptor because UBOs are sticked to the driver cb to avoid the
621 // limitation of 8 CBs.
622 if (nvc0->constbuf[5][0].user || cp->parm_size) {
623 gp100_cp_launch_desc_set_cb(desc, 0, screen->uniform_bo,
624 NVC0_CB_USR_INFO(5), 1 << 16);
625 }
626 gp100_cp_launch_desc_set_cb(desc, 7, screen->uniform_bo,
627 NVC0_CB_AUX_INFO(5), 1 << 11);
628 }
629
630 static inline void *
631 nve4_compute_alloc_launch_desc(struct nouveau_context *nv,
632 struct nouveau_bo **pbo, uint64_t *pgpuaddr)
633 {
634 uint8_t *ptr = nouveau_scratch_get(nv, 512, pgpuaddr, pbo);
635 if (!ptr)
636 return NULL;
637 if (*pgpuaddr & 255) {
638 unsigned adj = 256 - (*pgpuaddr & 255);
639 ptr += adj;
640 *pgpuaddr += adj;
641 }
642 return ptr;
643 }
644
645 static void
646 nve4_upload_indirect_desc(struct nouveau_pushbuf *push,
647 struct nv04_resource *res, uint64_t gpuaddr,
648 uint32_t length, uint32_t bo_offset)
649 {
650 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
651 PUSH_DATAh(push, gpuaddr);
652 PUSH_DATA (push, gpuaddr);
653 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
654 PUSH_DATA (push, length);
655 PUSH_DATA (push, 1);
656
657 nouveau_pushbuf_space(push, 32, 0, 1);
658 PUSH_REFN(push, res->bo, NOUVEAU_BO_RD | res->domain);
659
660 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (length / 4));
661 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x08 << 1));
662 nouveau_pushbuf_data(push, res->bo, bo_offset,
663 NVC0_IB_ENTRY_1_NO_PREFETCH | length);
664 }
665
666 void
667 nve4_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
668 {
669 struct nvc0_context *nvc0 = nvc0_context(pipe);
670 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
671 void *desc;
672 uint64_t desc_gpuaddr;
673 struct nouveau_bo *desc_bo;
674 int ret;
675
676 desc = nve4_compute_alloc_launch_desc(&nvc0->base, &desc_bo, &desc_gpuaddr);
677 if (!desc) {
678 ret = -1;
679 goto out;
680 }
681 BCTX_REFN_bo(nvc0->bufctx_cp, CP_DESC, NOUVEAU_BO_GART | NOUVEAU_BO_RD,
682 desc_bo);
683
684 ret = !nve4_state_validate_cp(nvc0, ~0);
685 if (ret)
686 goto out;
687
688 if (nvc0->screen->compute->oclass >= GP100_COMPUTE_CLASS)
689 gp100_compute_setup_launch_desc(nvc0, desc, info);
690 else
691 nve4_compute_setup_launch_desc(nvc0, desc, info);
692
693 nve4_compute_upload_input(nvc0, info);
694
695 #ifdef DEBUG
696 if (debug_get_num_option("NV50_PROG_DEBUG", 0)) {
697 if (nvc0->screen->compute->oclass >= GP100_COMPUTE_CLASS)
698 gp100_compute_dump_launch_desc(desc);
699 else
700 nve4_compute_dump_launch_desc(desc);
701 }
702 #endif
703
704 if (unlikely(info->indirect)) {
705 struct nv04_resource *res = nv04_resource(info->indirect);
706 uint32_t offset = res->offset + info->indirect_offset;
707
708 /* upload the descriptor */
709 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
710 PUSH_DATAh(push, desc_gpuaddr);
711 PUSH_DATA (push, desc_gpuaddr);
712 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
713 PUSH_DATA (push, 256);
714 PUSH_DATA (push, 1);
715 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (256 / 4));
716 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x08 << 1));
717 PUSH_DATAp(push, (const uint32_t *)desc, 256 / 4);
718
719 if (nvc0->screen->compute->oclass >= GP100_COMPUTE_CLASS) {
720 nve4_upload_indirect_desc(push, res, desc_gpuaddr + 48, 12, offset);
721 } else {
722 /* overwrite griddim_x and griddim_y as two 32-bits integers even
723 * if griddim_y must be a 16-bits integer */
724 nve4_upload_indirect_desc(push, res, desc_gpuaddr + 48, 8, offset);
725
726 /* overwrite the 16 high bits of griddim_y with griddim_z because
727 * we need (z << 16) | x */
728 nve4_upload_indirect_desc(push, res, desc_gpuaddr + 54, 4, offset + 8);
729 }
730 }
731
732 /* upload descriptor and flush */
733 BEGIN_NVC0(push, NVE4_CP(LAUNCH_DESC_ADDRESS), 1);
734 PUSH_DATA (push, desc_gpuaddr >> 8);
735 BEGIN_NVC0(push, NVE4_CP(LAUNCH), 1);
736 PUSH_DATA (push, 0x3);
737 BEGIN_NVC0(push, SUBC_CP(NV50_GRAPH_SERIALIZE), 1);
738 PUSH_DATA (push, 0);
739
740 out:
741 if (ret)
742 NOUVEAU_ERR("Failed to launch grid !\n");
743 nouveau_scratch_done(&nvc0->base);
744 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_DESC);
745 }
746
747
748 #define NVE4_TIC_ENTRY_INVALID 0x000fffff
749
750 static void
751 nve4_compute_validate_textures(struct nvc0_context *nvc0)
752 {
753 struct nouveau_bo *txc = nvc0->screen->txc;
754 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
755 const unsigned s = 5;
756 unsigned i;
757 uint32_t commands[2][32];
758 unsigned n[2] = { 0, 0 };
759
760 for (i = 0; i < nvc0->num_textures[s]; ++i) {
761 struct nv50_tic_entry *tic = nv50_tic_entry(nvc0->textures[s][i]);
762 struct nv04_resource *res;
763 const bool dirty = !!(nvc0->textures_dirty[s] & (1 << i));
764
765 if (!tic) {
766 nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID;
767 continue;
768 }
769 res = nv04_resource(tic->pipe.texture);
770 nvc0_update_tic(nvc0, tic, res);
771
772 if (tic->id < 0) {
773 tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
774
775 PUSH_SPACE(push, 16);
776 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
777 PUSH_DATAh(push, txc->offset + (tic->id * 32));
778 PUSH_DATA (push, txc->offset + (tic->id * 32));
779 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
780 PUSH_DATA (push, 32);
781 PUSH_DATA (push, 1);
782 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 9);
783 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
784 PUSH_DATAp(push, &tic->tic[0], 8);
785
786 commands[0][n[0]++] = (tic->id << 4) | 1;
787 } else
788 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
789 commands[1][n[1]++] = (tic->id << 4) | 1;
790 }
791 nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
792
793 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
794 res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
795
796 nvc0->tex_handles[s][i] &= ~NVE4_TIC_ENTRY_INVALID;
797 nvc0->tex_handles[s][i] |= tic->id;
798 if (dirty)
799 BCTX_REFN(nvc0->bufctx_cp, CP_TEX(i), res, RD);
800 }
801 for (; i < nvc0->state.num_textures[s]; ++i) {
802 nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID;
803 nvc0->textures_dirty[s] |= 1 << i;
804 }
805
806 if (n[0]) {
807 BEGIN_NIC0(push, NVE4_CP(TIC_FLUSH), n[0]);
808 PUSH_DATAp(push, commands[0], n[0]);
809 }
810 if (n[1]) {
811 BEGIN_NIC0(push, NVE4_CP(TEX_CACHE_CTL), n[1]);
812 PUSH_DATAp(push, commands[1], n[1]);
813 }
814
815 nvc0->state.num_textures[s] = nvc0->num_textures[s];
816
817 /* Invalidate all 3D textures because they are aliased. */
818 for (int s = 0; s < 5; s++) {
819 for (int i = 0; i < nvc0->num_textures[s]; i++)
820 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
821 nvc0->textures_dirty[s] = ~0;
822 }
823 nvc0->dirty_3d |= NVC0_NEW_3D_TEXTURES;
824 }
825
826
827 #ifdef DEBUG
828 static const char *nve4_cache_split_name(unsigned value)
829 {
830 switch (value) {
831 case NVC1_3D_CACHE_SPLIT_16K_SHARED_48K_L1: return "16K_SHARED_48K_L1";
832 case NVE4_3D_CACHE_SPLIT_32K_SHARED_32K_L1: return "32K_SHARED_32K_L1";
833 case NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1: return "48K_SHARED_16K_L1";
834 default:
835 return "(invalid)";
836 }
837 }
838
839 static void
840 nve4_compute_dump_launch_desc(const struct nve4_cp_launch_desc *desc)
841 {
842 const uint32_t *data = (const uint32_t *)desc;
843 unsigned i;
844 bool zero = false;
845
846 debug_printf("COMPUTE LAUNCH DESCRIPTOR:\n");
847
848 for (i = 0; i < sizeof(*desc); i += 4) {
849 if (data[i / 4]) {
850 debug_printf("[%x]: 0x%08x\n", i, data[i / 4]);
851 zero = false;
852 } else
853 if (!zero) {
854 debug_printf("...\n");
855 zero = true;
856 }
857 }
858
859 debug_printf("entry = 0x%x\n", desc->entry);
860 debug_printf("grid dimensions = %ux%ux%u\n",
861 desc->griddim_x, desc->griddim_y, desc->griddim_z);
862 debug_printf("block dimensions = %ux%ux%u\n",
863 desc->blockdim_x, desc->blockdim_y, desc->blockdim_z);
864 debug_printf("s[] size: 0x%x\n", desc->shared_size);
865 debug_printf("l[] size: -0x%x / +0x%x\n",
866 desc->local_size_n, desc->local_size_p);
867 debug_printf("stack size: 0x%x\n", desc->cstack_size);
868 debug_printf("barrier count: %u\n", desc->bar_alloc);
869 debug_printf("$r count: %u\n", desc->gpr_alloc);
870 debug_printf("cache split: %s\n", nve4_cache_split_name(desc->cache_split));
871 debug_printf("linked tsc: %d\n", desc->linked_tsc);
872
873 for (i = 0; i < 8; ++i) {
874 uint64_t address;
875 uint32_t size = desc->cb[i].size;
876 bool valid = !!(desc->cb_mask & (1 << i));
877
878 address = ((uint64_t)desc->cb[i].address_h << 32) | desc->cb[i].address_l;
879
880 if (!valid && !address && !size)
881 continue;
882 debug_printf("CB[%u]: address = 0x%"PRIx64", size 0x%x%s\n",
883 i, address, size, valid ? "" : " (invalid)");
884 }
885 }
886
887 static void
888 gp100_compute_dump_launch_desc(const struct gp100_cp_launch_desc *desc)
889 {
890 const uint32_t *data = (const uint32_t *)desc;
891 unsigned i;
892 bool zero = false;
893
894 debug_printf("COMPUTE LAUNCH DESCRIPTOR:\n");
895
896 for (i = 0; i < sizeof(*desc); i += 4) {
897 if (data[i / 4]) {
898 debug_printf("[%x]: 0x%08x\n", i, data[i / 4]);
899 zero = false;
900 } else
901 if (!zero) {
902 debug_printf("...\n");
903 zero = true;
904 }
905 }
906
907 debug_printf("entry = 0x%x\n", desc->entry);
908 debug_printf("grid dimensions = %ux%ux%u\n",
909 desc->griddim_x, desc->griddim_y, desc->griddim_z);
910 debug_printf("block dimensions = %ux%ux%u\n",
911 desc->blockdim_x, desc->blockdim_y, desc->blockdim_z);
912 debug_printf("s[] size: 0x%x\n", desc->shared_size);
913 debug_printf("l[] size: -0x%x / +0x%x\n",
914 desc->local_size_n, desc->local_size_p);
915 debug_printf("stack size: 0x%x\n", desc->cstack_size);
916 debug_printf("barrier count: %u\n", desc->bar_alloc);
917 debug_printf("$r count: %u\n", desc->gpr_alloc);
918 debug_printf("linked tsc: %d\n", desc->linked_tsc);
919
920 for (i = 0; i < 8; ++i) {
921 uint64_t address;
922 uint32_t size = desc->cb[i].size_sh4 << 4;
923 bool valid = !!(desc->cb_mask & (1 << i));
924
925 address = ((uint64_t)desc->cb[i].address_h << 32) | desc->cb[i].address_l;
926
927 if (!valid && !address && !size)
928 continue;
929 debug_printf("CB[%u]: address = 0x%"PRIx64", size 0x%x%s\n",
930 i, address, size, valid ? "" : " (invalid)");
931 }
932 }
933 #endif
934
935 #ifdef NOUVEAU_NVE4_MP_TRAP_HANDLER
936 static void
937 nve4_compute_trap_info(struct nvc0_context *nvc0)
938 {
939 struct nvc0_screen *screen = nvc0->screen;
940 struct nouveau_bo *bo = screen->parm;
941 int ret, i;
942 volatile struct nve4_mp_trap_info *info;
943 uint8_t *map;
944
945 ret = nouveau_bo_map(bo, NOUVEAU_BO_RDWR, nvc0->base.client);
946 if (ret)
947 return;
948 map = (uint8_t *)bo->map;
949 info = (volatile struct nve4_mp_trap_info *)(map + NVE4_CP_PARAM_TRAP_INFO);
950
951 if (info->lock) {
952 debug_printf("trapstat = %08x\n", info->trapstat);
953 debug_printf("warperr = %08x\n", info->warperr);
954 debug_printf("PC = %x\n", info->pc);
955 debug_printf("tid = %u %u %u\n",
956 info->tid[0], info->tid[1], info->tid[2]);
957 debug_printf("ctaid = %u %u %u\n",
958 info->ctaid[0], info->ctaid[1], info->ctaid[2]);
959 for (i = 0; i <= 63; ++i)
960 debug_printf("$r%i = %08x\n", i, info->r[i]);
961 for (i = 0; i <= 6; ++i)
962 debug_printf("$p%i = %i\n", i, (info->flags >> i) & 1);
963 debug_printf("$c = %x\n", info->flags >> 12);
964 }
965 info->lock = 0;
966 }
967 #endif