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nvc0: remove outdated surfaces validation code for GK104
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nve4_compute.c
1 /*
2 * Copyright 2012 Nouveau Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Christoph Bumiller
23 */
24
25 #include "nvc0/nvc0_context.h"
26 #include "nvc0/nve4_compute.h"
27
28 #include "codegen/nv50_ir_driver.h"
29
30 #ifdef DEBUG
31 static void nve4_compute_dump_launch_desc(const struct nve4_cp_launch_desc *);
32 #endif
33
34
35 int
36 nve4_screen_compute_setup(struct nvc0_screen *screen,
37 struct nouveau_pushbuf *push)
38 {
39 struct nouveau_device *dev = screen->base.device;
40 struct nouveau_object *chan = screen->base.channel;
41 int i;
42 int ret;
43 uint32_t obj_class;
44 uint64_t address;
45
46 switch (dev->chipset & ~0xf) {
47 case 0x100:
48 case 0xf0:
49 obj_class = NVF0_COMPUTE_CLASS; /* GK110 */
50 break;
51 case 0xe0:
52 obj_class = NVE4_COMPUTE_CLASS; /* GK104 */
53 break;
54 case 0x110:
55 obj_class = GM107_COMPUTE_CLASS;
56 break;
57 case 0x120:
58 obj_class = GM200_COMPUTE_CLASS;
59 break;
60 default:
61 NOUVEAU_ERR("unsupported chipset: NV%02x\n", dev->chipset);
62 return -1;
63 }
64
65 ret = nouveau_object_new(chan, 0xbeef00c0, obj_class, NULL, 0,
66 &screen->compute);
67 if (ret) {
68 NOUVEAU_ERR("Failed to allocate compute object: %d\n", ret);
69 return ret;
70 }
71
72 BEGIN_NVC0(push, SUBC_CP(NV01_SUBCHAN_OBJECT), 1);
73 PUSH_DATA (push, screen->compute->oclass);
74
75 BEGIN_NVC0(push, NVE4_CP(TEMP_ADDRESS_HIGH), 2);
76 PUSH_DATAh(push, screen->tls->offset);
77 PUSH_DATA (push, screen->tls->offset);
78 /* No idea why there are 2. Divide size by 2 to be safe.
79 * Actually this might be per-MP TEMP size and looks like I'm only using
80 * 2 MPs instead of all 8.
81 */
82 BEGIN_NVC0(push, NVE4_CP(MP_TEMP_SIZE_HIGH(0)), 3);
83 PUSH_DATAh(push, screen->tls->size / screen->mp_count);
84 PUSH_DATA (push, (screen->tls->size / screen->mp_count) & ~0x7fff);
85 PUSH_DATA (push, 0xff);
86 BEGIN_NVC0(push, NVE4_CP(MP_TEMP_SIZE_HIGH(1)), 3);
87 PUSH_DATAh(push, screen->tls->size / screen->mp_count);
88 PUSH_DATA (push, (screen->tls->size / screen->mp_count) & ~0x7fff);
89 PUSH_DATA (push, 0xff);
90
91 /* Unified address space ? Who needs that ? Certainly not OpenCL.
92 *
93 * FATAL: Buffers with addresses inside [0x1000000, 0x3000000] will NOT be
94 * accessible. We cannot prevent that at the moment, so expect failure.
95 */
96 BEGIN_NVC0(push, NVE4_CP(LOCAL_BASE), 1);
97 PUSH_DATA (push, 0xff << 24);
98 BEGIN_NVC0(push, NVE4_CP(SHARED_BASE), 1);
99 PUSH_DATA (push, 0xfe << 24);
100
101 BEGIN_NVC0(push, NVE4_CP(CODE_ADDRESS_HIGH), 2);
102 PUSH_DATAh(push, screen->text->offset);
103 PUSH_DATA (push, screen->text->offset);
104
105 BEGIN_NVC0(push, SUBC_CP(0x0310), 1);
106 PUSH_DATA (push, (obj_class >= NVF0_COMPUTE_CLASS) ? 0x400 : 0x300);
107
108 /* NOTE: these do not affect the state used by the 3D object */
109 BEGIN_NVC0(push, NVE4_CP(TIC_ADDRESS_HIGH), 3);
110 PUSH_DATAh(push, screen->txc->offset);
111 PUSH_DATA (push, screen->txc->offset);
112 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
113 BEGIN_NVC0(push, NVE4_CP(TSC_ADDRESS_HIGH), 3);
114 PUSH_DATAh(push, screen->txc->offset + 65536);
115 PUSH_DATA (push, screen->txc->offset + 65536);
116 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
117
118 if (obj_class >= NVF0_COMPUTE_CLASS) {
119 /* The blob calls GK110_COMPUTE.FIRMWARE[0x6], along with the args (0x1)
120 * passed with GK110_COMPUTE.GRAPH.SCRATCH[0x2]. This is currently
121 * disabled because our firmware doesn't support these commands and the
122 * GPU hangs if they are used. */
123 BEGIN_NIC0(push, SUBC_CP(0x0248), 64);
124 for (i = 63; i >= 0; i--)
125 PUSH_DATA(push, 0x38000 | i);
126 IMMED_NVC0(push, SUBC_CP(NV50_GRAPH_SERIALIZE), 0);
127 }
128
129 BEGIN_NVC0(push, NVE4_CP(TEX_CB_INDEX), 1);
130 PUSH_DATA (push, 7); /* does not interfere with 3D */
131
132 /* Disabling this UNK command avoid a read fault when using texelFetch()
133 * from a compute shader for weird reasons.
134 if (obj_class == NVF0_COMPUTE_CLASS)
135 IMMED_NVC0(push, SUBC_CP(0x02c4), 1);
136 */
137
138 address = screen->uniform_bo->offset + NVC0_CB_AUX_INFO(5);
139
140 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
141 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
142 PUSH_DATAh(push, address + NVC0_CB_AUX_MS_INFO);
143 PUSH_DATA (push, address + NVC0_CB_AUX_MS_INFO);
144 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
145 PUSH_DATA (push, 64);
146 PUSH_DATA (push, 1);
147 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 17);
148 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
149 PUSH_DATA (push, 0); /* 0 */
150 PUSH_DATA (push, 0);
151 PUSH_DATA (push, 1); /* 1 */
152 PUSH_DATA (push, 0);
153 PUSH_DATA (push, 0); /* 2 */
154 PUSH_DATA (push, 1);
155 PUSH_DATA (push, 1); /* 3 */
156 PUSH_DATA (push, 1);
157 PUSH_DATA (push, 2); /* 4 */
158 PUSH_DATA (push, 0);
159 PUSH_DATA (push, 3); /* 5 */
160 PUSH_DATA (push, 0);
161 PUSH_DATA (push, 2); /* 6 */
162 PUSH_DATA (push, 1);
163 PUSH_DATA (push, 3); /* 7 */
164 PUSH_DATA (push, 1);
165
166 #ifdef NOUVEAU_NVE4_MP_TRAP_HANDLER
167 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
168 PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_TRAP_INFO_PTR);
169 PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_TRAP_INFO_PTR);
170 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
171 PUSH_DATA (push, 28);
172 PUSH_DATA (push, 1);
173 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 8);
174 PUSH_DATA (push, 1);
175 PUSH_DATA (push, screen->parm->offset + NVE4_CP_PARAM_TRAP_INFO);
176 PUSH_DATAh(push, screen->parm->offset + NVE4_CP_PARAM_TRAP_INFO);
177 PUSH_DATA (push, screen->tls->offset);
178 PUSH_DATAh(push, screen->tls->offset);
179 PUSH_DATA (push, screen->tls->size / 2); /* MP TEMP block size */
180 PUSH_DATA (push, screen->tls->size / 2 / 64); /* warp TEMP block size */
181 PUSH_DATA (push, 0); /* warp cfstack size */
182 #endif
183
184 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
185 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
186
187 return 0;
188 }
189
190 static void
191 nve4_compute_validate_surfaces(struct nvc0_context *nvc0)
192 {
193 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
194 uint64_t address;
195 const int s = 5;
196 int i, j;
197
198 if (!nvc0->images_dirty[s])
199 return;
200
201 address = nvc0->screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
202
203 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
204 PUSH_DATAh(push, address + NVC0_CB_AUX_SU_INFO(0));
205 PUSH_DATA (push, address + NVC0_CB_AUX_SU_INFO(0));
206 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
207 PUSH_DATA (push, 16 * NVC0_MAX_IMAGES * 4);
208 PUSH_DATA (push, 0x1);
209 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 16 * NVC0_MAX_IMAGES);
210 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
211
212 for (i = 0; i < NVC0_MAX_IMAGES; ++i) {
213 struct pipe_image_view *view = &nvc0->images[s][i];
214 if (view->resource) {
215 struct nv04_resource *res = nv04_resource(view->resource);
216
217 nve4_set_surface_info(push, view, nvc0);
218 BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RDWR);
219 } else {
220 for (j = 0; j < 16; j++)
221 PUSH_DATA(push, 0);
222 }
223 }
224 }
225
226 /* Thankfully, textures with samplers follow the normal rules. */
227 static void
228 nve4_compute_validate_samplers(struct nvc0_context *nvc0)
229 {
230 bool need_flush = nve4_validate_tsc(nvc0, 5);
231 if (need_flush) {
232 BEGIN_NVC0(nvc0->base.pushbuf, NVE4_CP(TSC_FLUSH), 1);
233 PUSH_DATA (nvc0->base.pushbuf, 0);
234 }
235 }
236 /* (Code duplicated at bottom for various non-convincing reasons.
237 * E.g. we might want to use the COMPUTE subchannel to upload TIC/TSC
238 * entries to avoid a subchannel switch.
239 * Same for texture cache flushes.
240 * Also, the bufctx differs, and more IFs in the 3D version looks ugly.)
241 */
242 static void nve4_compute_validate_textures(struct nvc0_context *);
243
244 static void
245 nve4_compute_set_tex_handles(struct nvc0_context *nvc0)
246 {
247 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
248 struct nvc0_screen *screen = nvc0->screen;
249 uint64_t address;
250 const unsigned s = nvc0_shader_stage(PIPE_SHADER_COMPUTE);
251 unsigned i, n;
252 uint32_t dirty = nvc0->textures_dirty[s] | nvc0->samplers_dirty[s];
253
254 if (!dirty)
255 return;
256 i = ffs(dirty) - 1;
257 n = util_logbase2(dirty) + 1 - i;
258 assert(n);
259
260 address = screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
261
262 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
263 PUSH_DATAh(push, address + NVC0_CB_AUX_TEX_INFO(i));
264 PUSH_DATA (push, address + NVC0_CB_AUX_TEX_INFO(i));
265 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
266 PUSH_DATA (push, n * 4);
267 PUSH_DATA (push, 0x1);
268 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + n);
269 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
270 PUSH_DATAp(push, &nvc0->tex_handles[s][i], n);
271
272 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
273 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
274
275 nvc0->textures_dirty[s] = 0;
276 nvc0->samplers_dirty[s] = 0;
277 }
278
279 static void
280 nve4_compute_validate_constbufs(struct nvc0_context *nvc0)
281 {
282 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
283 const int s = 5;
284
285 while (nvc0->constbuf_dirty[s]) {
286 int i = ffs(nvc0->constbuf_dirty[s]) - 1;
287 nvc0->constbuf_dirty[s] &= ~(1 << i);
288
289 if (nvc0->constbuf[s][i].user) {
290 struct nouveau_bo *bo = nvc0->screen->uniform_bo;
291 const unsigned base = NVC0_CB_USR_INFO(s);
292 const unsigned size = nvc0->constbuf[s][0].size;
293 assert(i == 0); /* we really only want OpenGL uniforms here */
294 assert(nvc0->constbuf[s][0].u.data);
295
296 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
297 PUSH_DATAh(push, bo->offset + base);
298 PUSH_DATA (push, bo->offset + base);
299 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
300 PUSH_DATA (push, size);
301 PUSH_DATA (push, 0x1);
302 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (size / 4));
303 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
304 PUSH_DATAp(push, nvc0->constbuf[s][0].u.data, size / 4);
305 }
306 else {
307 struct nv04_resource *res =
308 nv04_resource(nvc0->constbuf[s][i].u.buf);
309 if (res) {
310 uint64_t address
311 = nvc0->screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
312
313 assert(i > 0); /* we really only want uniform buffer objects */
314
315 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
316 PUSH_DATAh(push, address + NVC0_CB_AUX_UBO_INFO(i - 1));
317 PUSH_DATA (push, address + NVC0_CB_AUX_UBO_INFO(i - 1));
318 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
319 PUSH_DATA (push, 4 * 4);
320 PUSH_DATA (push, 0x1);
321 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 4);
322 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
323
324 PUSH_DATA (push, res->address + nvc0->constbuf[s][i].offset);
325 PUSH_DATAh(push, res->address + nvc0->constbuf[s][i].offset);
326 PUSH_DATA (push, nvc0->constbuf[5][i].size);
327 PUSH_DATA (push, 0);
328 BCTX_REFN(nvc0->bufctx_cp, CP_CB(i), res, RD);
329
330 res->cb_bindings[s] |= 1 << i;
331 }
332 }
333 }
334
335 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
336 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
337 }
338
339 static void
340 nve4_compute_validate_buffers(struct nvc0_context *nvc0)
341 {
342 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
343 uint64_t address;
344 const int s = 5;
345 int i;
346
347 address = nvc0->screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
348
349 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
350 PUSH_DATAh(push, address + NVC0_CB_AUX_BUF_INFO(0));
351 PUSH_DATA (push, address + NVC0_CB_AUX_BUF_INFO(0));
352 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
353 PUSH_DATA (push, 4 * NVC0_MAX_BUFFERS * 4);
354 PUSH_DATA (push, 0x1);
355 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 4 * NVC0_MAX_BUFFERS);
356 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
357
358 for (i = 0; i < NVC0_MAX_BUFFERS; i++) {
359 if (nvc0->buffers[s][i].buffer) {
360 struct nv04_resource *res =
361 nv04_resource(nvc0->buffers[s][i].buffer);
362 PUSH_DATA (push, res->address + nvc0->buffers[s][i].buffer_offset);
363 PUSH_DATAh(push, res->address + nvc0->buffers[s][i].buffer_offset);
364 PUSH_DATA (push, nvc0->buffers[s][i].buffer_size);
365 PUSH_DATA (push, 0);
366 BCTX_REFN(nvc0->bufctx_cp, CP_BUF, res, RDWR);
367 } else {
368 PUSH_DATA (push, 0);
369 PUSH_DATA (push, 0);
370 PUSH_DATA (push, 0);
371 PUSH_DATA (push, 0);
372 }
373 }
374 }
375
376 static struct nvc0_state_validate
377 validate_list_cp[] = {
378 { nvc0_compprog_validate, NVC0_NEW_CP_PROGRAM },
379 { nve4_compute_validate_textures, NVC0_NEW_CP_TEXTURES },
380 { nve4_compute_validate_samplers, NVC0_NEW_CP_SAMPLERS },
381 { nve4_compute_set_tex_handles, NVC0_NEW_CP_TEXTURES |
382 NVC0_NEW_CP_SAMPLERS },
383 { nve4_compute_validate_surfaces, NVC0_NEW_CP_SURFACES },
384 { nvc0_compute_validate_globals, NVC0_NEW_CP_GLOBALS },
385 { nve4_compute_validate_buffers, NVC0_NEW_CP_BUFFERS },
386 { nve4_compute_validate_constbufs, NVC0_NEW_CP_CONSTBUF },
387 };
388
389 static bool
390 nve4_state_validate_cp(struct nvc0_context *nvc0, uint32_t mask)
391 {
392 bool ret;
393
394 ret = nvc0_state_validate(nvc0, mask, validate_list_cp,
395 ARRAY_SIZE(validate_list_cp), &nvc0->dirty_cp,
396 nvc0->bufctx_cp);
397
398 if (unlikely(nvc0->state.flushed))
399 nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, true);
400 return ret;
401 }
402
403 static void
404 nve4_compute_upload_input(struct nvc0_context *nvc0,
405 const struct pipe_grid_info *info)
406 {
407 struct nvc0_screen *screen = nvc0->screen;
408 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
409 struct nvc0_program *cp = nvc0->compprog;
410 uint64_t address;
411
412 address = screen->uniform_bo->offset + NVC0_CB_AUX_INFO(5);
413
414 if (cp->parm_size) {
415 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
416 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_USR_INFO(5));
417 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_USR_INFO(5));
418 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
419 PUSH_DATA (push, cp->parm_size);
420 PUSH_DATA (push, 0x1);
421 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (cp->parm_size / 4));
422 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
423 PUSH_DATAp(push, info->input, cp->parm_size / 4);
424 }
425 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
426 PUSH_DATAh(push, address + NVC0_CB_AUX_GRID_INFO);
427 PUSH_DATA (push, address + NVC0_CB_AUX_GRID_INFO);
428 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
429 PUSH_DATA (push, 7 * 4);
430 PUSH_DATA (push, 0x1);
431
432 if (unlikely(info->indirect)) {
433 struct nv04_resource *res = nv04_resource(info->indirect);
434 uint32_t offset = res->offset + info->indirect_offset;
435
436 nouveau_pushbuf_space(push, 16, 0, 1);
437 PUSH_REFN(push, res->bo, NOUVEAU_BO_RD | res->domain);
438
439 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 7);
440 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
441 PUSH_DATAp(push, info->block, 3);
442 nouveau_pushbuf_data(push, res->bo, offset,
443 NVC0_IB_ENTRY_1_NO_PREFETCH | 3 * 4);
444 } else {
445 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 7);
446 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
447 PUSH_DATAp(push, info->block, 3);
448 PUSH_DATAp(push, info->grid, 3);
449 }
450 PUSH_DATA (push, 0);
451
452 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
453 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
454 }
455
456 static inline uint8_t
457 nve4_compute_derive_cache_split(struct nvc0_context *nvc0, uint32_t shared_size)
458 {
459 if (shared_size > (32 << 10))
460 return NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1;
461 if (shared_size > (16 << 10))
462 return NVE4_3D_CACHE_SPLIT_32K_SHARED_32K_L1;
463 return NVC1_3D_CACHE_SPLIT_16K_SHARED_48K_L1;
464 }
465
466 static void
467 nve4_compute_setup_launch_desc(struct nvc0_context *nvc0,
468 struct nve4_cp_launch_desc *desc,
469 const struct pipe_grid_info *info)
470 {
471 const struct nvc0_screen *screen = nvc0->screen;
472 const struct nvc0_program *cp = nvc0->compprog;
473
474 nve4_cp_launch_desc_init_default(desc);
475
476 desc->entry = nvc0_program_symbol_offset(cp, info->pc);
477
478 desc->griddim_x = info->grid[0];
479 desc->griddim_y = info->grid[1];
480 desc->griddim_z = info->grid[2];
481 desc->blockdim_x = info->block[0];
482 desc->blockdim_y = info->block[1];
483 desc->blockdim_z = info->block[2];
484
485 desc->shared_size = align(cp->cp.smem_size, 0x100);
486 desc->local_size_p = (cp->hdr[1] & 0xfffff0) + align(cp->cp.lmem_size, 0x10);
487 desc->local_size_n = 0;
488 desc->cstack_size = 0x800;
489 desc->cache_split = nve4_compute_derive_cache_split(nvc0, cp->cp.smem_size);
490
491 desc->gpr_alloc = cp->num_gprs;
492 desc->bar_alloc = cp->num_barriers;
493
494 // Only bind user uniforms and the driver constant buffer through the
495 // launch descriptor because UBOs are sticked to the driver cb to avoid the
496 // limitation of 8 CBs.
497 if (nvc0->constbuf[5][0].user || cp->parm_size) {
498 nve4_cp_launch_desc_set_cb(desc, 0, screen->uniform_bo,
499 NVC0_CB_USR_INFO(5), 1 << 16);
500 }
501 nve4_cp_launch_desc_set_cb(desc, 7, screen->uniform_bo,
502 NVC0_CB_AUX_INFO(5), 1 << 11);
503 }
504
505 static inline struct nve4_cp_launch_desc *
506 nve4_compute_alloc_launch_desc(struct nouveau_context *nv,
507 struct nouveau_bo **pbo, uint64_t *pgpuaddr)
508 {
509 uint8_t *ptr = nouveau_scratch_get(nv, 512, pgpuaddr, pbo);
510 if (!ptr)
511 return NULL;
512 if (*pgpuaddr & 255) {
513 unsigned adj = 256 - (*pgpuaddr & 255);
514 ptr += adj;
515 *pgpuaddr += adj;
516 }
517 return (struct nve4_cp_launch_desc *)ptr;
518 }
519
520 void
521 nve4_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
522 {
523 struct nvc0_context *nvc0 = nvc0_context(pipe);
524 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
525 struct nve4_cp_launch_desc *desc;
526 uint64_t desc_gpuaddr;
527 struct nouveau_bo *desc_bo;
528 int ret;
529
530 desc = nve4_compute_alloc_launch_desc(&nvc0->base, &desc_bo, &desc_gpuaddr);
531 if (!desc) {
532 ret = -1;
533 goto out;
534 }
535 BCTX_REFN_bo(nvc0->bufctx_cp, CP_DESC, NOUVEAU_BO_GART | NOUVEAU_BO_RD,
536 desc_bo);
537
538 ret = !nve4_state_validate_cp(nvc0, ~0);
539 if (ret)
540 goto out;
541
542 nve4_compute_setup_launch_desc(nvc0, desc, info);
543
544 nve4_compute_upload_input(nvc0, info);
545
546 #ifdef DEBUG
547 if (debug_get_num_option("NV50_PROG_DEBUG", 0))
548 nve4_compute_dump_launch_desc(desc);
549 #endif
550
551 if (unlikely(info->indirect)) {
552 struct nv04_resource *res = nv04_resource(info->indirect);
553 uint32_t offset = res->offset + info->indirect_offset;
554
555 /* upload the descriptor */
556 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
557 PUSH_DATAh(push, desc_gpuaddr);
558 PUSH_DATA (push, desc_gpuaddr);
559 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
560 PUSH_DATA (push, 256);
561 PUSH_DATA (push, 1);
562 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (256 / 4));
563 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x08 << 1));
564 PUSH_DATAp(push, (const uint32_t *)desc, 256 / 4);
565
566 /* overwrite griddim_x and griddim_y as two 32-bits integers even
567 * if griddim_y must be a 16-bits integer */
568 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
569 PUSH_DATAh(push, desc_gpuaddr + 48);
570 PUSH_DATA (push, desc_gpuaddr + 48);
571 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
572 PUSH_DATA (push, 8);
573 PUSH_DATA (push, 1);
574
575 nouveau_pushbuf_space(push, 16, 0, 1);
576 PUSH_REFN(push, res->bo, NOUVEAU_BO_RD | res->domain);
577
578 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (8 / 4));
579 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x08 << 1));
580 nouveau_pushbuf_data(push, res->bo, offset,
581 NVC0_IB_ENTRY_1_NO_PREFETCH | 2 * 4);
582
583 /* overwrite the 16 high bits of griddim_y with griddim_z because
584 * we need (z << 16) | x */
585 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
586 PUSH_DATAh(push, desc_gpuaddr + 54);
587 PUSH_DATA (push, desc_gpuaddr + 54);
588 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
589 PUSH_DATA (push, 4);
590 PUSH_DATA (push, 1);
591 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (4 / 4));
592 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x08 << 1));
593 nouveau_pushbuf_data(push, res->bo, offset + 8,
594 NVC0_IB_ENTRY_1_NO_PREFETCH | 1 * 4);
595 }
596
597 /* upload descriptor and flush */
598 BEGIN_NVC0(push, NVE4_CP(LAUNCH_DESC_ADDRESS), 1);
599 PUSH_DATA (push, desc_gpuaddr >> 8);
600 BEGIN_NVC0(push, NVE4_CP(LAUNCH), 1);
601 PUSH_DATA (push, 0x3);
602 BEGIN_NVC0(push, SUBC_CP(NV50_GRAPH_SERIALIZE), 1);
603 PUSH_DATA (push, 0);
604
605 out:
606 if (ret)
607 NOUVEAU_ERR("Failed to launch grid !\n");
608 nouveau_scratch_done(&nvc0->base);
609 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_DESC);
610 }
611
612
613 #define NVE4_TIC_ENTRY_INVALID 0x000fffff
614
615 static void
616 nve4_compute_validate_textures(struct nvc0_context *nvc0)
617 {
618 struct nouveau_bo *txc = nvc0->screen->txc;
619 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
620 const unsigned s = 5;
621 unsigned i;
622 uint32_t commands[2][32];
623 unsigned n[2] = { 0, 0 };
624
625 for (i = 0; i < nvc0->num_textures[s]; ++i) {
626 struct nv50_tic_entry *tic = nv50_tic_entry(nvc0->textures[s][i]);
627 struct nv04_resource *res;
628 const bool dirty = !!(nvc0->textures_dirty[s] & (1 << i));
629
630 if (!tic) {
631 nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID;
632 continue;
633 }
634 res = nv04_resource(tic->pipe.texture);
635
636 if (tic->id < 0) {
637 tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
638
639 PUSH_SPACE(push, 16);
640 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
641 PUSH_DATAh(push, txc->offset + (tic->id * 32));
642 PUSH_DATA (push, txc->offset + (tic->id * 32));
643 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
644 PUSH_DATA (push, 32);
645 PUSH_DATA (push, 1);
646 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 9);
647 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
648 PUSH_DATAp(push, &tic->tic[0], 8);
649
650 commands[0][n[0]++] = (tic->id << 4) | 1;
651 } else
652 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
653 commands[1][n[1]++] = (tic->id << 4) | 1;
654 }
655 nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
656
657 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
658 res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
659
660 nvc0->tex_handles[s][i] &= ~NVE4_TIC_ENTRY_INVALID;
661 nvc0->tex_handles[s][i] |= tic->id;
662 if (dirty)
663 BCTX_REFN(nvc0->bufctx_cp, CP_TEX(i), res, RD);
664 }
665 for (; i < nvc0->state.num_textures[s]; ++i)
666 nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID;
667
668 if (n[0]) {
669 BEGIN_NIC0(push, NVE4_CP(TIC_FLUSH), n[0]);
670 PUSH_DATAp(push, commands[0], n[0]);
671 }
672 if (n[1]) {
673 BEGIN_NIC0(push, NVE4_CP(TEX_CACHE_CTL), n[1]);
674 PUSH_DATAp(push, commands[1], n[1]);
675 }
676
677 nvc0->state.num_textures[s] = nvc0->num_textures[s];
678 }
679
680
681 #ifdef DEBUG
682 static const char *nve4_cache_split_name(unsigned value)
683 {
684 switch (value) {
685 case NVC1_3D_CACHE_SPLIT_16K_SHARED_48K_L1: return "16K_SHARED_48K_L1";
686 case NVE4_3D_CACHE_SPLIT_32K_SHARED_32K_L1: return "32K_SHARED_32K_L1";
687 case NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1: return "48K_SHARED_16K_L1";
688 default:
689 return "(invalid)";
690 }
691 }
692
693 static void
694 nve4_compute_dump_launch_desc(const struct nve4_cp_launch_desc *desc)
695 {
696 const uint32_t *data = (const uint32_t *)desc;
697 unsigned i;
698 bool zero = false;
699
700 debug_printf("COMPUTE LAUNCH DESCRIPTOR:\n");
701
702 for (i = 0; i < sizeof(*desc); i += 4) {
703 if (data[i / 4]) {
704 debug_printf("[%x]: 0x%08x\n", i, data[i / 4]);
705 zero = false;
706 } else
707 if (!zero) {
708 debug_printf("...\n");
709 zero = true;
710 }
711 }
712
713 debug_printf("entry = 0x%x\n", desc->entry);
714 debug_printf("grid dimensions = %ux%ux%u\n",
715 desc->griddim_x, desc->griddim_y, desc->griddim_z);
716 debug_printf("block dimensions = %ux%ux%u\n",
717 desc->blockdim_x, desc->blockdim_y, desc->blockdim_z);
718 debug_printf("s[] size: 0x%x\n", desc->shared_size);
719 debug_printf("l[] size: -0x%x / +0x%x\n",
720 desc->local_size_n, desc->local_size_p);
721 debug_printf("stack size: 0x%x\n", desc->cstack_size);
722 debug_printf("barrier count: %u\n", desc->bar_alloc);
723 debug_printf("$r count: %u\n", desc->gpr_alloc);
724 debug_printf("cache split: %s\n", nve4_cache_split_name(desc->cache_split));
725
726 for (i = 0; i < 8; ++i) {
727 uint64_t address;
728 uint32_t size = desc->cb[i].size;
729 bool valid = !!(desc->cb_mask & (1 << i));
730
731 address = ((uint64_t)desc->cb[i].address_h << 32) | desc->cb[i].address_l;
732
733 if (!valid && !address && !size)
734 continue;
735 debug_printf("CB[%u]: address = 0x%"PRIx64", size 0x%x%s\n",
736 i, address, size, valid ? "" : " (invalid)");
737 }
738 }
739 #endif
740
741 #ifdef NOUVEAU_NVE4_MP_TRAP_HANDLER
742 static void
743 nve4_compute_trap_info(struct nvc0_context *nvc0)
744 {
745 struct nvc0_screen *screen = nvc0->screen;
746 struct nouveau_bo *bo = screen->parm;
747 int ret, i;
748 volatile struct nve4_mp_trap_info *info;
749 uint8_t *map;
750
751 ret = nouveau_bo_map(bo, NOUVEAU_BO_RDWR, nvc0->base.client);
752 if (ret)
753 return;
754 map = (uint8_t *)bo->map;
755 info = (volatile struct nve4_mp_trap_info *)(map + NVE4_CP_PARAM_TRAP_INFO);
756
757 if (info->lock) {
758 debug_printf("trapstat = %08x\n", info->trapstat);
759 debug_printf("warperr = %08x\n", info->warperr);
760 debug_printf("PC = %x\n", info->pc);
761 debug_printf("tid = %u %u %u\n",
762 info->tid[0], info->tid[1], info->tid[2]);
763 debug_printf("ctaid = %u %u %u\n",
764 info->ctaid[0], info->ctaid[1], info->ctaid[2]);
765 for (i = 0; i <= 63; ++i)
766 debug_printf("$r%i = %08x\n", i, info->r[i]);
767 for (i = 0; i <= 6; ++i)
768 debug_printf("$p%i = %i\n", i, (info->flags >> i) & 1);
769 debug_printf("$c = %x\n", info->flags >> 12);
770 }
771 info->lock = 0;
772 }
773 #endif