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nvc0: Add new launch descriptor format for GP100
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nve4_compute.c
1 /*
2 * Copyright 2012 Nouveau Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Christoph Bumiller
23 */
24
25 #include "nvc0/nvc0_context.h"
26 #include "nvc0/nve4_compute.h"
27
28 #include "codegen/nv50_ir_driver.h"
29
30 #ifdef DEBUG
31 static void nve4_compute_dump_launch_desc(const struct nve4_cp_launch_desc *);
32 static void gp100_compute_dump_launch_desc(const struct gp100_cp_launch_desc *);
33 #endif
34
35
36 int
37 nve4_screen_compute_setup(struct nvc0_screen *screen,
38 struct nouveau_pushbuf *push)
39 {
40 struct nouveau_device *dev = screen->base.device;
41 struct nouveau_object *chan = screen->base.channel;
42 int i;
43 int ret;
44 uint32_t obj_class;
45 uint64_t address;
46
47 switch (dev->chipset & ~0xf) {
48 case 0x100:
49 case 0xf0:
50 obj_class = NVF0_COMPUTE_CLASS; /* GK110 */
51 break;
52 case 0xe0:
53 obj_class = NVE4_COMPUTE_CLASS; /* GK104 */
54 break;
55 case 0x110:
56 obj_class = GM107_COMPUTE_CLASS;
57 break;
58 case 0x120:
59 obj_class = GM200_COMPUTE_CLASS;
60 break;
61 default:
62 NOUVEAU_ERR("unsupported chipset: NV%02x\n", dev->chipset);
63 return -1;
64 }
65
66 ret = nouveau_object_new(chan, 0xbeef00c0, obj_class, NULL, 0,
67 &screen->compute);
68 if (ret) {
69 NOUVEAU_ERR("Failed to allocate compute object: %d\n", ret);
70 return ret;
71 }
72
73 BEGIN_NVC0(push, SUBC_CP(NV01_SUBCHAN_OBJECT), 1);
74 PUSH_DATA (push, screen->compute->oclass);
75
76 BEGIN_NVC0(push, NVE4_CP(TEMP_ADDRESS_HIGH), 2);
77 PUSH_DATAh(push, screen->tls->offset);
78 PUSH_DATA (push, screen->tls->offset);
79 /* No idea why there are 2. Divide size by 2 to be safe.
80 * Actually this might be per-MP TEMP size and looks like I'm only using
81 * 2 MPs instead of all 8.
82 */
83 BEGIN_NVC0(push, NVE4_CP(MP_TEMP_SIZE_HIGH(0)), 3);
84 PUSH_DATAh(push, screen->tls->size / screen->mp_count);
85 PUSH_DATA (push, (screen->tls->size / screen->mp_count) & ~0x7fff);
86 PUSH_DATA (push, 0xff);
87 BEGIN_NVC0(push, NVE4_CP(MP_TEMP_SIZE_HIGH(1)), 3);
88 PUSH_DATAh(push, screen->tls->size / screen->mp_count);
89 PUSH_DATA (push, (screen->tls->size / screen->mp_count) & ~0x7fff);
90 PUSH_DATA (push, 0xff);
91
92 /* Unified address space ? Who needs that ? Certainly not OpenCL.
93 *
94 * FATAL: Buffers with addresses inside [0x1000000, 0x3000000] will NOT be
95 * accessible. We cannot prevent that at the moment, so expect failure.
96 */
97 BEGIN_NVC0(push, NVE4_CP(LOCAL_BASE), 1);
98 PUSH_DATA (push, 0xff << 24);
99 BEGIN_NVC0(push, NVE4_CP(SHARED_BASE), 1);
100 PUSH_DATA (push, 0xfe << 24);
101
102 BEGIN_NVC0(push, NVE4_CP(CODE_ADDRESS_HIGH), 2);
103 PUSH_DATAh(push, screen->text->offset);
104 PUSH_DATA (push, screen->text->offset);
105
106 BEGIN_NVC0(push, SUBC_CP(0x0310), 1);
107 PUSH_DATA (push, (obj_class >= NVF0_COMPUTE_CLASS) ? 0x400 : 0x300);
108
109 /* NOTE: these do not affect the state used by the 3D object */
110 BEGIN_NVC0(push, NVE4_CP(TIC_ADDRESS_HIGH), 3);
111 PUSH_DATAh(push, screen->txc->offset);
112 PUSH_DATA (push, screen->txc->offset);
113 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
114 BEGIN_NVC0(push, NVE4_CP(TSC_ADDRESS_HIGH), 3);
115 PUSH_DATAh(push, screen->txc->offset + 65536);
116 PUSH_DATA (push, screen->txc->offset + 65536);
117 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
118
119 if (obj_class >= NVF0_COMPUTE_CLASS) {
120 /* The blob calls GK110_COMPUTE.FIRMWARE[0x6], along with the args (0x1)
121 * passed with GK110_COMPUTE.GRAPH.SCRATCH[0x2]. This is currently
122 * disabled because our firmware doesn't support these commands and the
123 * GPU hangs if they are used. */
124 BEGIN_NIC0(push, SUBC_CP(0x0248), 64);
125 for (i = 63; i >= 0; i--)
126 PUSH_DATA(push, 0x38000 | i);
127 IMMED_NVC0(push, SUBC_CP(NV50_GRAPH_SERIALIZE), 0);
128 }
129
130 BEGIN_NVC0(push, NVE4_CP(TEX_CB_INDEX), 1);
131 PUSH_DATA (push, 7); /* does not interfere with 3D */
132
133 /* Disabling this UNK command avoid a read fault when using texelFetch()
134 * from a compute shader for weird reasons.
135 if (obj_class == NVF0_COMPUTE_CLASS)
136 IMMED_NVC0(push, SUBC_CP(0x02c4), 1);
137 */
138
139 address = screen->uniform_bo->offset + NVC0_CB_AUX_INFO(5);
140
141 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
142 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
143 PUSH_DATAh(push, address + NVC0_CB_AUX_MS_INFO);
144 PUSH_DATA (push, address + NVC0_CB_AUX_MS_INFO);
145 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
146 PUSH_DATA (push, 64);
147 PUSH_DATA (push, 1);
148 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 17);
149 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
150 PUSH_DATA (push, 0); /* 0 */
151 PUSH_DATA (push, 0);
152 PUSH_DATA (push, 1); /* 1 */
153 PUSH_DATA (push, 0);
154 PUSH_DATA (push, 0); /* 2 */
155 PUSH_DATA (push, 1);
156 PUSH_DATA (push, 1); /* 3 */
157 PUSH_DATA (push, 1);
158 PUSH_DATA (push, 2); /* 4 */
159 PUSH_DATA (push, 0);
160 PUSH_DATA (push, 3); /* 5 */
161 PUSH_DATA (push, 0);
162 PUSH_DATA (push, 2); /* 6 */
163 PUSH_DATA (push, 1);
164 PUSH_DATA (push, 3); /* 7 */
165 PUSH_DATA (push, 1);
166
167 #ifdef NOUVEAU_NVE4_MP_TRAP_HANDLER
168 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
169 PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_TRAP_INFO_PTR);
170 PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_TRAP_INFO_PTR);
171 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
172 PUSH_DATA (push, 28);
173 PUSH_DATA (push, 1);
174 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 8);
175 PUSH_DATA (push, 1);
176 PUSH_DATA (push, screen->parm->offset + NVE4_CP_PARAM_TRAP_INFO);
177 PUSH_DATAh(push, screen->parm->offset + NVE4_CP_PARAM_TRAP_INFO);
178 PUSH_DATA (push, screen->tls->offset);
179 PUSH_DATAh(push, screen->tls->offset);
180 PUSH_DATA (push, screen->tls->size / 2); /* MP TEMP block size */
181 PUSH_DATA (push, screen->tls->size / 2 / 64); /* warp TEMP block size */
182 PUSH_DATA (push, 0); /* warp cfstack size */
183 #endif
184
185 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
186 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
187
188 return 0;
189 }
190
191 static void
192 gm107_compute_validate_surfaces(struct nvc0_context *nvc0,
193 struct pipe_image_view *view, int slot)
194 {
195 struct nv04_resource *res = nv04_resource(view->resource);
196 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
197 struct nvc0_screen *screen = nvc0->screen;
198 struct nouveau_bo *txc = nvc0->screen->txc;
199 struct nv50_tic_entry *tic;
200 uint64_t address;
201 const int s = 5;
202
203 tic = nv50_tic_entry(nvc0->images_tic[s][slot]);
204
205 res = nv04_resource(tic->pipe.texture);
206 nvc0_update_tic(nvc0, tic, res);
207
208 if (tic->id < 0) {
209 tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
210
211 /* upload the texture view */
212 PUSH_SPACE(push, 16);
213 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
214 PUSH_DATAh(push, txc->offset + (tic->id * 32));
215 PUSH_DATA (push, txc->offset + (tic->id * 32));
216 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
217 PUSH_DATA (push, 32);
218 PUSH_DATA (push, 1);
219 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 9);
220 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
221 PUSH_DATAp(push, &tic->tic[0], 8);
222
223 BEGIN_NIC0(push, NVE4_CP(TIC_FLUSH), 1);
224 PUSH_DATA (push, (tic->id << 4) | 1);
225 } else
226 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
227 BEGIN_NIC0(push, NVE4_CP(TEX_CACHE_CTL), 1);
228 PUSH_DATA (push, (tic->id << 4) | 1);
229 }
230 nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
231
232 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
233 res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
234
235 BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RD);
236
237 address = screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
238
239 /* upload the texture handle */
240 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
241 PUSH_DATAh(push, address + NVC0_CB_AUX_TEX_INFO(slot + 32));
242 PUSH_DATA (push, address + NVC0_CB_AUX_TEX_INFO(slot + 32));
243 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
244 PUSH_DATA (push, 4);
245 PUSH_DATA (push, 0x1);
246 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 2);
247 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
248 PUSH_DATA (push, tic->id);
249
250 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
251 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
252 }
253
254 static void
255 nve4_compute_validate_surfaces(struct nvc0_context *nvc0)
256 {
257 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
258 uint64_t address;
259 const int s = 5;
260 int i, j;
261
262 if (!nvc0->images_dirty[s])
263 return;
264
265 address = nvc0->screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
266
267 for (i = 0; i < NVC0_MAX_IMAGES; ++i) {
268 struct pipe_image_view *view = &nvc0->images[s][i];
269
270 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
271 PUSH_DATAh(push, address + NVC0_CB_AUX_SU_INFO(i));
272 PUSH_DATA (push, address + NVC0_CB_AUX_SU_INFO(i));
273 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
274 PUSH_DATA (push, 16 * 4);
275 PUSH_DATA (push, 0x1);
276 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 16);
277 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
278
279 if (view->resource) {
280 struct nv04_resource *res = nv04_resource(view->resource);
281
282 if (res->base.target == PIPE_BUFFER) {
283 if (view->access & PIPE_IMAGE_ACCESS_WRITE)
284 nvc0_mark_image_range_valid(view);
285 }
286
287 nve4_set_surface_info(push, view, nvc0);
288 BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RDWR);
289
290 if (nvc0->screen->base.class_3d >= GM107_3D_CLASS)
291 gm107_compute_validate_surfaces(nvc0, view, i);
292 } else {
293 for (j = 0; j < 16; j++)
294 PUSH_DATA(push, 0);
295 }
296 }
297 }
298
299 /* Thankfully, textures with samplers follow the normal rules. */
300 static void
301 nve4_compute_validate_samplers(struct nvc0_context *nvc0)
302 {
303 bool need_flush = nve4_validate_tsc(nvc0, 5);
304 if (need_flush) {
305 BEGIN_NVC0(nvc0->base.pushbuf, NVE4_CP(TSC_FLUSH), 1);
306 PUSH_DATA (nvc0->base.pushbuf, 0);
307 }
308
309 /* Invalidate all 3D samplers because they are aliased. */
310 for (int s = 0; s < 5; s++)
311 nvc0->samplers_dirty[s] = ~0;
312 nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLERS;
313 }
314
315 /* (Code duplicated at bottom for various non-convincing reasons.
316 * E.g. we might want to use the COMPUTE subchannel to upload TIC/TSC
317 * entries to avoid a subchannel switch.
318 * Same for texture cache flushes.
319 * Also, the bufctx differs, and more IFs in the 3D version looks ugly.)
320 */
321 static void nve4_compute_validate_textures(struct nvc0_context *);
322
323 static void
324 nve4_compute_set_tex_handles(struct nvc0_context *nvc0)
325 {
326 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
327 struct nvc0_screen *screen = nvc0->screen;
328 uint64_t address;
329 const unsigned s = nvc0_shader_stage(PIPE_SHADER_COMPUTE);
330 unsigned i, n;
331 uint32_t dirty = nvc0->textures_dirty[s] | nvc0->samplers_dirty[s];
332
333 if (!dirty)
334 return;
335 i = ffs(dirty) - 1;
336 n = util_logbase2(dirty) + 1 - i;
337 assert(n);
338
339 address = screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
340
341 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
342 PUSH_DATAh(push, address + NVC0_CB_AUX_TEX_INFO(i));
343 PUSH_DATA (push, address + NVC0_CB_AUX_TEX_INFO(i));
344 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
345 PUSH_DATA (push, n * 4);
346 PUSH_DATA (push, 0x1);
347 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + n);
348 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
349 PUSH_DATAp(push, &nvc0->tex_handles[s][i], n);
350
351 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
352 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
353
354 nvc0->textures_dirty[s] = 0;
355 nvc0->samplers_dirty[s] = 0;
356 }
357
358 static void
359 nve4_compute_validate_constbufs(struct nvc0_context *nvc0)
360 {
361 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
362 const int s = 5;
363
364 while (nvc0->constbuf_dirty[s]) {
365 int i = ffs(nvc0->constbuf_dirty[s]) - 1;
366 nvc0->constbuf_dirty[s] &= ~(1 << i);
367
368 if (nvc0->constbuf[s][i].user) {
369 struct nouveau_bo *bo = nvc0->screen->uniform_bo;
370 const unsigned base = NVC0_CB_USR_INFO(s);
371 const unsigned size = nvc0->constbuf[s][0].size;
372 assert(i == 0); /* we really only want OpenGL uniforms here */
373 assert(nvc0->constbuf[s][0].u.data);
374
375 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
376 PUSH_DATAh(push, bo->offset + base);
377 PUSH_DATA (push, bo->offset + base);
378 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
379 PUSH_DATA (push, size);
380 PUSH_DATA (push, 0x1);
381 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (size / 4));
382 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
383 PUSH_DATAp(push, nvc0->constbuf[s][0].u.data, size / 4);
384 }
385 else {
386 struct nv04_resource *res =
387 nv04_resource(nvc0->constbuf[s][i].u.buf);
388 if (res) {
389 uint64_t address
390 = nvc0->screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
391
392 assert(i > 0); /* we really only want uniform buffer objects */
393
394 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
395 PUSH_DATAh(push, address + NVC0_CB_AUX_UBO_INFO(i - 1));
396 PUSH_DATA (push, address + NVC0_CB_AUX_UBO_INFO(i - 1));
397 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
398 PUSH_DATA (push, 4 * 4);
399 PUSH_DATA (push, 0x1);
400 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 4);
401 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
402
403 PUSH_DATA (push, res->address + nvc0->constbuf[s][i].offset);
404 PUSH_DATAh(push, res->address + nvc0->constbuf[s][i].offset);
405 PUSH_DATA (push, nvc0->constbuf[5][i].size);
406 PUSH_DATA (push, 0);
407 BCTX_REFN(nvc0->bufctx_cp, CP_CB(i), res, RD);
408
409 res->cb_bindings[s] |= 1 << i;
410 }
411 }
412 }
413
414 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
415 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
416 }
417
418 static void
419 nve4_compute_validate_buffers(struct nvc0_context *nvc0)
420 {
421 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
422 uint64_t address;
423 const int s = 5;
424 int i;
425
426 address = nvc0->screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
427
428 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
429 PUSH_DATAh(push, address + NVC0_CB_AUX_BUF_INFO(0));
430 PUSH_DATA (push, address + NVC0_CB_AUX_BUF_INFO(0));
431 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
432 PUSH_DATA (push, 4 * NVC0_MAX_BUFFERS * 4);
433 PUSH_DATA (push, 0x1);
434 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 4 * NVC0_MAX_BUFFERS);
435 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
436
437 for (i = 0; i < NVC0_MAX_BUFFERS; i++) {
438 if (nvc0->buffers[s][i].buffer) {
439 struct nv04_resource *res =
440 nv04_resource(nvc0->buffers[s][i].buffer);
441 PUSH_DATA (push, res->address + nvc0->buffers[s][i].buffer_offset);
442 PUSH_DATAh(push, res->address + nvc0->buffers[s][i].buffer_offset);
443 PUSH_DATA (push, nvc0->buffers[s][i].buffer_size);
444 PUSH_DATA (push, 0);
445 BCTX_REFN(nvc0->bufctx_cp, CP_BUF, res, RDWR);
446 util_range_add(&res->valid_buffer_range,
447 nvc0->buffers[s][i].buffer_offset,
448 nvc0->buffers[s][i].buffer_offset +
449 nvc0->buffers[s][i].buffer_size);
450 } else {
451 PUSH_DATA (push, 0);
452 PUSH_DATA (push, 0);
453 PUSH_DATA (push, 0);
454 PUSH_DATA (push, 0);
455 }
456 }
457 }
458
459 static struct nvc0_state_validate
460 validate_list_cp[] = {
461 { nvc0_compprog_validate, NVC0_NEW_CP_PROGRAM },
462 { nve4_compute_validate_textures, NVC0_NEW_CP_TEXTURES },
463 { nve4_compute_validate_samplers, NVC0_NEW_CP_SAMPLERS },
464 { nve4_compute_set_tex_handles, NVC0_NEW_CP_TEXTURES |
465 NVC0_NEW_CP_SAMPLERS },
466 { nve4_compute_validate_surfaces, NVC0_NEW_CP_SURFACES },
467 { nvc0_compute_validate_globals, NVC0_NEW_CP_GLOBALS },
468 { nve4_compute_validate_buffers, NVC0_NEW_CP_BUFFERS },
469 { nve4_compute_validate_constbufs, NVC0_NEW_CP_CONSTBUF },
470 };
471
472 static bool
473 nve4_state_validate_cp(struct nvc0_context *nvc0, uint32_t mask)
474 {
475 bool ret;
476
477 ret = nvc0_state_validate(nvc0, mask, validate_list_cp,
478 ARRAY_SIZE(validate_list_cp), &nvc0->dirty_cp,
479 nvc0->bufctx_cp);
480
481 if (unlikely(nvc0->state.flushed))
482 nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, true);
483 return ret;
484 }
485
486 static void
487 nve4_compute_upload_input(struct nvc0_context *nvc0,
488 const struct pipe_grid_info *info)
489 {
490 struct nvc0_screen *screen = nvc0->screen;
491 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
492 struct nvc0_program *cp = nvc0->compprog;
493 uint64_t address;
494
495 address = screen->uniform_bo->offset + NVC0_CB_AUX_INFO(5);
496
497 if (cp->parm_size) {
498 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
499 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_USR_INFO(5));
500 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_USR_INFO(5));
501 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
502 PUSH_DATA (push, cp->parm_size);
503 PUSH_DATA (push, 0x1);
504 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (cp->parm_size / 4));
505 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
506 PUSH_DATAp(push, info->input, cp->parm_size / 4);
507 }
508 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
509 PUSH_DATAh(push, address + NVC0_CB_AUX_GRID_INFO(0));
510 PUSH_DATA (push, address + NVC0_CB_AUX_GRID_INFO(0));
511 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
512 PUSH_DATA (push, 8 * 4);
513 PUSH_DATA (push, 0x1);
514
515 if (unlikely(info->indirect)) {
516 struct nv04_resource *res = nv04_resource(info->indirect);
517 uint32_t offset = res->offset + info->indirect_offset;
518
519 nouveau_pushbuf_space(push, 32, 0, 1);
520 PUSH_REFN(push, res->bo, NOUVEAU_BO_RD | res->domain);
521
522 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 8);
523 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
524 PUSH_DATAp(push, info->block, 3);
525 nouveau_pushbuf_data(push, res->bo, offset,
526 NVC0_IB_ENTRY_1_NO_PREFETCH | 3 * 4);
527 } else {
528 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 8);
529 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
530 PUSH_DATAp(push, info->block, 3);
531 PUSH_DATAp(push, info->grid, 3);
532 }
533 PUSH_DATA (push, 0);
534 PUSH_DATA (push, info->work_dim);
535
536 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
537 PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
538 }
539
540 static inline uint8_t
541 nve4_compute_derive_cache_split(struct nvc0_context *nvc0, uint32_t shared_size)
542 {
543 if (shared_size > (32 << 10))
544 return NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1;
545 if (shared_size > (16 << 10))
546 return NVE4_3D_CACHE_SPLIT_32K_SHARED_32K_L1;
547 return NVC1_3D_CACHE_SPLIT_16K_SHARED_48K_L1;
548 }
549
550 static void
551 nve4_compute_setup_launch_desc(struct nvc0_context *nvc0,
552 struct nve4_cp_launch_desc *desc,
553 const struct pipe_grid_info *info)
554 {
555 const struct nvc0_screen *screen = nvc0->screen;
556 const struct nvc0_program *cp = nvc0->compprog;
557
558 nve4_cp_launch_desc_init_default(desc);
559
560 desc->entry = nvc0_program_symbol_offset(cp, info->pc);
561
562 desc->griddim_x = info->grid[0];
563 desc->griddim_y = info->grid[1];
564 desc->griddim_z = info->grid[2];
565 desc->blockdim_x = info->block[0];
566 desc->blockdim_y = info->block[1];
567 desc->blockdim_z = info->block[2];
568
569 desc->shared_size = align(cp->cp.smem_size, 0x100);
570 desc->local_size_p = (cp->hdr[1] & 0xfffff0) + align(cp->cp.lmem_size, 0x10);
571 desc->local_size_n = 0;
572 desc->cstack_size = 0x800;
573 desc->cache_split = nve4_compute_derive_cache_split(nvc0, cp->cp.smem_size);
574
575 desc->gpr_alloc = cp->num_gprs;
576 desc->bar_alloc = cp->num_barriers;
577
578 // Only bind user uniforms and the driver constant buffer through the
579 // launch descriptor because UBOs are sticked to the driver cb to avoid the
580 // limitation of 8 CBs.
581 if (nvc0->constbuf[5][0].user || cp->parm_size) {
582 nve4_cp_launch_desc_set_cb(desc, 0, screen->uniform_bo,
583 NVC0_CB_USR_INFO(5), 1 << 16);
584 }
585 nve4_cp_launch_desc_set_cb(desc, 7, screen->uniform_bo,
586 NVC0_CB_AUX_INFO(5), 1 << 11);
587 }
588
589 static void
590 gp100_compute_setup_launch_desc(struct nvc0_context *nvc0,
591 struct gp100_cp_launch_desc *desc,
592 const struct pipe_grid_info *info)
593 {
594 const struct nvc0_screen *screen = nvc0->screen;
595 const struct nvc0_program *cp = nvc0->compprog;
596
597 gp100_cp_launch_desc_init_default(desc);
598
599 desc->entry = nvc0_program_symbol_offset(cp, info->pc);
600
601 desc->griddim_x = info->grid[0];
602 desc->griddim_y = info->grid[1];
603 desc->griddim_z = info->grid[2];
604 desc->blockdim_x = info->block[0];
605 desc->blockdim_y = info->block[1];
606 desc->blockdim_z = info->block[2];
607
608 desc->shared_size = align(cp->cp.smem_size, 0x100);
609 desc->local_size_p = (cp->hdr[1] & 0xfffff0) + align(cp->cp.lmem_size, 0x10);
610 desc->local_size_n = 0;
611 desc->cstack_size = 0x800;
612
613 desc->gpr_alloc = cp->num_gprs;
614 desc->bar_alloc = cp->num_barriers;
615
616 // Only bind user uniforms and the driver constant buffer through the
617 // launch descriptor because UBOs are sticked to the driver cb to avoid the
618 // limitation of 8 CBs.
619 if (nvc0->constbuf[5][0].user || cp->parm_size) {
620 gp100_cp_launch_desc_set_cb(desc, 0, screen->uniform_bo,
621 NVC0_CB_USR_INFO(5), 1 << 16);
622 }
623 gp100_cp_launch_desc_set_cb(desc, 7, screen->uniform_bo,
624 NVC0_CB_AUX_INFO(5), 1 << 11);
625 }
626
627 static inline void *
628 nve4_compute_alloc_launch_desc(struct nouveau_context *nv,
629 struct nouveau_bo **pbo, uint64_t *pgpuaddr)
630 {
631 uint8_t *ptr = nouveau_scratch_get(nv, 512, pgpuaddr, pbo);
632 if (!ptr)
633 return NULL;
634 if (*pgpuaddr & 255) {
635 unsigned adj = 256 - (*pgpuaddr & 255);
636 ptr += adj;
637 *pgpuaddr += adj;
638 }
639 return ptr;
640 }
641
642 static void
643 nve4_upload_indirect_desc(struct nouveau_pushbuf *push,
644 struct nv04_resource *res, uint64_t gpuaddr,
645 uint32_t length, uint32_t bo_offset)
646 {
647 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
648 PUSH_DATAh(push, gpuaddr);
649 PUSH_DATA (push, gpuaddr);
650 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
651 PUSH_DATA (push, length);
652 PUSH_DATA (push, 1);
653
654 nouveau_pushbuf_space(push, 32, 0, 1);
655 PUSH_REFN(push, res->bo, NOUVEAU_BO_RD | res->domain);
656
657 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (length / 4));
658 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x08 << 1));
659 nouveau_pushbuf_data(push, res->bo, bo_offset,
660 NVC0_IB_ENTRY_1_NO_PREFETCH | length);
661 }
662
663 void
664 nve4_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
665 {
666 struct nvc0_context *nvc0 = nvc0_context(pipe);
667 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
668 void *desc;
669 uint64_t desc_gpuaddr;
670 struct nouveau_bo *desc_bo;
671 int ret;
672
673 desc = nve4_compute_alloc_launch_desc(&nvc0->base, &desc_bo, &desc_gpuaddr);
674 if (!desc) {
675 ret = -1;
676 goto out;
677 }
678 BCTX_REFN_bo(nvc0->bufctx_cp, CP_DESC, NOUVEAU_BO_GART | NOUVEAU_BO_RD,
679 desc_bo);
680
681 ret = !nve4_state_validate_cp(nvc0, ~0);
682 if (ret)
683 goto out;
684
685 if (nvc0->screen->compute->oclass >= GP100_COMPUTE_CLASS)
686 gp100_compute_setup_launch_desc(nvc0, desc, info);
687 else
688 nve4_compute_setup_launch_desc(nvc0, desc, info);
689
690 nve4_compute_upload_input(nvc0, info);
691
692 #ifdef DEBUG
693 if (debug_get_num_option("NV50_PROG_DEBUG", 0)) {
694 if (nvc0->screen->compute->oclass >= GP100_COMPUTE_CLASS)
695 gp100_compute_dump_launch_desc(desc);
696 else
697 nve4_compute_dump_launch_desc(desc);
698 }
699 #endif
700
701 if (unlikely(info->indirect)) {
702 struct nv04_resource *res = nv04_resource(info->indirect);
703 uint32_t offset = res->offset + info->indirect_offset;
704
705 /* upload the descriptor */
706 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
707 PUSH_DATAh(push, desc_gpuaddr);
708 PUSH_DATA (push, desc_gpuaddr);
709 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
710 PUSH_DATA (push, 256);
711 PUSH_DATA (push, 1);
712 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (256 / 4));
713 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x08 << 1));
714 PUSH_DATAp(push, (const uint32_t *)desc, 256 / 4);
715
716 if (nvc0->screen->compute->oclass >= GP100_COMPUTE_CLASS) {
717 nve4_upload_indirect_desc(push, res, desc_gpuaddr + 48, 12, offset);
718 } else {
719 /* overwrite griddim_x and griddim_y as two 32-bits integers even
720 * if griddim_y must be a 16-bits integer */
721 nve4_upload_indirect_desc(push, res, desc_gpuaddr + 48, 8, offset);
722
723 /* overwrite the 16 high bits of griddim_y with griddim_z because
724 * we need (z << 16) | x */
725 nve4_upload_indirect_desc(push, res, desc_gpuaddr + 54, 4, offset + 8);
726 }
727 }
728
729 /* upload descriptor and flush */
730 BEGIN_NVC0(push, NVE4_CP(LAUNCH_DESC_ADDRESS), 1);
731 PUSH_DATA (push, desc_gpuaddr >> 8);
732 BEGIN_NVC0(push, NVE4_CP(LAUNCH), 1);
733 PUSH_DATA (push, 0x3);
734 BEGIN_NVC0(push, SUBC_CP(NV50_GRAPH_SERIALIZE), 1);
735 PUSH_DATA (push, 0);
736
737 out:
738 if (ret)
739 NOUVEAU_ERR("Failed to launch grid !\n");
740 nouveau_scratch_done(&nvc0->base);
741 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_DESC);
742 }
743
744
745 #define NVE4_TIC_ENTRY_INVALID 0x000fffff
746
747 static void
748 nve4_compute_validate_textures(struct nvc0_context *nvc0)
749 {
750 struct nouveau_bo *txc = nvc0->screen->txc;
751 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
752 const unsigned s = 5;
753 unsigned i;
754 uint32_t commands[2][32];
755 unsigned n[2] = { 0, 0 };
756
757 for (i = 0; i < nvc0->num_textures[s]; ++i) {
758 struct nv50_tic_entry *tic = nv50_tic_entry(nvc0->textures[s][i]);
759 struct nv04_resource *res;
760 const bool dirty = !!(nvc0->textures_dirty[s] & (1 << i));
761
762 if (!tic) {
763 nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID;
764 continue;
765 }
766 res = nv04_resource(tic->pipe.texture);
767 nvc0_update_tic(nvc0, tic, res);
768
769 if (tic->id < 0) {
770 tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
771
772 PUSH_SPACE(push, 16);
773 BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
774 PUSH_DATAh(push, txc->offset + (tic->id * 32));
775 PUSH_DATA (push, txc->offset + (tic->id * 32));
776 BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
777 PUSH_DATA (push, 32);
778 PUSH_DATA (push, 1);
779 BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 9);
780 PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
781 PUSH_DATAp(push, &tic->tic[0], 8);
782
783 commands[0][n[0]++] = (tic->id << 4) | 1;
784 } else
785 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
786 commands[1][n[1]++] = (tic->id << 4) | 1;
787 }
788 nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
789
790 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
791 res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
792
793 nvc0->tex_handles[s][i] &= ~NVE4_TIC_ENTRY_INVALID;
794 nvc0->tex_handles[s][i] |= tic->id;
795 if (dirty)
796 BCTX_REFN(nvc0->bufctx_cp, CP_TEX(i), res, RD);
797 }
798 for (; i < nvc0->state.num_textures[s]; ++i) {
799 nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID;
800 nvc0->textures_dirty[s] |= 1 << i;
801 }
802
803 if (n[0]) {
804 BEGIN_NIC0(push, NVE4_CP(TIC_FLUSH), n[0]);
805 PUSH_DATAp(push, commands[0], n[0]);
806 }
807 if (n[1]) {
808 BEGIN_NIC0(push, NVE4_CP(TEX_CACHE_CTL), n[1]);
809 PUSH_DATAp(push, commands[1], n[1]);
810 }
811
812 nvc0->state.num_textures[s] = nvc0->num_textures[s];
813
814 /* Invalidate all 3D textures because they are aliased. */
815 for (int s = 0; s < 5; s++) {
816 for (int i = 0; i < nvc0->num_textures[s]; i++)
817 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
818 nvc0->textures_dirty[s] = ~0;
819 }
820 nvc0->dirty_3d |= NVC0_NEW_3D_TEXTURES;
821 }
822
823
824 #ifdef DEBUG
825 static const char *nve4_cache_split_name(unsigned value)
826 {
827 switch (value) {
828 case NVC1_3D_CACHE_SPLIT_16K_SHARED_48K_L1: return "16K_SHARED_48K_L1";
829 case NVE4_3D_CACHE_SPLIT_32K_SHARED_32K_L1: return "32K_SHARED_32K_L1";
830 case NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1: return "48K_SHARED_16K_L1";
831 default:
832 return "(invalid)";
833 }
834 }
835
836 static void
837 nve4_compute_dump_launch_desc(const struct nve4_cp_launch_desc *desc)
838 {
839 const uint32_t *data = (const uint32_t *)desc;
840 unsigned i;
841 bool zero = false;
842
843 debug_printf("COMPUTE LAUNCH DESCRIPTOR:\n");
844
845 for (i = 0; i < sizeof(*desc); i += 4) {
846 if (data[i / 4]) {
847 debug_printf("[%x]: 0x%08x\n", i, data[i / 4]);
848 zero = false;
849 } else
850 if (!zero) {
851 debug_printf("...\n");
852 zero = true;
853 }
854 }
855
856 debug_printf("entry = 0x%x\n", desc->entry);
857 debug_printf("grid dimensions = %ux%ux%u\n",
858 desc->griddim_x, desc->griddim_y, desc->griddim_z);
859 debug_printf("block dimensions = %ux%ux%u\n",
860 desc->blockdim_x, desc->blockdim_y, desc->blockdim_z);
861 debug_printf("s[] size: 0x%x\n", desc->shared_size);
862 debug_printf("l[] size: -0x%x / +0x%x\n",
863 desc->local_size_n, desc->local_size_p);
864 debug_printf("stack size: 0x%x\n", desc->cstack_size);
865 debug_printf("barrier count: %u\n", desc->bar_alloc);
866 debug_printf("$r count: %u\n", desc->gpr_alloc);
867 debug_printf("cache split: %s\n", nve4_cache_split_name(desc->cache_split));
868 debug_printf("linked tsc: %d\n", desc->linked_tsc);
869
870 for (i = 0; i < 8; ++i) {
871 uint64_t address;
872 uint32_t size = desc->cb[i].size;
873 bool valid = !!(desc->cb_mask & (1 << i));
874
875 address = ((uint64_t)desc->cb[i].address_h << 32) | desc->cb[i].address_l;
876
877 if (!valid && !address && !size)
878 continue;
879 debug_printf("CB[%u]: address = 0x%"PRIx64", size 0x%x%s\n",
880 i, address, size, valid ? "" : " (invalid)");
881 }
882 }
883
884 static void
885 gp100_compute_dump_launch_desc(const struct gp100_cp_launch_desc *desc)
886 {
887 const uint32_t *data = (const uint32_t *)desc;
888 unsigned i;
889 bool zero = false;
890
891 debug_printf("COMPUTE LAUNCH DESCRIPTOR:\n");
892
893 for (i = 0; i < sizeof(*desc); i += 4) {
894 if (data[i / 4]) {
895 debug_printf("[%x]: 0x%08x\n", i, data[i / 4]);
896 zero = false;
897 } else
898 if (!zero) {
899 debug_printf("...\n");
900 zero = true;
901 }
902 }
903
904 debug_printf("entry = 0x%x\n", desc->entry);
905 debug_printf("grid dimensions = %ux%ux%u\n",
906 desc->griddim_x, desc->griddim_y, desc->griddim_z);
907 debug_printf("block dimensions = %ux%ux%u\n",
908 desc->blockdim_x, desc->blockdim_y, desc->blockdim_z);
909 debug_printf("s[] size: 0x%x\n", desc->shared_size);
910 debug_printf("l[] size: -0x%x / +0x%x\n",
911 desc->local_size_n, desc->local_size_p);
912 debug_printf("stack size: 0x%x\n", desc->cstack_size);
913 debug_printf("barrier count: %u\n", desc->bar_alloc);
914 debug_printf("$r count: %u\n", desc->gpr_alloc);
915 debug_printf("linked tsc: %d\n", desc->linked_tsc);
916
917 for (i = 0; i < 8; ++i) {
918 uint64_t address;
919 uint32_t size = desc->cb[i].size_sh4 << 4;
920 bool valid = !!(desc->cb_mask & (1 << i));
921
922 address = ((uint64_t)desc->cb[i].address_h << 32) | desc->cb[i].address_l;
923
924 if (!valid && !address && !size)
925 continue;
926 debug_printf("CB[%u]: address = 0x%"PRIx64", size 0x%x%s\n",
927 i, address, size, valid ? "" : " (invalid)");
928 }
929 }
930 #endif
931
932 #ifdef NOUVEAU_NVE4_MP_TRAP_HANDLER
933 static void
934 nve4_compute_trap_info(struct nvc0_context *nvc0)
935 {
936 struct nvc0_screen *screen = nvc0->screen;
937 struct nouveau_bo *bo = screen->parm;
938 int ret, i;
939 volatile struct nve4_mp_trap_info *info;
940 uint8_t *map;
941
942 ret = nouveau_bo_map(bo, NOUVEAU_BO_RDWR, nvc0->base.client);
943 if (ret)
944 return;
945 map = (uint8_t *)bo->map;
946 info = (volatile struct nve4_mp_trap_info *)(map + NVE4_CP_PARAM_TRAP_INFO);
947
948 if (info->lock) {
949 debug_printf("trapstat = %08x\n", info->trapstat);
950 debug_printf("warperr = %08x\n", info->warperr);
951 debug_printf("PC = %x\n", info->pc);
952 debug_printf("tid = %u %u %u\n",
953 info->tid[0], info->tid[1], info->tid[2]);
954 debug_printf("ctaid = %u %u %u\n",
955 info->ctaid[0], info->ctaid[1], info->ctaid[2]);
956 for (i = 0; i <= 63; ++i)
957 debug_printf("$r%i = %08x\n", i, info->r[i]);
958 for (i = 0; i <= 6; ++i)
959 debug_printf("$p%i = %i\n", i, (info->flags >> i) & 1);
960 debug_printf("$c = %x\n", info->flags >> 12);
961 }
962 info->lock = 0;
963 }
964 #endif