src/gallium/drivers/nouveau/nvc0/nve4_compute.h

   1
   2 #ifndef NVE4_COMPUTE_H
   3 #define NVE4_COMPUTE_H
   4
   5 #include "nvc0/nve4_compute.xml.h"
   6
   7 /* Input space is implemented as c0[], to which we bind the screen->parm bo.
   8  */
   9 #define NVE4_CP_INPUT_USER           0x0000
  10 #define NVE4_CP_INPUT_USER_LIMIT     0x1000
  11 #define NVE4_CP_INPUT_GRID_INFO(i)  (0x1000 + (i) * 4)
  12 #define NVE4_CP_INPUT_NTID(i)       (0x1000 + (i) * 4)
  13 #define NVE4_CP_INPUT_NCTAID(i)     (0x100c + (i) * 4)
  14 #define NVE4_CP_INPUT_GRIDID         0x1018
  15 #define NVE4_CP_INPUT_TEX(i)        (0x1040 + (i) * 4)
  16 #define NVE4_CP_INPUT_TEX_STRIDE     4
  17 #define NVE4_CP_INPUT_TEX_MAX        32
  18 #define NVE4_CP_INPUT_MS_OFFSETS     0x10c0
  19 #define NVE4_CP_INPUT_SUF_STRIDE     64
  20 #define NVE4_CP_INPUT_SUF(i)        (0x1100 + (i) * NVE4_CP_INPUT_SUF_STRIDE)
  21 #define NVE4_CP_INPUT_SUF_MAX        32
  22 #define NVE4_CP_INPUT_TRAP_INFO_PTR  0x1900
  23 #define NVE4_CP_INPUT_TEMP_PTR       0x1908
  24 #define NVE4_CP_INPUT_MP_TEMP_SIZE   0x1910
  25 #define NVE4_CP_INPUT_WARP_TEMP_SIZE 0x1914
  26 #define NVE4_CP_INPUT_CSTACK_SIZE    0x1918
  27 #define NVE4_CP_INPUT_SIZE           0x1a00
  28 #define NVE4_CP_PARAM_TRAP_INFO      0x2000
  29 #define NVE4_CP_PARAM_TRAP_INFO_SZ  (1 << 16)
  30 #define NVE4_CP_PARAM_SIZE          (NVE4_CP_PARAM_TRAP_INFO + (1 << 16))
  31
  32 struct nve4_cp_launch_desc
  33 {
  34    u32 unk0[8];
  35    u32 entry;
  36    u32 unk9[3];
  37    u32 griddim_x    : 31;
  38    u32 unk12        : 1;
  39    u16 griddim_y;
  40    u16 griddim_z;
  41    u32 unk14[3];
  42    u16 shared_size; /* must be aligned to 0x100 */
  43    u16 unk15;
  44    u16 unk16;
  45    u16 blockdim_x;
  46    u16 blockdim_y;
  47    u16 blockdim_z;
  48    u32 cb_mask      : 8;
  49    u32 unk20_8      : 21;
  50    u32 cache_split  : 2;
  51    u32 unk20_31     : 1;
  52    u32 unk21[8];
  53    struct {
  54       u32 address_l;
  55       u32 address_h : 8;
  56       u32 reserved  : 7;
  57       u32 size      : 17;
  58    } cb[8];
  59    u32 local_size_p : 20;
  60    u32 unk45_20     : 7;
  61    u32 bar_alloc    : 5;
  62    u32 local_size_n : 20;
  63    u32 unk46_20     : 4;
  64    u32 gpr_alloc    : 8;
  65    u32 cstack_size  : 20;
  66    u32 unk47_20     : 12;
  67    u32 unk48[16];
  68 };
  69
  70 static inline void
  71 nve4_cp_launch_desc_init_default(struct nve4_cp_launch_desc *desc)
  72 {
  73    memset(desc, 0, sizeof(*desc));
  74
  75    desc->unk0[7]  = 0xbc000000;
  76    desc->unk9[2]  = 0x44014000;
  77    desc->unk47_20 = 0x300;
  78 }
  79
  80 static inline void
  81 nve4_cp_launch_desc_set_cb(struct nve4_cp_launch_desc *desc,
  82                            unsigned index,
  83                            struct nouveau_bo *bo,
  84                            uint32_t base, uint16_t size)
  85 {
  86    uint64_t address = bo->offset + base;
  87
  88    assert(index < 8);
  89    assert(!(base & 0xff));
  90
  91    desc->cb[index].address_l = address;
  92    desc->cb[index].address_h = address >> 32;
  93    desc->cb[index].size = size;
  94
  95    desc->cb_mask |= 1 << index;
  96 }
  97
  98 static inline void
  99 nve4_cp_launch_desc_set_ctx_cb(struct nve4_cp_launch_desc *desc,
 100                                unsigned index,
 101                                const struct nvc0_constbuf *cb)
 102 {
 103    assert(index < 8);
 104
 105    if (!cb->u.buf) {
 106       desc->cb_mask &= ~(1 << index);
 107    } else {
 108       const struct nv04_resource *buf = nv04_resource(cb->u.buf);
 109       assert(!cb->user);
 110       nve4_cp_launch_desc_set_cb(desc, index,
 111                                  buf->bo, buf->offset + cb->offset, cb->size);
 112    }
 113 }
 114
 115 struct nve4_mp_trap_info {
 116    u32 lock;
 117    u32 pc;
 118    u32 trapstat;
 119    u32 warperr;
 120    u32 tid[3];
 121    u32 ctaid[3];
 122    u32 pad028[2];
 123    u32 r[64];
 124    u32 flags;
 125    u32 pad134[3];
 126    u32 s[0x3000];
 127 };
 128
 129 #endif /* NVE4_COMPUTE_H */