src/gallium/drivers/nouveau/nvc0/nve4_compute.h

   1
   2 #ifndef NVE4_COMPUTE_H
   3 #define NVE4_COMPUTE_H
   4
   5 #include "nvc0/nve4_compute.xml.h"
   6
   7 struct nve4_cp_launch_desc
   8 {
   9    u32 unk0[8];
  10    u32 entry;
  11    u32 unk9[3];
  12    u32 griddim_x    : 31;
  13    u32 unk12        : 1;
  14    u16 griddim_y;
  15    u16 griddim_z;
  16    u32 unk14[3];
  17    u16 shared_size; /* must be aligned to 0x100 */
  18    u16 unk15;
  19    u16 unk16;
  20    u16 blockdim_x;
  21    u16 blockdim_y;
  22    u16 blockdim_z;
  23    u32 cb_mask      : 8;
  24    u32 unk20_8      : 21;
  25    u32 cache_split  : 2;
  26    u32 unk20_31     : 1;
  27    u32 unk21[8];
  28    struct {
  29       u32 address_l;
  30       u32 address_h : 8;
  31       u32 reserved  : 7;
  32       u32 size      : 17;
  33    } cb[8];
  34    u32 local_size_p : 20;
  35    u32 unk45_20     : 7;
  36    u32 bar_alloc    : 5;
  37    u32 local_size_n : 20;
  38    u32 unk46_20     : 4;
  39    u32 gpr_alloc    : 8;
  40    u32 cstack_size  : 20;
  41    u32 unk47_20     : 12;
  42    u32 unk48[16];
  43 };
  44
  45 static inline void
  46 nve4_cp_launch_desc_init_default(struct nve4_cp_launch_desc *desc)
  47 {
  48    memset(desc, 0, sizeof(*desc));
  49
  50    desc->unk0[7]  = 0xbc000000;
  51    desc->unk9[2]  = 0x44014000;
  52    desc->unk47_20 = 0x300;
  53 }
  54
  55 static inline void
  56 nve4_cp_launch_desc_set_cb(struct nve4_cp_launch_desc *desc,
  57                            unsigned index,
  58                            struct nouveau_bo *bo,
  59                            uint32_t base, uint32_t size)
  60 {
  61    uint64_t address = bo->offset + base;
  62
  63    assert(index < 8);
  64    assert(!(base & 0xff));
  65
  66    desc->cb[index].address_l = address;
  67    desc->cb[index].address_h = address >> 32;
  68    desc->cb[index].size = size;
  69
  70    desc->cb_mask |= 1 << index;
  71 }
  72
  73 struct nve4_mp_trap_info {
  74    u32 lock;
  75    u32 pc;
  76    u32 trapstat;
  77    u32 warperr;
  78    u32 tid[3];
  79    u32 ctaid[3];
  80    u32 pad028[2];
  81    u32 r[64];
  82    u32 flags;
  83    u32 pad134[3];
  84    u32 s[0x3000];
  85 };
  86
  87 #endif /* NVE4_COMPUTE_H */