src/gallium/drivers/nouveau/nvc0/qmdc3c0.c

   1 /*
   2  * Copyright 2020 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22 #include "qmd.h"
  23 #include "clc3c0qmd.h"
  24
  25 #define NVC3C0_QMDV02_02_VAL(a...) NVQMD_VAL(NVC3C0, QMDV02_02, ##a)
  26 #define NVC3C0_QMDV02_02_DEF(a...) NVQMD_DEF(NVC3C0, QMDV02_02, ##a)
  27 #define NVC3C0_QMDV02_02_IDX(a...) NVQMD_IDX(NVC3C0, QMDV02_02, ##a)
  28
  29 void
  30 NVC3C0QmdDump_V02_02(uint32_t *qmd)
  31 {
  32    NVC3C0_QMDV02_02_VAL(qmd, OUTER_PUT, "0x%x");
  33    NVC3C0_QMDV02_02_VAL(qmd, OUTER_OVERFLOW, "0x%x");
  34    NVC3C0_QMDV02_02_VAL(qmd, OUTER_GET, "0x%x");
  35    NVC3C0_QMDV02_02_VAL(qmd, OUTER_STICKY_OVERFLOW, "0x%x");
  36    NVC3C0_QMDV02_02_VAL(qmd, INNER_GET, "0x%x");
  37    NVC3C0_QMDV02_02_VAL(qmd, INNER_OVERFLOW, "0x%x");
  38    NVC3C0_QMDV02_02_VAL(qmd, INNER_PUT, "0x%x");
  39    NVC3C0_QMDV02_02_VAL(qmd, INNER_STICKY_OVERFLOW, "0x%x");
  40    NVC3C0_QMDV02_02_VAL(qmd, QMD_GROUP_ID, "0x%x");
  41    NVC3C0_QMDV02_02_VAL(qmd, SM_GLOBAL_CACHING_ENABLE, "0x%x");
  42    NVC3C0_QMDV02_02_DEF(qmd, RUN_CTA_IN_ONE_SM_PARTITION, FALSE, TRUE);
  43    NVC3C0_QMDV02_02_DEF(qmd, IS_QUEUE, FALSE, TRUE);
  44    NVC3C0_QMDV02_02_DEF(qmd, ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST, FALSE, TRUE);
  45    NVC3C0_QMDV02_02_DEF(qmd, SEMAPHORE_RELEASE_ENABLE0, FALSE, TRUE);
  46    NVC3C0_QMDV02_02_DEF(qmd, SEMAPHORE_RELEASE_ENABLE1, FALSE, TRUE);
  47    NVC3C0_QMDV02_02_DEF(qmd, REQUIRE_SCHEDULING_PCAS, FALSE, TRUE);
  48    NVC3C0_QMDV02_02_DEF(qmd, DEPENDENT_QMD_SCHEDULE_ENABLE, FALSE, TRUE);
  49    NVC3C0_QMDV02_02_DEF(qmd, DEPENDENT_QMD_TYPE, QUEUE, GRID);
  50    NVC3C0_QMDV02_02_DEF(qmd, DEPENDENT_QMD_FIELD_COPY, FALSE, TRUE);
  51    NVC3C0_QMDV02_02_VAL(qmd, QMD_RESERVED_B, "0x%x");
  52    NVC3C0_QMDV02_02_VAL(qmd, CIRCULAR_QUEUE_SIZE, "0x%x");
  53    NVC3C0_QMDV02_02_VAL(qmd, QMD_RESERVED_C, "0x%x");
  54    NVC3C0_QMDV02_02_DEF(qmd, INVALIDATE_TEXTURE_HEADER_CACHE, FALSE, TRUE);
  55    NVC3C0_QMDV02_02_DEF(qmd, INVALIDATE_TEXTURE_SAMPLER_CACHE, FALSE, TRUE);
  56    NVC3C0_QMDV02_02_DEF(qmd, INVALIDATE_TEXTURE_DATA_CACHE, FALSE, TRUE);
  57    NVC3C0_QMDV02_02_DEF(qmd, INVALIDATE_SHADER_DATA_CACHE, FALSE, TRUE);
  58    NVC3C0_QMDV02_02_DEF(qmd, INVALIDATE_INSTRUCTION_CACHE, FALSE, TRUE);
  59    NVC3C0_QMDV02_02_DEF(qmd, INVALIDATE_SHADER_CONSTANT_CACHE, FALSE, TRUE);
  60    NVC3C0_QMDV02_02_VAL(qmd, CTA_RASTER_WIDTH_RESUME, "0x%x");
  61    NVC3C0_QMDV02_02_VAL(qmd, CTA_RASTER_HEIGHT_RESUME, "0x%x");
  62    NVC3C0_QMDV02_02_VAL(qmd, CTA_RASTER_DEPTH_RESUME, "0x%x");
  63    NVC3C0_QMDV02_02_VAL(qmd, PROGRAM_OFFSET, "0x%x");
  64    NVC3C0_QMDV02_02_VAL(qmd, CIRCULAR_QUEUE_ADDR_LOWER, "0x%x");
  65    NVC3C0_QMDV02_02_VAL(qmd, CIRCULAR_QUEUE_ADDR_UPPER, "0x%x");
  66    NVC3C0_QMDV02_02_VAL(qmd, QMD_RESERVED_D, "0x%x");
  67    NVC3C0_QMDV02_02_VAL(qmd, CIRCULAR_QUEUE_ENTRY_SIZE, "0x%x");
  68    NVC3C0_QMDV02_02_VAL(qmd, CWD_REFERENCE_COUNT_ID, "0x%x");
  69    NVC3C0_QMDV02_02_VAL(qmd, CWD_REFERENCE_COUNT_DELTA_MINUS_ONE, "0x%x");
  70    NVC3C0_QMDV02_02_DEF(qmd, RELEASE_MEMBAR_TYPE, FE_NONE, FE_SYSMEMBAR);
  71    NVC3C0_QMDV02_02_DEF(qmd, CWD_REFERENCE_COUNT_INCR_ENABLE, FALSE, TRUE);
  72    NVC3C0_QMDV02_02_DEF(qmd, CWD_MEMBAR_TYPE, L1_NONE, L1_SYSMEMBAR, L1_MEMBAR);
  73    NVC3C0_QMDV02_02_DEF(qmd, SEQUENTIALLY_RUN_CTAS, FALSE, TRUE);
  74    NVC3C0_QMDV02_02_DEF(qmd, CWD_REFERENCE_COUNT_DECR_ENABLE, FALSE, TRUE);
  75    NVC3C0_QMDV02_02_DEF(qmd, API_VISIBLE_CALL_LIMIT, _32, NO_CHECK);
  76    NVC3C0_QMDV02_02_DEF(qmd, SAMPLER_INDEX, INDEPENDENTLY, VIA_HEADER_INDEX);
  77    NVC3C0_QMDV02_02_VAL(qmd, CTA_RASTER_WIDTH, "0x%x");
  78    NVC3C0_QMDV02_02_VAL(qmd, CTA_RASTER_HEIGHT, "0x%x");
  79    NVC3C0_QMDV02_02_VAL(qmd, QMD_RESERVED13A, "0x%x");
  80    NVC3C0_QMDV02_02_VAL(qmd, CTA_RASTER_DEPTH, "0x%x");
  81    NVC3C0_QMDV02_02_VAL(qmd, QMD_RESERVED14A, "0x%x");
  82    NVC3C0_QMDV02_02_VAL(qmd, DEPENDENT_QMD_POINTER, "0x%x");
  83    NVC3C0_QMDV02_02_VAL(qmd, QUEUE_ENTRIES_PER_CTA_MINUS_ONE, "0x%x");
  84    NVC3C0_QMDV02_02_VAL(qmd, COALESCE_WAITING_PERIOD, "0x%x");
  85    NVC3C0_QMDV02_02_VAL(qmd, SHARED_MEMORY_SIZE, "0x%x");
  86    NVC3C0_QMDV02_02_VAL(qmd, MIN_SM_CONFIG_SHARED_MEM_SIZE, "0x%x");
  87    NVC3C0_QMDV02_02_VAL(qmd, MAX_SM_CONFIG_SHARED_MEM_SIZE, "0x%x");
  88    NVC3C0_QMDV02_02_VAL(qmd, QMD_VERSION, "0x%x");
  89    NVC3C0_QMDV02_02_VAL(qmd, QMD_MAJOR_VERSION, "0x%x");
  90    NVC3C0_QMDV02_02_VAL(qmd, QMD_RESERVED_H, "0x%x");
  91    NVC3C0_QMDV02_02_VAL(qmd, CTA_THREAD_DIMENSION0, "0x%x");
  92    NVC3C0_QMDV02_02_VAL(qmd, CTA_THREAD_DIMENSION1, "0x%x");
  93    NVC3C0_QMDV02_02_VAL(qmd, CTA_THREAD_DIMENSION2, "0x%x");
  94    for (int i = 0; i < 8; i++)
  95       NVC3C0_QMDV02_02_IDX(qmd, CONSTANT_BUFFER_VALID, i, FALSE, TRUE);
  96    NVC3C0_QMDV02_02_VAL(qmd, REGISTER_COUNT_V, "0x%x");
  97    NVC3C0_QMDV02_02_VAL(qmd, TARGET_SM_CONFIG_SHARED_MEM_SIZE, "0x%x");
  98    NVC3C0_QMDV02_02_VAL(qmd, FREE_CTA_SLOTS_EMPTY_SM, "0x%x");
  99    NVC3C0_QMDV02_02_VAL(qmd, SM_DISABLE_MASK_LOWER, "0x%x");
 100    NVC3C0_QMDV02_02_VAL(qmd, SM_DISABLE_MASK_UPPER, "0x%x");
 101    NVC3C0_QMDV02_02_VAL(qmd, RELEASE0_ADDRESS_LOWER, "0x%x");
 102    NVC3C0_QMDV02_02_VAL(qmd, RELEASE0_ADDRESS_UPPER, "0x%x");
 103    NVC3C0_QMDV02_02_VAL(qmd, QMD_RESERVED_J, "0x%x");
 104    NVC3C0_QMDV02_02_DEF(qmd, RELEASE0_REDUCTION_OP, RED_ADD,
 105                                                     RED_MIN,
 106                                                     RED_MAX,
 107                                                     RED_INC,
 108                                                     RED_DEC,
 109                                                     RED_AND,
 110                                                     RED_OR,
 111                                                     RED_XOR);
 112    NVC3C0_QMDV02_02_VAL(qmd, QMD_RESERVED_K, "0x%x");
 113    NVC3C0_QMDV02_02_DEF(qmd, RELEASE0_REDUCTION_FORMAT, UNSIGNED_32, SIGNED_32);
 114    NVC3C0_QMDV02_02_DEF(qmd, RELEASE0_REDUCTION_ENABLE, FALSE, TRUE);
 115    NVC3C0_QMDV02_02_DEF(qmd, RELEASE0_STRUCTURE_SIZE, FOUR_WORDS, ONE_WORD);
 116    NVC3C0_QMDV02_02_VAL(qmd, RELEASE0_PAYLOAD, "0x%x");
 117    NVC3C0_QMDV02_02_VAL(qmd, RELEASE1_ADDRESS_LOWER, "0x%x");
 118    NVC3C0_QMDV02_02_VAL(qmd, RELEASE1_ADDRESS_UPPER, "0x%x");
 119    NVC3C0_QMDV02_02_VAL(qmd, QMD_RESERVED_L, "0x%x");
 120    NVC3C0_QMDV02_02_DEF(qmd, RELEASE1_REDUCTION_OP, RED_ADD,
 121                                                     RED_MIN,
 122                                                     RED_MAX,
 123                                                     RED_INC,
 124                                                     RED_DEC,
 125                                                     RED_AND,
 126                                                     RED_OR,
 127                                                     RED_XOR);
 128    NVC3C0_QMDV02_02_VAL(qmd, QMD_RESERVED_M, "0x%x");
 129    NVC3C0_QMDV02_02_DEF(qmd, RELEASE1_REDUCTION_FORMAT, UNSIGNED_32, SIGNED_32);
 130    NVC3C0_QMDV02_02_DEF(qmd, RELEASE1_REDUCTION_ENABLE, FALSE, TRUE);
 131    NVC3C0_QMDV02_02_DEF(qmd, RELEASE1_STRUCTURE_SIZE, FOUR_WORDS, ONE_WORD);
 132    NVC3C0_QMDV02_02_VAL(qmd, RELEASE1_PAYLOAD, "0x%x");
 133    NVC3C0_QMDV02_02_VAL(qmd, SHADER_LOCAL_MEMORY_LOW_SIZE, "0x%x");
 134    NVC3C0_QMDV02_02_VAL(qmd, QMD_RESERVED_N, "0x%x");
 135    NVC3C0_QMDV02_02_VAL(qmd, BARRIER_COUNT, "0x%x");
 136    NVC3C0_QMDV02_02_VAL(qmd, SHADER_LOCAL_MEMORY_HIGH_SIZE, "0x%x");
 137    NVC3C0_QMDV02_02_VAL(qmd, REGISTER_COUNT, "0x%x");
 138    NVC3C0_QMDV02_02_VAL(qmd, SHADER_LOCAL_MEMORY_CRS_SIZE, "0x%x");
 139    NVC3C0_QMDV02_02_VAL(qmd, SASS_VERSION, "0x%x");
 140    for (int i = 0; i < 8; i++) {
 141       NVC3C0_QMDV02_02_VAL(qmd, CONSTANT_BUFFER_ADDR_LOWER, i, "0x%x");
 142       NVC3C0_QMDV02_02_VAL(qmd, CONSTANT_BUFFER_ADDR_UPPER, i, "0x%x");
 143       NVC3C0_QMDV02_02_VAL(qmd, CONSTANT_BUFFER_RESERVED_ADDR, i, "0x%x");
 144       NVC3C0_QMDV02_02_IDX(qmd, CONSTANT_BUFFER_INVALIDATE, i, FALSE, TRUE);
 145       NVC3C0_QMDV02_02_VAL(qmd, CONSTANT_BUFFER_SIZE_SHIFTED4, i, "0x%x");
 146    }
 147    NVC3C0_QMDV02_02_VAL(qmd, PROGRAM_ADDRESS_LOWER, "0x%x");
 148    NVC3C0_QMDV02_02_VAL(qmd, PROGRAM_ADDRESS_UPPER, "0x%x");
 149    NVC3C0_QMDV02_02_VAL(qmd, QMD_RESERVED_S, "0x%x");
 150    NVC3C0_QMDV02_02_VAL(qmd, HW_ONLY_INNER_GET, "0x%x");
 151    NVC3C0_QMDV02_02_VAL(qmd, HW_ONLY_REQUIRE_SCHEDULING_PCAS, "0x%x");
 152    NVC3C0_QMDV02_02_VAL(qmd, HW_ONLY_INNER_PUT, "0x%x");
 153    NVC3C0_QMDV02_02_VAL(qmd, HW_ONLY_SCG_TYPE, "0x%x");
 154    NVC3C0_QMDV02_02_VAL(qmd, HW_ONLY_SPAN_LIST_HEAD_INDEX, "0x%x");
 155    NVC3C0_QMDV02_02_VAL(qmd, QMD_RESERVED_Q, "0x%x");
 156    NVC3C0_QMDV02_02_DEF(qmd, HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID, FALSE, TRUE);
 157    NVC3C0_QMDV02_02_VAL(qmd, HW_ONLY_SKED_NEXT_QMD_POINTER, "0x%x");
 158    NVC3C0_QMDV02_02_VAL(qmd, QMD_SPARE_G, "0x%x");
 159    NVC3C0_QMDV02_02_VAL(qmd, QMD_SPARE_H, "0x%x");
 160    NVC3C0_QMDV02_02_VAL(qmd, QMD_SPARE_I, "0x%x");
 161    NVC3C0_QMDV02_02_VAL(qmd, QMD_SPARE_J, "0x%x");
 162    NVC3C0_QMDV02_02_VAL(qmd, QMD_SPARE_K, "0x%x");
 163    NVC3C0_QMDV02_02_VAL(qmd, QMD_SPARE_L, "0x%x");
 164    NVC3C0_QMDV02_02_VAL(qmd, QMD_SPARE_M, "0x%x");
 165    NVC3C0_QMDV02_02_VAL(qmd, QMD_SPARE_N, "0x%x");
 166    NVC3C0_QMDV02_02_VAL(qmd, DEBUG_ID_UPPER, "0x%x");
 167    NVC3C0_QMDV02_02_VAL(qmd, DEBUG_ID_LOWER, "0x%x");
 168 }