src/gallium/drivers/nv04/nv04_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_inlines.h"
   3 #include "util/u_simple_screen.h"
   4
   5 #include "nv04_context.h"
   6 #include "nv04_screen.h"
   7
   8 static const char *
   9 nv04_screen_get_name(struct pipe_screen *screen)
  10 {
  11         struct nv04_screen *nv04screen = nv04_screen(screen);
  12         struct nouveau_device *dev = nv04screen->nvws->channel->device;
  13         static char buffer[128];
  14
  15         snprintf(buffer, sizeof(buffer), "NV%02X", dev->chipset);
  16         return buffer;
  17 }
  18
  19 static const char *
  20 nv04_screen_get_vendor(struct pipe_screen *screen)
  21 {
  22         return "nouveau";
  23 }
  24
  25 static int
  26 nv04_screen_get_param(struct pipe_screen *screen, int param)
  27 {
  28         switch (param) {
  29         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  30                 return 1;
  31         case PIPE_CAP_NPOT_TEXTURES:
  32                 return 0;
  33         case PIPE_CAP_TWO_SIDED_STENCIL:
  34                 return 0;
  35         case PIPE_CAP_GLSL:
  36                 return 0;
  37         case PIPE_CAP_S3TC:
  38                 return 0;
  39         case PIPE_CAP_ANISOTROPIC_FILTER:
  40                 return 0;
  41         case PIPE_CAP_POINT_SPRITE:
  42                 return 0;
  43         case PIPE_CAP_MAX_RENDER_TARGETS:
  44                 return 1;
  45         case PIPE_CAP_OCCLUSION_QUERY:
  46                 return 0;
  47         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  48                 return 0;
  49         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  50                 return 10;
  51         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  52                 return 0;
  53         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  54                 return 0;
  55         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  56                 return 0;
  57         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  58                 return 0;
  59         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  60                 return 1;
  61         case NOUVEAU_CAP_HW_VTXBUF:
  62         case NOUVEAU_CAP_HW_IDXBUF:
  63                 return 0;
  64         default:
  65                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  66                 return 0;
  67         }
  68 }
  69
  70 static float
  71 nv04_screen_get_paramf(struct pipe_screen *screen, int param)
  72 {
  73         switch (param) {
  74         case PIPE_CAP_MAX_LINE_WIDTH:
  75         case PIPE_CAP_MAX_LINE_WIDTH_AA:
  76                 return 0.0;
  77         case PIPE_CAP_MAX_POINT_WIDTH:
  78         case PIPE_CAP_MAX_POINT_WIDTH_AA:
  79                 return 0.0;
  80         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
  81                 return 0.0;
  82         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
  83                 return 0.0;
  84         default:
  85                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  86                 return 0.0;
  87         }
  88 }
  89
  90 static boolean
  91 nv04_screen_is_format_supported(struct pipe_screen *screen,
  92                                 enum pipe_format format,
  93                                 enum pipe_texture_target target,
  94                                 unsigned tex_usage, unsigned geom_flags)
  95 {
  96         if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET) {
  97                 switch (format) {
  98                 case PIPE_FORMAT_A8R8G8B8_UNORM:
  99                 case PIPE_FORMAT_R5G6B5_UNORM:
 100                 case PIPE_FORMAT_Z16_UNORM:
 101                         return TRUE;
 102                 default:
 103                         break;
 104                 }
 105         } else {
 106                 switch (format) {
 107                 case PIPE_FORMAT_A8R8G8B8_UNORM:
 108                 case PIPE_FORMAT_X8R8G8B8_UNORM:
 109                 case PIPE_FORMAT_A1R5G5B5_UNORM:
 110                 case PIPE_FORMAT_R5G6B5_UNORM:
 111                 case PIPE_FORMAT_L8_UNORM:
 112                 case PIPE_FORMAT_A8_UNORM:
 113                         return TRUE;
 114                 default:
 115                         break;
 116                 }
 117         }
 118
 119         return FALSE;
 120 }
 121
 122 static void *
 123 nv04_surface_map(struct pipe_screen *screen, struct pipe_surface *surface,
 124                  unsigned flags )
 125 {
 126         void *map;
 127         struct nv04_miptree *nv04mt = (struct nv04_miptree *)surface->texture;
 128
 129         map = pipe_buffer_map(screen, nv04mt->buffer, flags);
 130         if (!map)
 131                 return NULL;
 132
 133         return map + surface->offset;
 134 }
 135
 136 static void
 137 nv04_surface_unmap(struct pipe_screen *screen, struct pipe_surface *surface)
 138 {
 139         struct nv04_miptree *nv04mt = (struct nv04_miptree *)surface->texture;
 140
 141         pipe_buffer_unmap(screen, nv04mt->buffer);
 142 }
 143
 144 static void
 145 nv04_screen_destroy(struct pipe_screen *pscreen)
 146 {
 147         struct nv04_screen *screen = nv04_screen(pscreen);
 148         struct nouveau_winsys *nvws = screen->nvws;
 149
 150         nvws->notifier_free(&screen->sync);
 151         nvws->grobj_free(&screen->fahrenheit);
 152         nv04_surface_2d_takedown(&screen->eng2d);
 153
 154         FREE(pscreen);
 155 }
 156
 157 static struct pipe_buffer *
 158 nv04_surface_buffer(struct pipe_surface *surf)
 159 {
 160         struct nv04_miptree *mt = (struct nv04_miptree *)surf->texture;
 161
 162         return mt->buffer;
 163 }
 164
 165 struct pipe_screen *
 166 nv04_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws)
 167 {
 168         struct nv04_screen *screen = CALLOC_STRUCT(nv04_screen);
 169         unsigned fahrenheit_class = 0, sub3d_class = 0;
 170         unsigned chipset = nvws->channel->device->chipset;
 171         int ret;
 172
 173         if (!screen)
 174                 return NULL;
 175         screen->nvws = nvws;
 176
 177         if (chipset>=0x20) {
 178                 fahrenheit_class = 0;
 179                 sub3d_class = 0;
 180         } else if (chipset>=0x10) {
 181                 fahrenheit_class = NV10_DX5_TEXTURED_TRIANGLE;
 182                 sub3d_class = NV10_CONTEXT_SURFACES_3D;
 183         } else {
 184                 fahrenheit_class=NV04_DX5_TEXTURED_TRIANGLE;
 185                 sub3d_class = NV04_CONTEXT_SURFACES_3D;
 186         }
 187
 188         if (!fahrenheit_class) {
 189                 NOUVEAU_ERR("Unknown nv04 chipset: nv%02x\n", chipset);
 190                 return NULL;
 191         }
 192
 193         /* 2D engine setup */
 194         screen->eng2d = nv04_surface_2d_init(nvws);
 195         screen->eng2d->buf = nv04_surface_buffer;
 196
 197         /* 3D object */
 198         ret = nvws->grobj_alloc(nvws, fahrenheit_class, &screen->fahrenheit);
 199         if (ret) {
 200                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 201                 return NULL;
 202         }
 203
 204         /* 3D surface object */
 205         ret = nvws->grobj_alloc(nvws, sub3d_class, &screen->context_surfaces_3d);
 206         if (ret) {
 207                 NOUVEAU_ERR("Error creating 3D surface object: %d\n", ret);
 208                 return NULL;
 209         }
 210
 211         /* Notifier for sync purposes */
 212         ret = nvws->notifier_alloc(nvws, 1, &screen->sync);
 213         if (ret) {
 214                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 215                 nv04_screen_destroy(&screen->pipe);
 216                 return NULL;
 217         }
 218
 219         screen->pipe.winsys = ws;
 220         screen->pipe.destroy = nv04_screen_destroy;
 221
 222         screen->pipe.get_name = nv04_screen_get_name;
 223         screen->pipe.get_vendor = nv04_screen_get_vendor;
 224         screen->pipe.get_param = nv04_screen_get_param;
 225         screen->pipe.get_paramf = nv04_screen_get_paramf;
 226
 227         screen->pipe.is_format_supported = nv04_screen_is_format_supported;
 228
 229         screen->pipe.surface_map = nv04_surface_map;
 230         screen->pipe.surface_unmap = nv04_surface_unmap;
 231
 232         nv04_screen_init_miptree_functions(&screen->pipe);
 233         u_simple_screen_init(&screen->pipe);
 234
 235         return &screen->pipe;
 236 }
 237