src/gallium/drivers/nv04/nv04_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_inlines.h"
   3
   4 #include "nv04_context.h"
   5 #include "nv04_screen.h"
   6
   7 static int
   8 nv04_screen_get_param(struct pipe_screen *screen, int param)
   9 {
  10         switch (param) {
  11         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  12                 return 1;
  13         case PIPE_CAP_NPOT_TEXTURES:
  14                 return 0;
  15         case PIPE_CAP_TWO_SIDED_STENCIL:
  16                 return 0;
  17         case PIPE_CAP_GLSL:
  18                 return 0;
  19         case PIPE_CAP_S3TC:
  20                 return 0;
  21         case PIPE_CAP_ANISOTROPIC_FILTER:
  22                 return 0;
  23         case PIPE_CAP_POINT_SPRITE:
  24                 return 0;
  25         case PIPE_CAP_MAX_RENDER_TARGETS:
  26                 return 1;
  27         case PIPE_CAP_OCCLUSION_QUERY:
  28                 return 0;
  29         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  30                 return 0;
  31         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  32                 return 10;
  33         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  34                 return 0;
  35         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  36                 return 0;
  37         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  38                 return 0;
  39         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  40                 return 0;
  41         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  42                 return 1;
  43         case PIPE_CAP_TGSI_CONT_SUPPORTED:
  44                 return 0;
  45         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  46                 return 0;
  47         case NOUVEAU_CAP_HW_VTXBUF:
  48         case NOUVEAU_CAP_HW_IDXBUF:
  49                 return 0;
  50         default:
  51                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  52                 return 0;
  53         }
  54 }
  55
  56 static float
  57 nv04_screen_get_paramf(struct pipe_screen *screen, int param)
  58 {
  59         switch (param) {
  60         case PIPE_CAP_MAX_LINE_WIDTH:
  61         case PIPE_CAP_MAX_LINE_WIDTH_AA:
  62                 return 0.0;
  63         case PIPE_CAP_MAX_POINT_WIDTH:
  64         case PIPE_CAP_MAX_POINT_WIDTH_AA:
  65                 return 0.0;
  66         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
  67                 return 0.0;
  68         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
  69                 return 0.0;
  70         default:
  71                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  72                 return 0.0;
  73         }
  74 }
  75
  76 static boolean
  77 nv04_screen_is_format_supported(struct pipe_screen *screen,
  78                                 enum pipe_format format,
  79                                 enum pipe_texture_target target,
  80                                 unsigned tex_usage, unsigned geom_flags)
  81 {
  82         if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET) {
  83                 switch (format) {
  84                 case PIPE_FORMAT_A8R8G8B8_UNORM:
  85                 case PIPE_FORMAT_R5G6B5_UNORM:
  86                         return TRUE;
  87                 default:
  88                         break;
  89                 }
  90         } else
  91         if (tex_usage & PIPE_TEXTURE_USAGE_DEPTH_STENCIL) {
  92                 switch (format) {
  93                 case PIPE_FORMAT_Z16_UNORM:
  94                         return TRUE;
  95                 default:
  96                         break;
  97                 }
  98         } else {
  99                 switch (format) {
 100                 case PIPE_FORMAT_A8R8G8B8_UNORM:
 101                 case PIPE_FORMAT_X8R8G8B8_UNORM:
 102                 case PIPE_FORMAT_A1R5G5B5_UNORM:
 103                 case PIPE_FORMAT_R5G6B5_UNORM:
 104                 case PIPE_FORMAT_L8_UNORM:
 105                 case PIPE_FORMAT_A8_UNORM:
 106                         return TRUE;
 107                 default:
 108                         break;
 109                 }
 110         }
 111
 112         return FALSE;
 113 }
 114
 115 static void
 116 nv04_screen_destroy(struct pipe_screen *pscreen)
 117 {
 118         struct nv04_screen *screen = nv04_screen(pscreen);
 119
 120         nouveau_notifier_free(&screen->sync);
 121         nouveau_grobj_free(&screen->fahrenheit);
 122         nv04_surface_2d_takedown(&screen->eng2d);
 123
 124         FREE(pscreen);
 125 }
 126
 127 static struct pipe_buffer *
 128 nv04_surface_buffer(struct pipe_surface *surf)
 129 {
 130         struct nv04_miptree *mt = (struct nv04_miptree *)surf->texture;
 131
 132         return mt->buffer;
 133 }
 134
 135 struct pipe_screen *
 136 nv04_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 137 {
 138         struct nv04_screen *screen = CALLOC_STRUCT(nv04_screen);
 139         struct nouveau_channel *chan;
 140         struct pipe_screen *pscreen;
 141         unsigned fahrenheit_class = 0, sub3d_class = 0;
 142         int ret;
 143
 144         if (!screen)
 145                 return NULL;
 146         pscreen = &screen->base.base;
 147
 148         ret = nouveau_screen_init(&screen->base, dev);
 149         if (ret) {
 150                 nv04_screen_destroy(pscreen);
 151                 return NULL;
 152         }
 153         chan = screen->base.channel;
 154
 155         pscreen->winsys = ws;
 156         pscreen->destroy = nv04_screen_destroy;
 157         pscreen->get_param = nv04_screen_get_param;
 158         pscreen->get_paramf = nv04_screen_get_paramf;
 159         pscreen->is_format_supported = nv04_screen_is_format_supported;
 160
 161         nv04_screen_init_miptree_functions(pscreen);
 162         nv04_screen_init_transfer_functions(pscreen);
 163
 164         if (dev->chipset >= 0x20) {
 165                 fahrenheit_class = 0;
 166                 sub3d_class = 0;
 167         } else if (dev->chipset >= 0x10) {
 168                 fahrenheit_class = NV10_DX5_TEXTURED_TRIANGLE;
 169                 sub3d_class = NV10_CONTEXT_SURFACES_3D;
 170         } else {
 171                 fahrenheit_class=NV04_DX5_TEXTURED_TRIANGLE;
 172                 sub3d_class = NV04_CONTEXT_SURFACES_3D;
 173         }
 174
 175         if (!fahrenheit_class) {
 176                 NOUVEAU_ERR("Unknown nv04 chipset: nv%02x\n", dev->chipset);
 177                 return NULL;
 178         }
 179
 180         /* 3D object */
 181         ret = nouveau_grobj_alloc(chan, 0xbeef0001, fahrenheit_class,
 182                                   &screen->fahrenheit);
 183         if (ret) {
 184                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 185                 return NULL;
 186         }
 187         BIND_RING(chan, screen->fahrenheit, 7);
 188
 189         /* 3D surface object */
 190         ret = nouveau_grobj_alloc(chan, 0xbeef0002, sub3d_class,
 191                                   &screen->context_surfaces_3d);
 192         if (ret) {
 193                 NOUVEAU_ERR("Error creating 3D surface object: %d\n", ret);
 194                 return NULL;
 195         }
 196         BIND_RING(chan, screen->context_surfaces_3d, 6);
 197
 198         /* 2D engine setup */
 199         screen->eng2d = nv04_surface_2d_init(&screen->base);
 200         screen->eng2d->buf = nv04_surface_buffer;
 201
 202         /* Notifier for sync purposes */
 203         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 204         if (ret) {
 205                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 206                 nv04_screen_destroy(pscreen);
 207                 return NULL;
 208         }
 209
 210         return pscreen;
 211 }
 212