projects / mesa.git / blob
? search:


12df7fd1997b4c0eb07389e7f8cf37dc89cf2bef
[mesa.git] / src / gallium / drivers / nv04 / nv04_surface_2d.c
1 #include "pipe/p_context.h"
2 #include "pipe/p_format.h"
3 #include "util/u_format.h"
4 #include "util/u_math.h"
5 #include "util/u_memory.h"
6
7 #include "nouveau/nouveau_winsys.h"
8 #include "nouveau/nouveau_util.h"
9 #include "nouveau/nouveau_screen.h"
10 #include "nv04_surface_2d.h"
11
12 static INLINE int
13 nv04_surface_format(enum pipe_format format)
14 {
15 switch (format) {
16 case PIPE_FORMAT_A8_UNORM:
17 case PIPE_FORMAT_L8_UNORM:
18 case PIPE_FORMAT_I8_UNORM:
19 return NV04_CONTEXT_SURFACES_2D_FORMAT_Y8;
20 case PIPE_FORMAT_R16_SNORM:
21 case PIPE_FORMAT_R5G6B5_UNORM:
22 case PIPE_FORMAT_Z16_UNORM:
23 case PIPE_FORMAT_A8L8_UNORM:
24 return NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5;
25 case PIPE_FORMAT_X8R8G8B8_UNORM:
26 case PIPE_FORMAT_A8R8G8B8_UNORM:
27 return NV04_CONTEXT_SURFACES_2D_FORMAT_A8R8G8B8;
28 case PIPE_FORMAT_Z24S8_UNORM:
29 case PIPE_FORMAT_Z24X8_UNORM:
30 return NV04_CONTEXT_SURFACES_2D_FORMAT_Y32;
31 default:
32 return -1;
33 }
34 }
35
36 static INLINE int
37 nv04_rect_format(enum pipe_format format)
38 {
39 switch (format) {
40 case PIPE_FORMAT_A8_UNORM:
41 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
42 case PIPE_FORMAT_R5G6B5_UNORM:
43 case PIPE_FORMAT_A8L8_UNORM:
44 case PIPE_FORMAT_Z16_UNORM:
45 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A16R5G6B5;
46 case PIPE_FORMAT_X8R8G8B8_UNORM:
47 case PIPE_FORMAT_A8R8G8B8_UNORM:
48 case PIPE_FORMAT_Z24S8_UNORM:
49 case PIPE_FORMAT_Z24X8_UNORM:
50 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
51 default:
52 return -1;
53 }
54 }
55
56 static INLINE int
57 nv04_scaled_image_format(enum pipe_format format)
58 {
59 switch (format) {
60 case PIPE_FORMAT_A8_UNORM:
61 case PIPE_FORMAT_L8_UNORM:
62 case PIPE_FORMAT_I8_UNORM:
63 return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_Y8;
64 case PIPE_FORMAT_A1R5G5B5_UNORM:
65 return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A1R5G5B5;
66 case PIPE_FORMAT_A8R8G8B8_UNORM:
67 return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8;
68 case PIPE_FORMAT_X8R8G8B8_UNORM:
69 return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8;
70 case PIPE_FORMAT_R5G6B5_UNORM:
71 case PIPE_FORMAT_R16_SNORM:
72 case PIPE_FORMAT_A8L8_UNORM:
73 return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5;
74 default:
75 return -1;
76 }
77 }
78
79 static INLINE unsigned
80 nv04_swizzle_bits(unsigned x, unsigned y)
81 {
82 unsigned u = (x & 0x001) << 0 |
83 (x & 0x002) << 1 |
84 (x & 0x004) << 2 |
85 (x & 0x008) << 3 |
86 (x & 0x010) << 4 |
87 (x & 0x020) << 5 |
88 (x & 0x040) << 6 |
89 (x & 0x080) << 7 |
90 (x & 0x100) << 8 |
91 (x & 0x200) << 9 |
92 (x & 0x400) << 10 |
93 (x & 0x800) << 11;
94
95 unsigned v = (y & 0x001) << 1 |
96 (y & 0x002) << 2 |
97 (y & 0x004) << 3 |
98 (y & 0x008) << 4 |
99 (y & 0x010) << 5 |
100 (y & 0x020) << 6 |
101 (y & 0x040) << 7 |
102 (y & 0x080) << 8 |
103 (y & 0x100) << 9 |
104 (y & 0x200) << 10 |
105 (y & 0x400) << 11 |
106 (y & 0x800) << 12;
107 return v | u;
108 }
109
110 static int
111 nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx,
112 struct pipe_surface *dst, int dx, int dy,
113 struct pipe_surface *src, int sx, int sy,
114 int w, int h)
115 {
116 struct nouveau_channel *chan = ctx->swzsurf->channel;
117 struct nouveau_grobj *swzsurf = ctx->swzsurf;
118 struct nouveau_grobj *sifm = ctx->sifm;
119 struct nouveau_bo *src_bo = nouveau_bo(ctx->buf(src));
120 struct nouveau_bo *dst_bo = nouveau_bo(ctx->buf(dst));
121 const unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
122 /* Max width & height may not be the same on all HW, but must be POT */
123 const unsigned max_w = 1024;
124 const unsigned max_h = 1024;
125 unsigned sub_w = w > max_w ? max_w : w;
126 unsigned sub_h = h > max_h ? max_h : h;
127 unsigned x;
128 unsigned y;
129
130 /* Swizzled surfaces must be POT */
131 assert(util_is_pot(dst->width) && util_is_pot(dst->height));
132
133 /* If area is too large to copy in one shot we must copy it in POT chunks to meet alignment requirements */
134 assert(sub_w == w || util_is_pot(sub_w));
135 assert(sub_h == h || util_is_pot(sub_h));
136
137 MARK_RING (chan, 8 + ((w+sub_w)/sub_w)*((h+sub_h)/sub_h)*17, 2 +
138 ((w+sub_w)/sub_w)*((h+sub_h)/sub_h)*2);
139
140 BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_DMA_IMAGE, 1);
141 OUT_RELOCo(chan, dst_bo,
142 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
143
144 BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_FORMAT, 1);
145 OUT_RING (chan, nv04_surface_format(dst->format) |
146 log2i(dst->width) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_SHIFT |
147 log2i(dst->height) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_SHIFT);
148
149 BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE, 1);
150 OUT_RELOCo(chan, src_bo,
151 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
152 BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE, 1);
153 OUT_RING (chan, swzsurf->handle);
154
155 for (y = 0; y < h; y += sub_h) {
156 sub_h = MIN2(sub_h, h - y);
157
158 for (x = 0; x < w; x += sub_w) {
159 sub_w = MIN2(sub_w, w - x);
160
161 /* Must be 64-byte aligned */
162 assert(!((dst->offset + nv04_swizzle_bits(dx+x, dy+y) * util_format_get_blocksize(dst->texture->format)) & 63));
163
164 BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_OFFSET, 1);
165 OUT_RELOCl(chan, dst_bo, dst->offset + nv04_swizzle_bits(dx+x, dy+y) * util_format_get_blocksize(dst->texture->format),
166 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
167
168 BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION, 9);
169 OUT_RING (chan, NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE);
170 OUT_RING (chan, nv04_scaled_image_format(src->format));
171 OUT_RING (chan, NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY);
172 OUT_RING (chan, 0);
173 OUT_RING (chan, sub_h << NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H_SHIFT | sub_w);
174 OUT_RING (chan, 0);
175 OUT_RING (chan, sub_h << NV04_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H_SHIFT | sub_w);
176 OUT_RING (chan, 1 << 20);
177 OUT_RING (chan, 1 << 20);
178
179 BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_SIZE, 4);
180 OUT_RING (chan, sub_h << NV04_SCALED_IMAGE_FROM_MEMORY_SIZE_H_SHIFT | sub_w);
181 OUT_RING (chan, src_pitch |
182 NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER |
183 NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE);
184 OUT_RELOCl(chan, src_bo, src->offset + (sy+y) * src_pitch + (sx+x) * util_format_get_blocksize(src->texture->format),
185 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
186 OUT_RING (chan, 0);
187 }
188 }
189
190 return 0;
191 }
192
193 static int
194 nv04_surface_copy_m2mf(struct nv04_surface_2d *ctx,
195 struct pipe_surface *dst, int dx, int dy,
196 struct pipe_surface *src, int sx, int sy, int w, int h)
197 {
198 struct nouveau_channel *chan = ctx->m2mf->channel;
199 struct nouveau_grobj *m2mf = ctx->m2mf;
200 struct nouveau_bo *src_bo = nouveau_bo(ctx->buf(src));
201 struct nouveau_bo *dst_bo = nouveau_bo(ctx->buf(dst));
202 unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
203 unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
204 unsigned dst_offset = dst->offset + dy * dst_pitch +
205 dx * util_format_get_blocksize(dst->texture->format);
206 unsigned src_offset = src->offset + sy * src_pitch +
207 sx * util_format_get_blocksize(src->texture->format);
208
209 MARK_RING (chan, 3 + ((h / 2047) + 1) * 9, 2 + ((h / 2047) + 1) * 2);
210 BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_IN, 2);
211 OUT_RELOCo(chan, src_bo,
212 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
213 OUT_RELOCo(chan, dst_bo,
214 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
215
216 while (h) {
217 int count = (h > 2047) ? 2047 : h;
218
219 BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
220 OUT_RELOCl(chan, src_bo, src_offset,
221 NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD);
222 OUT_RELOCl(chan, dst_bo, dst_offset,
223 NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_WR);
224 OUT_RING (chan, src_pitch);
225 OUT_RING (chan, dst_pitch);
226 OUT_RING (chan, w * util_format_get_blocksize(src->texture->format));
227 OUT_RING (chan, count);
228 OUT_RING (chan, 0x0101);
229 OUT_RING (chan, 0);
230
231 h -= count;
232 src_offset += src_pitch * count;
233 dst_offset += dst_pitch * count;
234 }
235
236 return 0;
237 }
238
239 static int
240 nv04_surface_copy_blit(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
241 int dx, int dy, struct pipe_surface *src, int sx, int sy,
242 int w, int h)
243 {
244 struct nouveau_channel *chan = ctx->surf2d->channel;
245 struct nouveau_grobj *surf2d = ctx->surf2d;
246 struct nouveau_grobj *blit = ctx->blit;
247 struct nouveau_bo *src_bo = nouveau_bo(ctx->buf(src));
248 struct nouveau_bo *dst_bo = nouveau_bo(ctx->buf(dst));
249 unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
250 unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
251 int format;
252
253 format = nv04_surface_format(dst->format);
254 if (format < 0)
255 return 1;
256
257 MARK_RING (chan, 12, 4);
258 BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
259 OUT_RELOCo(chan, src_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
260 OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
261 BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
262 OUT_RING (chan, format);
263 OUT_RING (chan, (dst_pitch << 16) | src_pitch);
264 OUT_RELOCl(chan, src_bo, src->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
265 OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
266
267 BEGIN_RING(chan, blit, 0x0300, 3);
268 OUT_RING (chan, (sy << 16) | sx);
269 OUT_RING (chan, (dy << 16) | dx);
270 OUT_RING (chan, ( h << 16) | w);
271
272 return 0;
273 }
274
275 static void
276 nv04_surface_copy(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
277 int dx, int dy, struct pipe_surface *src, int sx, int sy,
278 int w, int h)
279 {
280 unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
281 unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
282 int src_linear = src->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR;
283 int dst_linear = dst->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR;
284
285 assert(src->format == dst->format);
286
287 /* Setup transfer to swizzle the texture to vram if needed */
288 if (src_linear && !dst_linear && w > 1 && h > 1) {
289 nv04_surface_copy_swizzle(ctx, dst, dx, dy, src, sx, sy, w, h);
290 return;
291 }
292
293 /* NV_CONTEXT_SURFACES_2D has buffer alignment restrictions, fallback
294 * to NV_MEMORY_TO_MEMORY_FORMAT in this case.
295 */
296 if ((src->offset & 63) || (dst->offset & 63) ||
297 (src_pitch & 63) || (dst_pitch & 63)) {
298 nv04_surface_copy_m2mf(ctx, dst, dx, dy, src, sx, sy, w, h);
299 return;
300 }
301
302 nv04_surface_copy_blit(ctx, dst, dx, dy, src, sx, sy, w, h);
303 }
304
305 static void
306 nv04_surface_fill(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
307 int dx, int dy, int w, int h, unsigned value)
308 {
309 struct nouveau_channel *chan = ctx->surf2d->channel;
310 struct nouveau_grobj *surf2d = ctx->surf2d;
311 struct nouveau_grobj *rect = ctx->rect;
312 struct nouveau_bo *dst_bo = nouveau_bo(ctx->buf(dst));
313 unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
314 int cs2d_format, gdirect_format;
315
316 cs2d_format = nv04_surface_format(dst->format);
317 assert(cs2d_format >= 0);
318
319 gdirect_format = nv04_rect_format(dst->format);
320 assert(gdirect_format >= 0);
321
322 MARK_RING (chan, 16, 4);
323 BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
324 OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
325 OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
326 BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
327 OUT_RING (chan, cs2d_format);
328 OUT_RING (chan, (dst_pitch << 16) | dst_pitch);
329 OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
330 OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
331
332 BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT, 1);
333 OUT_RING (chan, gdirect_format);
334 BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_COLOR1_A, 1);
335 OUT_RING (chan, value);
336 BEGIN_RING(chan, rect,
337 NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT(0), 2);
338 OUT_RING (chan, (dx << 16) | dy);
339 OUT_RING (chan, ( w << 16) | h);
340 }
341
342 void
343 nv04_surface_2d_takedown(struct nv04_surface_2d **pctx)
344 {
345 struct nv04_surface_2d *ctx;
346
347 if (!pctx || !*pctx)
348 return;
349 ctx = *pctx;
350 *pctx = NULL;
351
352 nouveau_notifier_free(&ctx->ntfy);
353 nouveau_grobj_free(&ctx->m2mf);
354 nouveau_grobj_free(&ctx->surf2d);
355 nouveau_grobj_free(&ctx->swzsurf);
356 nouveau_grobj_free(&ctx->rect);
357 nouveau_grobj_free(&ctx->blit);
358 nouveau_grobj_free(&ctx->sifm);
359
360 FREE(ctx);
361 }
362
363 struct nv04_surface_2d *
364 nv04_surface_2d_init(struct nouveau_screen *screen)
365 {
366 struct nv04_surface_2d *ctx = CALLOC_STRUCT(nv04_surface_2d);
367 struct nouveau_channel *chan = screen->channel;
368 unsigned handle = 0x88000000, class;
369 int ret;
370
371 if (!ctx)
372 return NULL;
373
374 ret = nouveau_notifier_alloc(chan, handle++, 1, &ctx->ntfy);
375 if (ret) {
376 nv04_surface_2d_takedown(&ctx);
377 return NULL;
378 }
379
380 ret = nouveau_grobj_alloc(chan, handle++, 0x0039, &ctx->m2mf);
381 if (ret) {
382 nv04_surface_2d_takedown(&ctx);
383 return NULL;
384 }
385
386 BEGIN_RING(chan, ctx->m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
387 OUT_RING (chan, ctx->ntfy->handle);
388
389 if (chan->device->chipset < 0x10)
390 class = NV04_CONTEXT_SURFACES_2D;
391 else
392 class = NV10_CONTEXT_SURFACES_2D;
393
394 ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->surf2d);
395 if (ret) {
396 nv04_surface_2d_takedown(&ctx);
397 return NULL;
398 }
399
400 BEGIN_RING(chan, ctx->surf2d,
401 NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
402 OUT_RING (chan, chan->vram->handle);
403 OUT_RING (chan, chan->vram->handle);
404
405 if (chan->device->chipset < 0x10)
406 class = NV04_IMAGE_BLIT;
407 else
408 class = NV12_IMAGE_BLIT;
409
410 ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->blit);
411 if (ret) {
412 nv04_surface_2d_takedown(&ctx);
413 return NULL;
414 }
415
416 BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_DMA_NOTIFY, 1);
417 OUT_RING (chan, ctx->ntfy->handle);
418 BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_SURFACE, 1);
419 OUT_RING (chan, ctx->surf2d->handle);
420 BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_OPERATION, 1);
421 OUT_RING (chan, NV04_IMAGE_BLIT_OPERATION_SRCCOPY);
422
423 ret = nouveau_grobj_alloc(chan, handle++, NV04_GDI_RECTANGLE_TEXT,
424 &ctx->rect);
425 if (ret) {
426 nv04_surface_2d_takedown(&ctx);
427 return NULL;
428 }
429
430 BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_DMA_NOTIFY, 1);
431 OUT_RING (chan, ctx->ntfy->handle);
432 BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_SURFACE, 1);
433 OUT_RING (chan, ctx->surf2d->handle);
434 BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_OPERATION, 1);
435 OUT_RING (chan, NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY);
436 BEGIN_RING(chan, ctx->rect,
437 NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT, 1);
438 OUT_RING (chan, NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_LE);
439
440 switch (chan->device->chipset & 0xf0) {
441 case 0x00:
442 case 0x10:
443 class = NV04_SWIZZLED_SURFACE;
444 break;
445 case 0x20:
446 class = NV20_SWIZZLED_SURFACE;
447 break;
448 case 0x30:
449 class = NV30_SWIZZLED_SURFACE;
450 break;
451 case 0x40:
452 case 0x60:
453 class = NV40_SWIZZLED_SURFACE;
454 break;
455 default:
456 /* Famous last words: this really can't happen.. */
457 assert(0);
458 break;
459 }
460
461 ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->swzsurf);
462 if (ret) {
463 nv04_surface_2d_takedown(&ctx);
464 return NULL;
465 }
466
467 switch (chan->device->chipset & 0xf0) {
468 case 0x10:
469 case 0x20:
470 class = NV10_SCALED_IMAGE_FROM_MEMORY;
471 break;
472 case 0x30:
473 class = NV30_SCALED_IMAGE_FROM_MEMORY;
474 break;
475 case 0x40:
476 case 0x60:
477 class = NV40_SCALED_IMAGE_FROM_MEMORY;
478 break;
479 default:
480 class = NV04_SCALED_IMAGE_FROM_MEMORY;
481 break;
482 }
483
484 ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->sifm);
485 if (ret) {
486 nv04_surface_2d_takedown(&ctx);
487 return NULL;
488 }
489
490 ctx->copy = nv04_surface_copy;
491 ctx->fill = nv04_surface_fill;
492 return ctx;
493 }