src/gallium/drivers/nv04/nv04_surface_2d.c

   1 #include "pipe/p_context.h"
   2 #include "pipe/p_format.h"
   3 #include "util/u_math.h"
   4 #include "util/u_memory.h"
   5
   6 #include "nouveau/nouveau_winsys.h"
   7 #include "nouveau/nouveau_util.h"
   8 #include "nouveau/nouveau_screen.h"
   9 #include "nv04_surface_2d.h"
  10
  11 static INLINE int
  12 nv04_surface_format(enum pipe_format format)
  13 {
  14         switch (format) {
  15         case PIPE_FORMAT_A8_UNORM:
  16         case PIPE_FORMAT_L8_UNORM:
  17         case PIPE_FORMAT_I8_UNORM:
  18                 return NV04_CONTEXT_SURFACES_2D_FORMAT_Y8;
  19         case PIPE_FORMAT_R16_SNORM:
  20         case PIPE_FORMAT_R5G6B5_UNORM:
  21         case PIPE_FORMAT_Z16_UNORM:
  22         case PIPE_FORMAT_A8L8_UNORM:
  23                 return NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5;
  24         case PIPE_FORMAT_X8R8G8B8_UNORM:
  25         case PIPE_FORMAT_A8R8G8B8_UNORM:
  26                 return NV04_CONTEXT_SURFACES_2D_FORMAT_A8R8G8B8;
  27         case PIPE_FORMAT_Z24S8_UNORM:
  28         case PIPE_FORMAT_Z24X8_UNORM:
  29                 return NV04_CONTEXT_SURFACES_2D_FORMAT_Y32;
  30         default:
  31                 return -1;
  32         }
  33 }
  34
  35 static INLINE int
  36 nv04_rect_format(enum pipe_format format)
  37 {
  38         switch (format) {
  39         case PIPE_FORMAT_A8_UNORM:
  40                 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
  41         case PIPE_FORMAT_R5G6B5_UNORM:
  42         case PIPE_FORMAT_A8L8_UNORM:
  43         case PIPE_FORMAT_Z16_UNORM:
  44                 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A16R5G6B5;
  45         case PIPE_FORMAT_X8R8G8B8_UNORM:
  46         case PIPE_FORMAT_A8R8G8B8_UNORM:
  47         case PIPE_FORMAT_Z24S8_UNORM:
  48         case PIPE_FORMAT_Z24X8_UNORM:
  49                 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
  50         default:
  51                 return -1;
  52         }
  53 }
  54
  55 static INLINE int
  56 nv04_scaled_image_format(enum pipe_format format)
  57 {
  58         switch (format) {
  59         case PIPE_FORMAT_A8_UNORM:
  60         case PIPE_FORMAT_L8_UNORM:
  61         case PIPE_FORMAT_I8_UNORM:
  62                 return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_Y8;
  63         case PIPE_FORMAT_A1R5G5B5_UNORM:
  64                 return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A1R5G5B5;
  65         case PIPE_FORMAT_A8R8G8B8_UNORM:
  66                 return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8;
  67         case PIPE_FORMAT_X8R8G8B8_UNORM:
  68                 return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8;
  69         case PIPE_FORMAT_R5G6B5_UNORM:
  70         case PIPE_FORMAT_R16_SNORM:
  71         case PIPE_FORMAT_A8L8_UNORM:
  72                 return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5;
  73         default:
  74                 return -1;
  75         }
  76 }
  77
  78 static INLINE unsigned
  79 nv04_swizzle_bits(unsigned x, unsigned y)
  80 {
  81         unsigned u = (x & 0x001) << 0 |
  82                      (x & 0x002) << 1 |
  83                      (x & 0x004) << 2 |
  84                      (x & 0x008) << 3 |
  85                      (x & 0x010) << 4 |
  86                      (x & 0x020) << 5 |
  87                      (x & 0x040) << 6 |
  88                      (x & 0x080) << 7 |
  89                      (x & 0x100) << 8 |
  90                      (x & 0x200) << 9 |
  91                      (x & 0x400) << 10 |
  92                      (x & 0x800) << 11;
  93
  94         unsigned v = (y & 0x001) << 1 |
  95                      (y & 0x002) << 2 |
  96                      (y & 0x004) << 3 |
  97                      (y & 0x008) << 4 |
  98                      (y & 0x010) << 5 |
  99                      (y & 0x020) << 6 |
 100                      (y & 0x040) << 7 |
 101                      (y & 0x080) << 8 |
 102                      (y & 0x100) << 9 |
 103                      (y & 0x200) << 10 |
 104                      (y & 0x400) << 11 |
 105                      (y & 0x800) << 12;
 106         return v | u;
 107 }
 108
 109 static int
 110 nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx,
 111                           struct pipe_surface *dst, int dx, int dy,
 112                           struct pipe_surface *src, int sx, int sy,
 113                           int w, int h)
 114 {
 115         struct nouveau_channel *chan = ctx->swzsurf->channel;
 116         struct nouveau_grobj *swzsurf = ctx->swzsurf;
 117         struct nouveau_grobj *sifm = ctx->sifm;
 118         struct nouveau_bo *src_bo = nouveau_bo(ctx->buf(src));
 119         struct nouveau_bo *dst_bo = nouveau_bo(ctx->buf(dst));
 120         const unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
 121         /* Max width & height may not be the same on all HW, but must be POT */
 122         const unsigned max_w = 1024;
 123         const unsigned max_h = 1024;
 124         unsigned sub_w = w > max_w ? max_w : w;
 125         unsigned sub_h = h > max_h ? max_h : h;
 126         unsigned x;
 127         unsigned y;
 128
 129         /* Swizzled surfaces must be POT  */
 130         assert(util_is_pot(dst->width) && util_is_pot(dst->height));
 131
 132         /* If area is too large to copy in one shot we must copy it in POT chunks to meet alignment requirements */
 133         assert(sub_w == w || util_is_pot(sub_w));
 134         assert(sub_h == h || util_is_pot(sub_h));
 135
 136         BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_DMA_IMAGE, 1);
 137         OUT_RELOCo(chan, dst_bo,
 138                          NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 139
 140         BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_FORMAT, 1);
 141         OUT_RING  (chan, nv04_surface_format(dst->format) |
 142                          log2i(dst->width) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_SHIFT |
 143                          log2i(dst->height) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_SHIFT);
 144
 145         BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE, 1);
 146         OUT_RELOCo(chan, src_bo,
 147                          NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 148         BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE, 1);
 149         OUT_RING  (chan, swzsurf->handle);
 150
 151         for (y = 0; y < h; y += sub_h) {
 152           sub_h = MIN2(sub_h, h - y);
 153
 154           for (x = 0; x < w; x += sub_w) {
 155             sub_w = MIN2(sub_w, w - x);
 156
 157             /* Must be 64-byte aligned */
 158             assert(!((dst->offset + nv04_swizzle_bits(dx+x, dy+y) * dst->texture->block.size) & 63));
 159
 160             BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_OFFSET, 1);
 161             OUT_RELOCl(chan, dst_bo, dst->offset + nv04_swizzle_bits(dx+x, dy+y) * dst->texture->block.size,
 162                              NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 163
 164             BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION, 9);
 165             OUT_RING  (chan, NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE);
 166             OUT_RING  (chan, nv04_scaled_image_format(src->format));
 167             OUT_RING  (chan, NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY);
 168             OUT_RING  (chan, 0);
 169             OUT_RING  (chan, sub_h << NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H_SHIFT | sub_w);
 170             OUT_RING  (chan, 0);
 171             OUT_RING  (chan, sub_h << NV04_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H_SHIFT | sub_w);
 172             OUT_RING  (chan, 1 << 20);
 173             OUT_RING  (chan, 1 << 20);
 174
 175             BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_SIZE, 4);
 176             OUT_RING  (chan, sub_h << NV04_SCALED_IMAGE_FROM_MEMORY_SIZE_H_SHIFT | sub_w);
 177             OUT_RING  (chan, src_pitch |
 178                              NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER |
 179                              NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE);
 180             OUT_RELOCl(chan, src_bo, src->offset + (sy+y) * src_pitch + (sx+x) * src->texture->block.size,
 181                              NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 182             OUT_RING  (chan, 0);
 183           }
 184         }
 185
 186         return 0;
 187 }
 188
 189 static int
 190 nv04_surface_copy_m2mf(struct nv04_surface_2d *ctx,
 191                        struct pipe_surface *dst, int dx, int dy,
 192                        struct pipe_surface *src, int sx, int sy, int w, int h)
 193 {
 194         struct nouveau_channel *chan = ctx->m2mf->channel;
 195         struct nouveau_grobj *m2mf = ctx->m2mf;
 196         struct nouveau_bo *src_bo = nouveau_bo(ctx->buf(src));
 197         struct nouveau_bo *dst_bo = nouveau_bo(ctx->buf(dst));
 198         unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
 199         unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
 200         unsigned dst_offset = dst->offset + dy * dst_pitch +
 201                               dx * dst->texture->block.size;
 202         unsigned src_offset = src->offset + sy * src_pitch +
 203                               sx * src->texture->block.size;
 204
 205         WAIT_RING (chan, 3 + ((h / 2047) + 1) * 9);
 206         BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_IN, 2);
 207         OUT_RELOCo(chan, src_bo,
 208                    NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 209         OUT_RELOCo(chan, dst_bo,
 210                    NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 211
 212         while (h) {
 213                 int count = (h > 2047) ? 2047 : h;
 214
 215                 BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
 216                 OUT_RELOCl(chan, src_bo, src_offset,
 217                            NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD);
 218                 OUT_RELOCl(chan, dst_bo, dst_offset,
 219                            NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_WR);
 220                 OUT_RING  (chan, src_pitch);
 221                 OUT_RING  (chan, dst_pitch);
 222                 OUT_RING  (chan, w * src->texture->block.size);
 223                 OUT_RING  (chan, count);
 224                 OUT_RING  (chan, 0x0101);
 225                 OUT_RING  (chan, 0);
 226
 227                 h -= count;
 228                 src_offset += src_pitch * count;
 229                 dst_offset += dst_pitch * count;
 230         }
 231
 232         return 0;
 233 }
 234
 235 static int
 236 nv04_surface_copy_blit(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
 237                        int dx, int dy, struct pipe_surface *src, int sx, int sy,
 238                        int w, int h)
 239 {
 240         struct nouveau_channel *chan = ctx->surf2d->channel;
 241         struct nouveau_grobj *surf2d = ctx->surf2d;
 242         struct nouveau_grobj *blit = ctx->blit;
 243         struct nouveau_bo *src_bo = nouveau_bo(ctx->buf(src));
 244         struct nouveau_bo *dst_bo = nouveau_bo(ctx->buf(dst));
 245         unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
 246         unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
 247         int format;
 248
 249         format = nv04_surface_format(dst->format);
 250         if (format < 0)
 251                 return 1;
 252
 253         WAIT_RING (chan, 12);
 254         BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
 255         OUT_RELOCo(chan, src_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 256         OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 257         BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
 258         OUT_RING  (chan, format);
 259         OUT_RING  (chan, (dst_pitch << 16) | src_pitch);
 260         OUT_RELOCl(chan, src_bo, src->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 261         OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 262
 263         BEGIN_RING(chan, blit, 0x0300, 3);
 264         OUT_RING  (chan, (sy << 16) | sx);
 265         OUT_RING  (chan, (dy << 16) | dx);
 266         OUT_RING  (chan, ( h << 16) |  w);
 267
 268         return 0;
 269 }
 270
 271 static void
 272 nv04_surface_copy(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
 273                   int dx, int dy, struct pipe_surface *src, int sx, int sy,
 274                   int w, int h)
 275 {
 276         unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
 277         unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
 278         int src_linear = src->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR;
 279         int dst_linear = dst->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR;
 280
 281         assert(src->format == dst->format);
 282
 283         /* Setup transfer to swizzle the texture to vram if needed */
 284         if (src_linear && !dst_linear && w > 1 && h > 1) {
 285            nv04_surface_copy_swizzle(ctx, dst, dx, dy, src, sx, sy, w, h);
 286            return;
 287         }
 288
 289         /* NV_CONTEXT_SURFACES_2D has buffer alignment restrictions, fallback
 290          * to NV_MEMORY_TO_MEMORY_FORMAT in this case.
 291          */
 292         if ((src->offset & 63) || (dst->offset & 63) ||
 293             (src_pitch & 63) || (dst_pitch & 63)) {
 294                 nv04_surface_copy_m2mf(ctx, dst, dx, dy, src, sx, sy, w, h);
 295                 return;
 296         }
 297
 298         nv04_surface_copy_blit(ctx, dst, dx, dy, src, sx, sy, w, h);
 299 }
 300
 301 static void
 302 nv04_surface_fill(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
 303                   int dx, int dy, int w, int h, unsigned value)
 304 {
 305         struct nouveau_channel *chan = ctx->surf2d->channel;
 306         struct nouveau_grobj *surf2d = ctx->surf2d;
 307         struct nouveau_grobj *rect = ctx->rect;
 308         struct nouveau_bo *dst_bo = nouveau_bo(ctx->buf(dst));
 309         unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
 310         int cs2d_format, gdirect_format;
 311
 312         cs2d_format = nv04_surface_format(dst->format);
 313         assert(cs2d_format >= 0);
 314
 315         gdirect_format = nv04_rect_format(dst->format);
 316         assert(gdirect_format >= 0);
 317
 318         WAIT_RING (chan, 16);
 319         BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
 320         OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 321         OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 322         BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
 323         OUT_RING  (chan, cs2d_format);
 324         OUT_RING  (chan, (dst_pitch << 16) | dst_pitch);
 325         OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 326         OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 327
 328         BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT, 1);
 329         OUT_RING  (chan, gdirect_format);
 330         BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_COLOR1_A, 1);
 331         OUT_RING  (chan, value);
 332         BEGIN_RING(chan, rect,
 333                    NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT(0), 2);
 334         OUT_RING  (chan, (dx << 16) | dy);
 335         OUT_RING  (chan, ( w << 16) |  h);
 336 }
 337
 338 void
 339 nv04_surface_2d_takedown(struct nv04_surface_2d **pctx)
 340 {
 341         struct nv04_surface_2d *ctx;
 342
 343         if (!pctx || !*pctx)
 344                 return;
 345         ctx = *pctx;
 346         *pctx = NULL;
 347
 348         nouveau_notifier_free(&ctx->ntfy);
 349         nouveau_grobj_free(&ctx->m2mf);
 350         nouveau_grobj_free(&ctx->surf2d);
 351         nouveau_grobj_free(&ctx->swzsurf);
 352         nouveau_grobj_free(&ctx->rect);
 353         nouveau_grobj_free(&ctx->blit);
 354         nouveau_grobj_free(&ctx->sifm);
 355
 356         FREE(ctx);
 357 }
 358
 359 struct nv04_surface_2d *
 360 nv04_surface_2d_init(struct nouveau_screen *screen)
 361 {
 362         struct nv04_surface_2d *ctx = CALLOC_STRUCT(nv04_surface_2d);
 363         struct nouveau_channel *chan = screen->channel;
 364         unsigned handle = 0x88000000, class;
 365         int ret;
 366
 367         if (!ctx)
 368                 return NULL;
 369
 370         ret = nouveau_notifier_alloc(chan, handle++, 1, &ctx->ntfy);
 371         if (ret) {
 372                 nv04_surface_2d_takedown(&ctx);
 373                 return NULL;
 374         }
 375
 376         ret = nouveau_grobj_alloc(chan, handle++, 0x0039, &ctx->m2mf);
 377         if (ret) {
 378                 nv04_surface_2d_takedown(&ctx);
 379                 return NULL;
 380         }
 381
 382         BEGIN_RING(chan, ctx->m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
 383         OUT_RING  (chan, ctx->ntfy->handle);
 384
 385         if (chan->device->chipset < 0x10)
 386                 class = NV04_CONTEXT_SURFACES_2D;
 387         else
 388                 class = NV10_CONTEXT_SURFACES_2D;
 389
 390         ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->surf2d);
 391         if (ret) {
 392                 nv04_surface_2d_takedown(&ctx);
 393                 return NULL;
 394         }
 395
 396         BEGIN_RING(chan, ctx->surf2d,
 397                          NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
 398         OUT_RING  (chan, chan->vram->handle);
 399         OUT_RING  (chan, chan->vram->handle);
 400
 401         if (chan->device->chipset < 0x10)
 402                 class = NV04_IMAGE_BLIT;
 403         else
 404                 class = NV12_IMAGE_BLIT;
 405
 406         ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->blit);
 407         if (ret) {
 408                 nv04_surface_2d_takedown(&ctx);
 409                 return NULL;
 410         }
 411
 412         BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_DMA_NOTIFY, 1);
 413         OUT_RING  (chan, ctx->ntfy->handle);
 414         BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_SURFACE, 1);
 415         OUT_RING  (chan, ctx->surf2d->handle);
 416         BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_OPERATION, 1);
 417         OUT_RING  (chan, NV04_IMAGE_BLIT_OPERATION_SRCCOPY);
 418
 419         ret = nouveau_grobj_alloc(chan, handle++, NV04_GDI_RECTANGLE_TEXT,
 420                                   &ctx->rect);
 421         if (ret) {
 422                 nv04_surface_2d_takedown(&ctx);
 423                 return NULL;
 424         }
 425
 426         BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_DMA_NOTIFY, 1);
 427         OUT_RING  (chan, ctx->ntfy->handle);
 428         BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_SURFACE, 1);
 429         OUT_RING  (chan, ctx->surf2d->handle);
 430         BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_OPERATION, 1);
 431         OUT_RING  (chan, NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY);
 432         BEGIN_RING(chan, ctx->rect,
 433                          NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT, 1);
 434         OUT_RING  (chan, NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_LE);
 435
 436         switch (chan->device->chipset & 0xf0) {
 437         case 0x00:
 438         case 0x10:
 439                 class = NV04_SWIZZLED_SURFACE;
 440                 break;
 441         case 0x20:
 442                 class = NV20_SWIZZLED_SURFACE;
 443                 break;
 444         case 0x30:
 445                 class = NV30_SWIZZLED_SURFACE;
 446                 break;
 447         case 0x40:
 448         case 0x60:
 449                 class = NV40_SWIZZLED_SURFACE;
 450                 break;
 451         default:
 452                 /* Famous last words: this really can't happen.. */
 453                 assert(0);
 454                 break;
 455         }
 456
 457         ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->swzsurf);
 458         if (ret) {
 459                 nv04_surface_2d_takedown(&ctx);
 460                 return NULL;
 461         }
 462
 463         switch (chan->device->chipset & 0xf0) {
 464         case 0x10:
 465         case 0x20:
 466                 class = NV10_SCALED_IMAGE_FROM_MEMORY;
 467                 break;
 468         case 0x30:
 469                 class = NV30_SCALED_IMAGE_FROM_MEMORY;
 470                 break;
 471         case 0x40:
 472         case 0x60:
 473                 class = NV40_SCALED_IMAGE_FROM_MEMORY;
 474                 break;
 475         default:
 476                 class = NV04_SCALED_IMAGE_FROM_MEMORY;
 477                 break;
 478         }
 479
 480         ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->sifm);
 481         if (ret) {
 482                 nv04_surface_2d_takedown(&ctx);
 483                 return NULL;
 484         }
 485
 486         ctx->copy = nv04_surface_copy;
 487         ctx->fill = nv04_surface_fill;
 488         return ctx;
 489 }