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Merge branch 'mesa_7_5_branch'
[mesa.git] / src / gallium / drivers / nv04 / nv04_surface_2d.c
1 #include "pipe/p_context.h"
2 #include "pipe/p_format.h"
3 #include "util/u_memory.h"
4
5 #include "nouveau/nouveau_winsys.h"
6 #include "nouveau/nouveau_util.h"
7 #include "nouveau/nouveau_screen.h"
8 #include "nv04_surface_2d.h"
9
10 static INLINE int
11 nv04_surface_format(enum pipe_format format)
12 {
13 switch (format) {
14 case PIPE_FORMAT_A8_UNORM:
15 return NV04_CONTEXT_SURFACES_2D_FORMAT_Y8;
16 case PIPE_FORMAT_R16_SNORM:
17 case PIPE_FORMAT_R5G6B5_UNORM:
18 return NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5;
19 case PIPE_FORMAT_X8R8G8B8_UNORM:
20 case PIPE_FORMAT_A8R8G8B8_UNORM:
21 return NV04_CONTEXT_SURFACES_2D_FORMAT_A8R8G8B8;
22 case PIPE_FORMAT_Z24S8_UNORM:
23 return NV04_CONTEXT_SURFACES_2D_FORMAT_Y32;
24 default:
25 return -1;
26 }
27 }
28
29 static INLINE int
30 nv04_rect_format(enum pipe_format format)
31 {
32 switch (format) {
33 case PIPE_FORMAT_A8_UNORM:
34 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
35 case PIPE_FORMAT_R5G6B5_UNORM:
36 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A16R5G6B5;
37 case PIPE_FORMAT_A8R8G8B8_UNORM:
38 case PIPE_FORMAT_Z24S8_UNORM:
39 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
40 default:
41 return -1;
42 }
43 }
44
45 static INLINE int
46 nv04_scaled_image_format(enum pipe_format format)
47 {
48 switch (format) {
49 case PIPE_FORMAT_A1R5G5B5_UNORM:
50 return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A1R5G5B5;
51 case PIPE_FORMAT_A8R8G8B8_UNORM:
52 return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8;
53 case PIPE_FORMAT_X8R8G8B8_UNORM:
54 return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8;
55 case PIPE_FORMAT_R5G6B5_UNORM:
56 case PIPE_FORMAT_R16_SNORM:
57 return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5;
58 default:
59 return -1;
60 }
61 }
62
63 static INLINE unsigned
64 nv04_swizzle_bits(unsigned x, unsigned y)
65 {
66 unsigned u = (x & 0x001) << 0 |
67 (x & 0x002) << 1 |
68 (x & 0x004) << 2 |
69 (x & 0x008) << 3 |
70 (x & 0x010) << 4 |
71 (x & 0x020) << 5 |
72 (x & 0x040) << 6 |
73 (x & 0x080) << 7 |
74 (x & 0x100) << 8 |
75 (x & 0x200) << 9 |
76 (x & 0x400) << 10 |
77 (x & 0x800) << 11;
78
79 unsigned v = (y & 0x001) << 1 |
80 (y & 0x002) << 2 |
81 (y & 0x004) << 3 |
82 (y & 0x008) << 4 |
83 (y & 0x010) << 5 |
84 (y & 0x020) << 6 |
85 (y & 0x040) << 7 |
86 (y & 0x080) << 8 |
87 (y & 0x100) << 9 |
88 (y & 0x200) << 10 |
89 (y & 0x400) << 11 |
90 (y & 0x800) << 12;
91 return v | u;
92 }
93
94 static int
95 nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx,
96 struct pipe_surface *dst, int dx, int dy,
97 struct pipe_surface *src, int sx, int sy,
98 int w, int h)
99 {
100 struct nouveau_channel *chan = ctx->swzsurf->channel;
101 struct nouveau_grobj *swzsurf = ctx->swzsurf;
102 struct nouveau_grobj *sifm = ctx->sifm;
103 struct nouveau_bo *src_bo = nouveau_bo(ctx->buf(src));
104 struct nouveau_bo *dst_bo = nouveau_bo(ctx->buf(dst));
105 const unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
106 const unsigned max_w = 1024;
107 const unsigned max_h = 1024;
108 const unsigned sub_w = w > max_w ? max_w : w;
109 const unsigned sub_h = h > max_h ? max_h : h;
110 unsigned cx;
111 unsigned cy;
112
113 #if 0
114 /* That's the way she likes it */
115 assert(src_pitch == ((struct nv04_surface *)dst)->pitch);
116 #endif
117
118 BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_DMA_IMAGE, 1);
119 OUT_RELOCo(chan, dst_bo,
120 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
121
122 BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_FORMAT, 1);
123 OUT_RING (chan, nv04_surface_format(dst->format) |
124 log2i(w) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_SHIFT |
125 log2i(h) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_SHIFT);
126
127 BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE, 1);
128 OUT_RELOCo(chan, src_bo,
129 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
130 BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE, 1);
131 OUT_RING (chan, swzsurf->handle);
132
133 for (cy = 0; cy < h; cy += sub_h) {
134 for (cx = 0; cx < w; cx += sub_w) {
135 BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_OFFSET, 1);
136 OUT_RELOCl(chan, dst_bo, dst->offset + nv04_swizzle_bits(cx+dx, cy+dy) *
137 dst->texture->block.size, NOUVEAU_BO_GART |
138 NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
139
140 BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION, 9);
141 OUT_RING (chan, NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE);
142 OUT_RING (chan, nv04_scaled_image_format(src->format));
143 OUT_RING (chan, NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY);
144 OUT_RING (chan, 0);
145 OUT_RING (chan, sub_h << 16 | sub_w);
146 OUT_RING (chan, 0);
147 OUT_RING (chan, sub_h << 16 | sub_w);
148 OUT_RING (chan, 1 << 20);
149 OUT_RING (chan, 1 << 20);
150
151 BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_SIZE, 4);
152 OUT_RING (chan, sub_h << 16 | sub_w);
153 OUT_RING (chan, src_pitch |
154 NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER |
155 NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE);
156 OUT_RELOCl(chan, src_bo, src->offset + (cy+sy) * src_pitch +
157 (cx+sx) * src->texture->block.size, NOUVEAU_BO_GART |
158 NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
159 OUT_RING (chan, 0);
160 }
161 }
162
163 return 0;
164 }
165
166 static int
167 nv04_surface_copy_m2mf(struct nv04_surface_2d *ctx,
168 struct pipe_surface *dst, int dx, int dy,
169 struct pipe_surface *src, int sx, int sy, int w, int h)
170 {
171 struct nouveau_channel *chan = ctx->m2mf->channel;
172 struct nouveau_grobj *m2mf = ctx->m2mf;
173 struct nouveau_bo *src_bo = nouveau_bo(ctx->buf(src));
174 struct nouveau_bo *dst_bo = nouveau_bo(ctx->buf(dst));
175 unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
176 unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
177 unsigned dst_offset = dst->offset + dy * dst_pitch +
178 dx * dst->texture->block.size;
179 unsigned src_offset = src->offset + sy * src_pitch +
180 sx * src->texture->block.size;
181
182 WAIT_RING (chan, 3 + ((h / 2047) + 1) * 9);
183 BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_IN, 2);
184 OUT_RELOCo(chan, src_bo,
185 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
186 OUT_RELOCo(chan, dst_bo,
187 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
188
189 while (h) {
190 int count = (h > 2047) ? 2047 : h;
191
192 BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
193 OUT_RELOCl(chan, src_bo, src_offset,
194 NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD);
195 OUT_RELOCl(chan, dst_bo, dst_offset,
196 NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_WR);
197 OUT_RING (chan, src_pitch);
198 OUT_RING (chan, dst_pitch);
199 OUT_RING (chan, w * src->texture->block.size);
200 OUT_RING (chan, count);
201 OUT_RING (chan, 0x0101);
202 OUT_RING (chan, 0);
203
204 h -= count;
205 src_offset += src_pitch * count;
206 dst_offset += dst_pitch * count;
207 }
208
209 return 0;
210 }
211
212 static int
213 nv04_surface_copy_m2mf_swizzle(struct nv04_surface_2d *ctx,
214 struct pipe_surface *dst, int dx, int dy,
215 struct pipe_surface *src, int sx, int sy)
216 {
217 struct nouveau_channel *chan = ctx->m2mf->channel;
218 struct nouveau_grobj *m2mf = ctx->m2mf;
219 struct nouveau_bo *src_bo = nouveau_bo(ctx->buf(src));
220 struct nouveau_bo *dst_bo = nouveau_bo(ctx->buf(dst));
221 unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
222 unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
223 unsigned dst_offset = dst->offset + nv04_swizzle_bits(dx, dy) *
224 dst->texture->block.size;
225 unsigned src_offset = src->offset + sy * src_pitch +
226 sx * src->texture->block.size;
227
228 BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_IN, 2);
229 OUT_RELOCo(chan, src_bo,
230 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
231 OUT_RELOCo(chan, dst_bo,
232 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
233
234 BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
235 OUT_RELOCl(chan, src_bo, src_offset,
236 NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD);
237 OUT_RELOCl(chan, dst_bo, dst_offset,
238 NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_WR);
239 OUT_RING (chan, src_pitch);
240 OUT_RING (chan, dst_pitch);
241 OUT_RING (chan, 1 * src->texture->block.size);
242 OUT_RING (chan, 1);
243 OUT_RING (chan, 0x0101);
244 OUT_RING (chan, 0);
245
246 return 0;
247 }
248
249 static int
250 nv04_surface_copy_blit(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
251 int dx, int dy, struct pipe_surface *src, int sx, int sy,
252 int w, int h)
253 {
254 struct nouveau_channel *chan = ctx->surf2d->channel;
255 struct nouveau_grobj *surf2d = ctx->surf2d;
256 struct nouveau_grobj *blit = ctx->blit;
257 struct nouveau_bo *src_bo = nouveau_bo(ctx->buf(src));
258 struct nouveau_bo *dst_bo = nouveau_bo(ctx->buf(dst));
259 unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
260 unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
261 int format;
262
263 format = nv04_surface_format(dst->format);
264 if (format < 0)
265 return 1;
266
267 WAIT_RING (chan, 12);
268 BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
269 OUT_RELOCo(chan, src_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
270 OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
271 BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
272 OUT_RING (chan, format);
273 OUT_RING (chan, (dst_pitch << 16) | src_pitch);
274 OUT_RELOCl(chan, src_bo, src->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
275 OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
276
277 BEGIN_RING(chan, blit, 0x0300, 3);
278 OUT_RING (chan, (sy << 16) | sx);
279 OUT_RING (chan, (dy << 16) | dx);
280 OUT_RING (chan, ( h << 16) | w);
281
282 return 0;
283 }
284
285 static void
286 nv04_surface_copy(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
287 int dx, int dy, struct pipe_surface *src, int sx, int sy,
288 int w, int h)
289 {
290 unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
291 unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
292 int src_linear = src->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR;
293 int dst_linear = dst->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR;
294
295 assert(src->format == dst->format);
296
297 /* Setup transfer to swizzle the texture to vram if needed */
298 if (src_linear && !dst_linear) {
299 int x,y;
300
301 if ((w>1) && (h>1)) {
302 int potWidth = 1<<log2i(w);
303 int potHeight = 1<<log2i(h);
304 int remainWidth = w-potWidth;
305 int remainHeight = h-potHeight;
306 int squareDim = (potWidth>potHeight ? potHeight : potWidth);
307
308 /* top left is always POT, but we can only swizzle squares */
309 for (y=0; y<potHeight; y+=squareDim) {
310 for (x=0; x<potWidth; x+= squareDim) {
311 nv04_surface_copy_swizzle(ctx, dst, dx+x, dy+y,
312 src, sx+x, sy+y,
313 squareDim, squareDim);
314 }
315 }
316
317 /* top right */
318 if (remainWidth>0) {
319 nv04_surface_copy(ctx, dst, dx+potWidth, dy,
320 src, sx+potWidth, sy,
321 remainWidth, potHeight);
322 }
323
324 /* bottom left */
325 if (remainHeight>0) {
326 nv04_surface_copy(ctx, dst, dx, dy+potHeight,
327 src, sx, sy+potHeight,
328 potWidth, remainHeight);
329 }
330
331 /* bottom right */
332 if ((remainWidth>0) && (remainHeight>0)) {
333 nv04_surface_copy(ctx, dst, dx+potWidth, dy+potHeight,
334 src, sx+potWidth, sy+potHeight,
335 remainWidth, remainHeight);
336 }
337 } else if (w==1) {
338 /* We have a column to copy to a swizzled texture */
339 for (y=0; y<h; y++) {
340 nv04_surface_copy_m2mf_swizzle(ctx, dst, dx, dy+y,
341 src, sx, sy+y);
342 }
343 } else if (h==1) {
344 /* We have a row to copy to a swizzled texture */
345 for (x=0; x<w; x++) {
346 nv04_surface_copy_m2mf_swizzle(ctx, dst, dx+x, dy,
347 src, sx+x, sy);
348 }
349 }
350
351 return;
352 }
353
354 /* NV_CONTEXT_SURFACES_2D has buffer alignment restrictions, fallback
355 * to NV_MEMORY_TO_MEMORY_FORMAT in this case.
356 */
357 if ((src->offset & 63) || (dst->offset & 63) ||
358 (src_pitch & 63) || (dst_pitch & 63)) {
359 nv04_surface_copy_m2mf(ctx, dst, dx, dy, src, sx, sy, w, h);
360 return;
361 }
362
363 nv04_surface_copy_blit(ctx, dst, dx, dy, src, sx, sy, w, h);
364 }
365
366 static void
367 nv04_surface_fill(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
368 int dx, int dy, int w, int h, unsigned value)
369 {
370 struct nouveau_channel *chan = ctx->surf2d->channel;
371 struct nouveau_grobj *surf2d = ctx->surf2d;
372 struct nouveau_grobj *rect = ctx->rect;
373 struct nouveau_bo *dst_bo = nouveau_bo(ctx->buf(dst));
374 unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
375 int cs2d_format, gdirect_format;
376
377 cs2d_format = nv04_surface_format(dst->format);
378 assert(cs2d_format >= 0);
379
380 gdirect_format = nv04_rect_format(dst->format);
381 assert(gdirect_format >= 0);
382
383 WAIT_RING (chan, 16);
384 BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
385 OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
386 OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
387 BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
388 OUT_RING (chan, cs2d_format);
389 OUT_RING (chan, (dst_pitch << 16) | dst_pitch);
390 OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
391 OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
392
393 BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT, 1);
394 OUT_RING (chan, gdirect_format);
395 BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_COLOR1_A, 1);
396 OUT_RING (chan, value);
397 BEGIN_RING(chan, rect,
398 NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT(0), 2);
399 OUT_RING (chan, (dx << 16) | dy);
400 OUT_RING (chan, ( w << 16) | h);
401 }
402
403 void
404 nv04_surface_2d_takedown(struct nv04_surface_2d **pctx)
405 {
406 struct nv04_surface_2d *ctx;
407
408 if (!pctx || !*pctx)
409 return;
410 ctx = *pctx;
411 *pctx = NULL;
412
413 nouveau_notifier_free(&ctx->ntfy);
414 nouveau_grobj_free(&ctx->m2mf);
415 nouveau_grobj_free(&ctx->surf2d);
416 nouveau_grobj_free(&ctx->swzsurf);
417 nouveau_grobj_free(&ctx->rect);
418 nouveau_grobj_free(&ctx->blit);
419 nouveau_grobj_free(&ctx->sifm);
420
421 FREE(ctx);
422 }
423
424 struct nv04_surface_2d *
425 nv04_surface_2d_init(struct nouveau_screen *screen)
426 {
427 struct nv04_surface_2d *ctx = CALLOC_STRUCT(nv04_surface_2d);
428 struct nouveau_channel *chan = screen->channel;
429 unsigned handle = 0x88000000, class;
430 int ret;
431
432 if (!ctx)
433 return NULL;
434
435 ret = nouveau_notifier_alloc(chan, handle++, 1, &ctx->ntfy);
436 if (ret) {
437 nv04_surface_2d_takedown(&ctx);
438 return NULL;
439 }
440
441 ret = nouveau_grobj_alloc(chan, handle++, 0x0039, &ctx->m2mf);
442 if (ret) {
443 nv04_surface_2d_takedown(&ctx);
444 return NULL;
445 }
446
447 BEGIN_RING(chan, ctx->m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
448 OUT_RING (chan, ctx->ntfy->handle);
449
450 if (chan->device->chipset < 0x10)
451 class = NV04_CONTEXT_SURFACES_2D;
452 else
453 class = NV10_CONTEXT_SURFACES_2D;
454
455 ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->surf2d);
456 if (ret) {
457 nv04_surface_2d_takedown(&ctx);
458 return NULL;
459 }
460
461 BEGIN_RING(chan, ctx->surf2d,
462 NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
463 OUT_RING (chan, chan->vram->handle);
464 OUT_RING (chan, chan->vram->handle);
465
466 if (chan->device->chipset < 0x10)
467 class = NV04_IMAGE_BLIT;
468 else
469 class = NV12_IMAGE_BLIT;
470
471 ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->blit);
472 if (ret) {
473 nv04_surface_2d_takedown(&ctx);
474 return NULL;
475 }
476
477 BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_DMA_NOTIFY, 1);
478 OUT_RING (chan, ctx->ntfy->handle);
479 BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_SURFACE, 1);
480 OUT_RING (chan, ctx->surf2d->handle);
481 BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_OPERATION, 1);
482 OUT_RING (chan, NV04_IMAGE_BLIT_OPERATION_SRCCOPY);
483
484 ret = nouveau_grobj_alloc(chan, handle++, NV04_GDI_RECTANGLE_TEXT,
485 &ctx->rect);
486 if (ret) {
487 nv04_surface_2d_takedown(&ctx);
488 return NULL;
489 }
490
491 BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_DMA_NOTIFY, 1);
492 OUT_RING (chan, ctx->ntfy->handle);
493 BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_SURFACE, 1);
494 OUT_RING (chan, ctx->surf2d->handle);
495 BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_OPERATION, 1);
496 OUT_RING (chan, NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY);
497 BEGIN_RING(chan, ctx->rect,
498 NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT, 1);
499 OUT_RING (chan, NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_LE);
500
501 switch (chan->device->chipset & 0xf0) {
502 case 0x00:
503 case 0x10:
504 class = NV04_SWIZZLED_SURFACE;
505 break;
506 case 0x20:
507 class = NV20_SWIZZLED_SURFACE;
508 break;
509 case 0x30:
510 class = NV30_SWIZZLED_SURFACE;
511 break;
512 case 0x40:
513 case 0x60:
514 class = NV40_SWIZZLED_SURFACE;
515 break;
516 default:
517 /* Famous last words: this really can't happen.. */
518 assert(0);
519 break;
520 }
521
522 ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->swzsurf);
523 if (ret) {
524 nv04_surface_2d_takedown(&ctx);
525 return NULL;
526 }
527
528 switch (chan->device->chipset & 0xf0) {
529 case 0x10:
530 case 0x20:
531 class = NV10_SCALED_IMAGE_FROM_MEMORY;
532 break;
533 case 0x30:
534 class = NV30_SCALED_IMAGE_FROM_MEMORY;
535 break;
536 case 0x40:
537 case 0x60:
538 class = NV40_SCALED_IMAGE_FROM_MEMORY;
539 break;
540 default:
541 class = NV04_SCALED_IMAGE_FROM_MEMORY;
542 break;
543 }
544
545 ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->sifm);
546 if (ret) {
547 nv04_surface_2d_takedown(&ctx);
548 return NULL;
549 }
550
551 ctx->copy = nv04_surface_copy;
552 ctx->fill = nv04_surface_fill;
553 return ctx;
554 }