src/gallium/drivers/nv04/nv04_surface_2d.c

   1 #include "pipe/p_context.h"
   2 #include "pipe/p_format.h"
   3 #include "util/u_math.h"
   4 #include "util/u_memory.h"
   5
   6 #include "nouveau/nouveau_winsys.h"
   7 #include "nouveau/nouveau_util.h"
   8 #include "nouveau/nouveau_screen.h"
   9 #include "nv04_surface_2d.h"
  10
  11 static INLINE int
  12 nv04_surface_format(enum pipe_format format)
  13 {
  14         switch (format) {
  15         case PIPE_FORMAT_A8_UNORM:
  16         case PIPE_FORMAT_L8_UNORM:
  17         case PIPE_FORMAT_I8_UNORM:
  18                 return NV04_CONTEXT_SURFACES_2D_FORMAT_Y8;
  19         case PIPE_FORMAT_R16_SNORM:
  20         case PIPE_FORMAT_R5G6B5_UNORM:
  21         case PIPE_FORMAT_Z16_UNORM:
  22         case PIPE_FORMAT_A8L8_UNORM:
  23                 return NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5;
  24         case PIPE_FORMAT_X8R8G8B8_UNORM:
  25         case PIPE_FORMAT_A8R8G8B8_UNORM:
  26                 return NV04_CONTEXT_SURFACES_2D_FORMAT_A8R8G8B8;
  27         case PIPE_FORMAT_Z24S8_UNORM:
  28         case PIPE_FORMAT_Z24X8_UNORM:
  29                 return NV04_CONTEXT_SURFACES_2D_FORMAT_Y32;
  30         default:
  31                 return -1;
  32         }
  33 }
  34
  35 static INLINE int
  36 nv04_rect_format(enum pipe_format format)
  37 {
  38         switch (format) {
  39         case PIPE_FORMAT_A8_UNORM:
  40                 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
  41         case PIPE_FORMAT_R5G6B5_UNORM:
  42         case PIPE_FORMAT_A8L8_UNORM:
  43         case PIPE_FORMAT_Z16_UNORM:
  44                 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A16R5G6B5;
  45         case PIPE_FORMAT_A8R8G8B8_UNORM:
  46         case PIPE_FORMAT_Z24S8_UNORM:
  47         case PIPE_FORMAT_Z24X8_UNORM:
  48                 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
  49         default:
  50                 return -1;
  51         }
  52 }
  53
  54 static INLINE int
  55 nv04_scaled_image_format(enum pipe_format format)
  56 {
  57         switch (format) {
  58         case PIPE_FORMAT_A8_UNORM:
  59         case PIPE_FORMAT_L8_UNORM:
  60         case PIPE_FORMAT_I8_UNORM:
  61                 return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_Y8;
  62         case PIPE_FORMAT_A1R5G5B5_UNORM:
  63                 return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A1R5G5B5;
  64         case PIPE_FORMAT_A8R8G8B8_UNORM:
  65                 return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8;
  66         case PIPE_FORMAT_X8R8G8B8_UNORM:
  67                 return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8;
  68         case PIPE_FORMAT_R5G6B5_UNORM:
  69         case PIPE_FORMAT_R16_SNORM:
  70         case PIPE_FORMAT_A8L8_UNORM:
  71                 return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5;
  72         default:
  73                 return -1;
  74         }
  75 }
  76
  77 static INLINE unsigned
  78 nv04_swizzle_bits(unsigned x, unsigned y)
  79 {
  80         unsigned u = (x & 0x001) << 0 |
  81                      (x & 0x002) << 1 |
  82                      (x & 0x004) << 2 |
  83                      (x & 0x008) << 3 |
  84                      (x & 0x010) << 4 |
  85                      (x & 0x020) << 5 |
  86                      (x & 0x040) << 6 |
  87                      (x & 0x080) << 7 |
  88                      (x & 0x100) << 8 |
  89                      (x & 0x200) << 9 |
  90                      (x & 0x400) << 10 |
  91                      (x & 0x800) << 11;
  92
  93         unsigned v = (y & 0x001) << 1 |
  94                      (y & 0x002) << 2 |
  95                      (y & 0x004) << 3 |
  96                      (y & 0x008) << 4 |
  97                      (y & 0x010) << 5 |
  98                      (y & 0x020) << 6 |
  99                      (y & 0x040) << 7 |
 100                      (y & 0x080) << 8 |
 101                      (y & 0x100) << 9 |
 102                      (y & 0x200) << 10 |
 103                      (y & 0x400) << 11 |
 104                      (y & 0x800) << 12;
 105         return v | u;
 106 }
 107
 108 static int
 109 nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx,
 110                           struct pipe_surface *dst, int dx, int dy,
 111                           struct pipe_surface *src, int sx, int sy,
 112                           int w, int h)
 113 {
 114         struct nouveau_channel *chan = ctx->swzsurf->channel;
 115         struct nouveau_grobj *swzsurf = ctx->swzsurf;
 116         struct nouveau_grobj *sifm = ctx->sifm;
 117         struct nouveau_bo *src_bo = nouveau_bo(ctx->buf(src));
 118         struct nouveau_bo *dst_bo = nouveau_bo(ctx->buf(dst));
 119         const unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
 120         /* Max width & height may not be the same on all HW, but must be POT */
 121         const unsigned max_w = 1024;
 122         const unsigned max_h = 1024;
 123         unsigned sub_w = w > max_w ? max_w : w;
 124         unsigned sub_h = h > max_h ? max_h : h;
 125         unsigned x;
 126         unsigned y;
 127
 128         /* Swizzled surfaces must be POT  */
 129         assert(util_is_pot(dst->width) && util_is_pot(dst->height));
 130
 131         /* If area is too large to copy in one shot we must copy it in POT chunks to meet alignment requirements */
 132         assert(sub_w == w || util_is_pot(sub_w));
 133         assert(sub_h == h || util_is_pot(sub_h));
 134
 135         BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_DMA_IMAGE, 1);
 136         OUT_RELOCo(chan, dst_bo,
 137                          NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 138
 139         BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_FORMAT, 1);
 140         OUT_RING  (chan, nv04_surface_format(dst->format) |
 141                          log2i(dst->width) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_SHIFT |
 142                          log2i(dst->height) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_SHIFT);
 143
 144         BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE, 1);
 145         OUT_RELOCo(chan, src_bo,
 146                          NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 147         BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE, 1);
 148         OUT_RING  (chan, swzsurf->handle);
 149
 150         for (y = 0; y < h; y += sub_h) {
 151           sub_h = MIN2(sub_h, h - y);
 152
 153           for (x = 0; x < w; x += sub_w) {
 154             sub_w = MIN2(sub_w, w - x);
 155
 156             /* Must be 64-byte aligned */
 157             assert(!((dst->offset + nv04_swizzle_bits(dx+x, dy+y) * dst->texture->block.size) & 63));
 158
 159             BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_OFFSET, 1);
 160             OUT_RELOCl(chan, dst_bo, dst->offset + nv04_swizzle_bits(dx+x, dy+y) * dst->texture->block.size,
 161                              NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 162
 163             BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION, 9);
 164             OUT_RING  (chan, NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE);
 165             OUT_RING  (chan, nv04_scaled_image_format(src->format));
 166             OUT_RING  (chan, NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY);
 167             OUT_RING  (chan, 0);
 168             OUT_RING  (chan, sub_h << NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H_SHIFT | sub_w);
 169             OUT_RING  (chan, 0);
 170             OUT_RING  (chan, sub_h << NV04_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H_SHIFT | sub_w);
 171             OUT_RING  (chan, 1 << 20);
 172             OUT_RING  (chan, 1 << 20);
 173
 174             BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_SIZE, 4);
 175             OUT_RING  (chan, sub_h << NV04_SCALED_IMAGE_FROM_MEMORY_SIZE_H_SHIFT | sub_w);
 176             OUT_RING  (chan, src_pitch |
 177                              NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER |
 178                              NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE);
 179             OUT_RELOCl(chan, src_bo, src->offset + (sy+y) * src_pitch + (sx+x) * src->texture->block.size,
 180                              NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 181             OUT_RING  (chan, 0);
 182           }
 183         }
 184
 185         return 0;
 186 }
 187
 188 static int
 189 nv04_surface_copy_m2mf(struct nv04_surface_2d *ctx,
 190                        struct pipe_surface *dst, int dx, int dy,
 191                        struct pipe_surface *src, int sx, int sy, int w, int h)
 192 {
 193         struct nouveau_channel *chan = ctx->m2mf->channel;
 194         struct nouveau_grobj *m2mf = ctx->m2mf;
 195         struct nouveau_bo *src_bo = nouveau_bo(ctx->buf(src));
 196         struct nouveau_bo *dst_bo = nouveau_bo(ctx->buf(dst));
 197         unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
 198         unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
 199         unsigned dst_offset = dst->offset + dy * dst_pitch +
 200                               dx * dst->texture->block.size;
 201         unsigned src_offset = src->offset + sy * src_pitch +
 202                               sx * src->texture->block.size;
 203
 204         WAIT_RING (chan, 3 + ((h / 2047) + 1) * 9);
 205         BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_IN, 2);
 206         OUT_RELOCo(chan, src_bo,
 207                    NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 208         OUT_RELOCo(chan, dst_bo,
 209                    NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 210
 211         while (h) {
 212                 int count = (h > 2047) ? 2047 : h;
 213
 214                 BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
 215                 OUT_RELOCl(chan, src_bo, src_offset,
 216                            NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD);
 217                 OUT_RELOCl(chan, dst_bo, dst_offset,
 218                            NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_WR);
 219                 OUT_RING  (chan, src_pitch);
 220                 OUT_RING  (chan, dst_pitch);
 221                 OUT_RING  (chan, w * src->texture->block.size);
 222                 OUT_RING  (chan, count);
 223                 OUT_RING  (chan, 0x0101);
 224                 OUT_RING  (chan, 0);
 225
 226                 h -= count;
 227                 src_offset += src_pitch * count;
 228                 dst_offset += dst_pitch * count;
 229         }
 230
 231         return 0;
 232 }
 233
 234 static int
 235 nv04_surface_copy_blit(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
 236                        int dx, int dy, struct pipe_surface *src, int sx, int sy,
 237                        int w, int h)
 238 {
 239         struct nouveau_channel *chan = ctx->surf2d->channel;
 240         struct nouveau_grobj *surf2d = ctx->surf2d;
 241         struct nouveau_grobj *blit = ctx->blit;
 242         struct nouveau_bo *src_bo = nouveau_bo(ctx->buf(src));
 243         struct nouveau_bo *dst_bo = nouveau_bo(ctx->buf(dst));
 244         unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
 245         unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
 246         int format;
 247
 248         format = nv04_surface_format(dst->format);
 249         if (format < 0)
 250                 return 1;
 251
 252         WAIT_RING (chan, 12);
 253         BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
 254         OUT_RELOCo(chan, src_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 255         OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 256         BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
 257         OUT_RING  (chan, format);
 258         OUT_RING  (chan, (dst_pitch << 16) | src_pitch);
 259         OUT_RELOCl(chan, src_bo, src->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 260         OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 261
 262         BEGIN_RING(chan, blit, 0x0300, 3);
 263         OUT_RING  (chan, (sy << 16) | sx);
 264         OUT_RING  (chan, (dy << 16) | dx);
 265         OUT_RING  (chan, ( h << 16) |  w);
 266
 267         return 0;
 268 }
 269
 270 static void
 271 nv04_surface_copy(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
 272                   int dx, int dy, struct pipe_surface *src, int sx, int sy,
 273                   int w, int h)
 274 {
 275         unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
 276         unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
 277         int src_linear = src->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR;
 278         int dst_linear = dst->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR;
 279
 280         assert(src->format == dst->format);
 281
 282         /* Setup transfer to swizzle the texture to vram if needed */
 283         if (src_linear && !dst_linear && w > 1 && h > 1) {
 284            nv04_surface_copy_swizzle(ctx, dst, dx, dy, src, sx, sy, w, h);
 285            return;
 286         }
 287
 288         /* NV_CONTEXT_SURFACES_2D has buffer alignment restrictions, fallback
 289          * to NV_MEMORY_TO_MEMORY_FORMAT in this case.
 290          */
 291         if ((src->offset & 63) || (dst->offset & 63) ||
 292             (src_pitch & 63) || (dst_pitch & 63)) {
 293                 nv04_surface_copy_m2mf(ctx, dst, dx, dy, src, sx, sy, w, h);
 294                 return;
 295         }
 296
 297         nv04_surface_copy_blit(ctx, dst, dx, dy, src, sx, sy, w, h);
 298 }
 299
 300 static void
 301 nv04_surface_fill(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
 302                   int dx, int dy, int w, int h, unsigned value)
 303 {
 304         struct nouveau_channel *chan = ctx->surf2d->channel;
 305         struct nouveau_grobj *surf2d = ctx->surf2d;
 306         struct nouveau_grobj *rect = ctx->rect;
 307         struct nouveau_bo *dst_bo = nouveau_bo(ctx->buf(dst));
 308         unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
 309         int cs2d_format, gdirect_format;
 310
 311         cs2d_format = nv04_surface_format(dst->format);
 312         assert(cs2d_format >= 0);
 313
 314         gdirect_format = nv04_rect_format(dst->format);
 315         assert(gdirect_format >= 0);
 316
 317         WAIT_RING (chan, 16);
 318         BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
 319         OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 320         OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 321         BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
 322         OUT_RING  (chan, cs2d_format);
 323         OUT_RING  (chan, (dst_pitch << 16) | dst_pitch);
 324         OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 325         OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 326
 327         BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT, 1);
 328         OUT_RING  (chan, gdirect_format);
 329         BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_COLOR1_A, 1);
 330         OUT_RING  (chan, value);
 331         BEGIN_RING(chan, rect,
 332                    NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT(0), 2);
 333         OUT_RING  (chan, (dx << 16) | dy);
 334         OUT_RING  (chan, ( w << 16) |  h);
 335 }
 336
 337 void
 338 nv04_surface_2d_takedown(struct nv04_surface_2d **pctx)
 339 {
 340         struct nv04_surface_2d *ctx;
 341
 342         if (!pctx || !*pctx)
 343                 return;
 344         ctx = *pctx;
 345         *pctx = NULL;
 346
 347         nouveau_notifier_free(&ctx->ntfy);
 348         nouveau_grobj_free(&ctx->m2mf);
 349         nouveau_grobj_free(&ctx->surf2d);
 350         nouveau_grobj_free(&ctx->swzsurf);
 351         nouveau_grobj_free(&ctx->rect);
 352         nouveau_grobj_free(&ctx->blit);
 353         nouveau_grobj_free(&ctx->sifm);
 354
 355         FREE(ctx);
 356 }
 357
 358 struct nv04_surface_2d *
 359 nv04_surface_2d_init(struct nouveau_screen *screen)
 360 {
 361         struct nv04_surface_2d *ctx = CALLOC_STRUCT(nv04_surface_2d);
 362         struct nouveau_channel *chan = screen->channel;
 363         unsigned handle = 0x88000000, class;
 364         int ret;
 365
 366         if (!ctx)
 367                 return NULL;
 368
 369         ret = nouveau_notifier_alloc(chan, handle++, 1, &ctx->ntfy);
 370         if (ret) {
 371                 nv04_surface_2d_takedown(&ctx);
 372                 return NULL;
 373         }
 374
 375         ret = nouveau_grobj_alloc(chan, handle++, 0x0039, &ctx->m2mf);
 376         if (ret) {
 377                 nv04_surface_2d_takedown(&ctx);
 378                 return NULL;
 379         }
 380
 381         BEGIN_RING(chan, ctx->m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
 382         OUT_RING  (chan, ctx->ntfy->handle);
 383
 384         if (chan->device->chipset < 0x10)
 385                 class = NV04_CONTEXT_SURFACES_2D;
 386         else
 387                 class = NV10_CONTEXT_SURFACES_2D;
 388
 389         ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->surf2d);
 390         if (ret) {
 391                 nv04_surface_2d_takedown(&ctx);
 392                 return NULL;
 393         }
 394
 395         BEGIN_RING(chan, ctx->surf2d,
 396                          NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
 397         OUT_RING  (chan, chan->vram->handle);
 398         OUT_RING  (chan, chan->vram->handle);
 399
 400         if (chan->device->chipset < 0x10)
 401                 class = NV04_IMAGE_BLIT;
 402         else
 403                 class = NV12_IMAGE_BLIT;
 404
 405         ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->blit);
 406         if (ret) {
 407                 nv04_surface_2d_takedown(&ctx);
 408                 return NULL;
 409         }
 410
 411         BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_DMA_NOTIFY, 1);
 412         OUT_RING  (chan, ctx->ntfy->handle);
 413         BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_SURFACE, 1);
 414         OUT_RING  (chan, ctx->surf2d->handle);
 415         BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_OPERATION, 1);
 416         OUT_RING  (chan, NV04_IMAGE_BLIT_OPERATION_SRCCOPY);
 417
 418         ret = nouveau_grobj_alloc(chan, handle++, NV04_GDI_RECTANGLE_TEXT,
 419                                   &ctx->rect);
 420         if (ret) {
 421                 nv04_surface_2d_takedown(&ctx);
 422                 return NULL;
 423         }
 424
 425         BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_DMA_NOTIFY, 1);
 426         OUT_RING  (chan, ctx->ntfy->handle);
 427         BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_SURFACE, 1);
 428         OUT_RING  (chan, ctx->surf2d->handle);
 429         BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_OPERATION, 1);
 430         OUT_RING  (chan, NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY);
 431         BEGIN_RING(chan, ctx->rect,
 432                          NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT, 1);
 433         OUT_RING  (chan, NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_LE);
 434
 435         switch (chan->device->chipset & 0xf0) {
 436         case 0x00:
 437         case 0x10:
 438                 class = NV04_SWIZZLED_SURFACE;
 439                 break;
 440         case 0x20:
 441                 class = NV20_SWIZZLED_SURFACE;
 442                 break;
 443         case 0x30:
 444                 class = NV30_SWIZZLED_SURFACE;
 445                 break;
 446         case 0x40:
 447         case 0x60:
 448                 class = NV40_SWIZZLED_SURFACE;
 449                 break;
 450         default:
 451                 /* Famous last words: this really can't happen.. */
 452                 assert(0);
 453                 break;
 454         }
 455
 456         ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->swzsurf);
 457         if (ret) {
 458                 nv04_surface_2d_takedown(&ctx);
 459                 return NULL;
 460         }
 461
 462         switch (chan->device->chipset & 0xf0) {
 463         case 0x10:
 464         case 0x20:
 465                 class = NV10_SCALED_IMAGE_FROM_MEMORY;
 466                 break;
 467         case 0x30:
 468                 class = NV30_SCALED_IMAGE_FROM_MEMORY;
 469                 break;
 470         case 0x40:
 471         case 0x60:
 472                 class = NV40_SCALED_IMAGE_FROM_MEMORY;
 473                 break;
 474         default:
 475                 class = NV04_SCALED_IMAGE_FROM_MEMORY;
 476                 break;
 477         }
 478
 479         ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->sifm);
 480         if (ret) {
 481                 nv04_surface_2d_takedown(&ctx);
 482                 return NULL;
 483         }
 484
 485         ctx->copy = nv04_surface_copy;
 486         ctx->fill = nv04_surface_fill;
 487         return ctx;
 488 }