src/gallium/drivers/nv04/nv04_surface_2d.c

   1 #include "pipe/p_context.h"
   2 #include "pipe/p_format.h"
   3 #include "util/u_memory.h"
   4
   5 #include "nouveau/nouveau_winsys.h"
   6 #include "nouveau/nouveau_util.h"
   7 #include "nouveau/nouveau_screen.h"
   8 #include "nv04_surface_2d.h"
   9
  10 static INLINE int
  11 nv04_surface_format(enum pipe_format format)
  12 {
  13         switch (format) {
  14         case PIPE_FORMAT_A8_UNORM:
  15                 return NV04_CONTEXT_SURFACES_2D_FORMAT_Y8;
  16         case PIPE_FORMAT_R16_SNORM:
  17         case PIPE_FORMAT_R5G6B5_UNORM:
  18                 return NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5;
  19         case PIPE_FORMAT_X8R8G8B8_UNORM:
  20         case PIPE_FORMAT_A8R8G8B8_UNORM:
  21                 return NV04_CONTEXT_SURFACES_2D_FORMAT_A8R8G8B8;
  22         case PIPE_FORMAT_Z24S8_UNORM:
  23                 return NV04_CONTEXT_SURFACES_2D_FORMAT_Y32;
  24         default:
  25                 return -1;
  26         }
  27 }
  28
  29 static INLINE int
  30 nv04_rect_format(enum pipe_format format)
  31 {
  32         switch (format) {
  33         case PIPE_FORMAT_A8_UNORM:
  34                 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
  35         case PIPE_FORMAT_R5G6B5_UNORM:
  36                 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A16R5G6B5;
  37         case PIPE_FORMAT_A8R8G8B8_UNORM:
  38         case PIPE_FORMAT_Z24S8_UNORM:
  39                 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
  40         default:
  41                 return -1;
  42         }
  43 }
  44
  45 static INLINE int
  46 nv04_scaled_image_format(enum pipe_format format)
  47 {
  48         switch (format) {
  49         case PIPE_FORMAT_A1R5G5B5_UNORM:
  50                 return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A1R5G5B5;
  51         case PIPE_FORMAT_A8R8G8B8_UNORM:
  52                 return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8;
  53         case PIPE_FORMAT_X8R8G8B8_UNORM:
  54                 return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8;
  55         case PIPE_FORMAT_R5G6B5_UNORM:
  56         case PIPE_FORMAT_R16_SNORM:
  57                 return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5;
  58         default:
  59                 return -1;
  60         }
  61 }
  62
  63 static INLINE unsigned
  64 nv04_swizzle_bits(unsigned x, unsigned y)
  65 {
  66         unsigned u = (x & 0x001) << 0 |
  67                      (x & 0x002) << 1 |
  68                      (x & 0x004) << 2 |
  69                      (x & 0x008) << 3 |
  70                      (x & 0x010) << 4 |
  71                      (x & 0x020) << 5 |
  72                      (x & 0x040) << 6 |
  73                      (x & 0x080) << 7 |
  74                      (x & 0x100) << 8 |
  75                      (x & 0x200) << 9 |
  76                      (x & 0x400) << 10 |
  77                      (x & 0x800) << 11;
  78
  79         unsigned v = (y & 0x001) << 1 |
  80                      (y & 0x002) << 2 |
  81                      (y & 0x004) << 3 |
  82                      (y & 0x008) << 4 |
  83                      (y & 0x010) << 5 |
  84                      (y & 0x020) << 6 |
  85                      (y & 0x040) << 7 |
  86                      (y & 0x080) << 8 |
  87                      (y & 0x100) << 9 |
  88                      (y & 0x200) << 10 |
  89                      (y & 0x400) << 11 |
  90                      (y & 0x800) << 12;
  91         return v | u;
  92 }
  93
  94 static int
  95 nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx,
  96                           struct pipe_surface *dst, int dx, int dy,
  97                           struct pipe_surface *src, int sx, int sy,
  98                           int w, int h)
  99 {
 100         struct nouveau_channel *chan = ctx->swzsurf->channel;
 101         struct nouveau_grobj *swzsurf = ctx->swzsurf;
 102         struct nouveau_grobj *sifm = ctx->sifm;
 103         struct nouveau_bo *src_bo = nouveau_bo(ctx->buf(src));
 104         struct nouveau_bo *dst_bo = nouveau_bo(ctx->buf(dst));
 105         const unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
 106         const unsigned max_w = 1024;
 107         const unsigned max_h = 1024;
 108         const unsigned sub_w = w > max_w ? max_w : w;
 109         const unsigned sub_h = h > max_h ? max_h : h;
 110         unsigned cx;
 111         unsigned cy;
 112
 113         /* POT or GTFO */
 114         assert(!(w & (w - 1)) && !(h & (h - 1)));
 115         /* That's the way she likes it */
 116         assert(src_pitch == ((struct nv04_surface *)dst)->pitch);
 117
 118         BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_DMA_IMAGE, 1);
 119         OUT_RELOCo(chan, dst_bo,
 120                          NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 121
 122         BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_FORMAT, 1);
 123         OUT_RING  (chan, nv04_surface_format(dst->format) |
 124                          log2i(w) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_SHIFT |
 125                          log2i(h) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_SHIFT);
 126
 127         BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE, 1);
 128         OUT_RELOCo(chan, src_bo,
 129                          NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 130         BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE, 1);
 131         OUT_RING  (chan, swzsurf->handle);
 132
 133         for (cy = 0; cy < h; cy += sub_h) {
 134           for (cx = 0; cx < w; cx += sub_w) {
 135             BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_OFFSET, 1);
 136             OUT_RELOCl(chan, dst_bo, dst->offset + nv04_swizzle_bits(cx, cy) *
 137                              dst->texture->block.size, NOUVEAU_BO_GART |
 138                              NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 139
 140             BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION, 9);
 141             OUT_RING  (chan, NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE);
 142             OUT_RING  (chan, nv04_scaled_image_format(src->format));
 143             OUT_RING  (chan, NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY);
 144             OUT_RING  (chan, 0);
 145             OUT_RING  (chan, sub_h << 16 | sub_w);
 146             OUT_RING  (chan, 0);
 147             OUT_RING  (chan, sub_h << 16 | sub_w);
 148             OUT_RING  (chan, 1 << 20);
 149             OUT_RING  (chan, 1 << 20);
 150
 151             BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_SIZE, 4);
 152             OUT_RING  (chan, sub_h << 16 | sub_w);
 153             OUT_RING  (chan, src_pitch |
 154                              NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER |
 155                              NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE);
 156             OUT_RELOCl(chan, src_bo, src->offset + cy * src_pitch +
 157                              cx * src->texture->block.size, NOUVEAU_BO_GART |
 158                              NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 159             OUT_RING  (chan, 0);
 160           }
 161         }
 162
 163         return 0;
 164 }
 165
 166 static int
 167 nv04_surface_copy_m2mf(struct nv04_surface_2d *ctx,
 168                        struct pipe_surface *dst, int dx, int dy,
 169                        struct pipe_surface *src, int sx, int sy, int w, int h)
 170 {
 171         struct nouveau_channel *chan = ctx->m2mf->channel;
 172         struct nouveau_grobj *m2mf = ctx->m2mf;
 173         struct nouveau_bo *src_bo = nouveau_bo(ctx->buf(src));
 174         struct nouveau_bo *dst_bo = nouveau_bo(ctx->buf(dst));
 175         unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
 176         unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
 177         unsigned dst_offset = dst->offset + dy * dst_pitch +
 178                               dx * dst->texture->block.size;
 179         unsigned src_offset = src->offset + sy * src_pitch +
 180                               sx * src->texture->block.size;
 181
 182         WAIT_RING (chan, 3 + ((h / 2047) + 1) * 9);
 183         BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_IN, 2);
 184         OUT_RELOCo(chan, src_bo,
 185                    NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 186         OUT_RELOCo(chan, dst_bo,
 187                    NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 188
 189         while (h) {
 190                 int count = (h > 2047) ? 2047 : h;
 191
 192                 BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
 193                 OUT_RELOCl(chan, src_bo, src_offset,
 194                            NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD);
 195                 OUT_RELOCl(chan, dst_bo, dst_offset,
 196                            NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_WR);
 197                 OUT_RING  (chan, src_pitch);
 198                 OUT_RING  (chan, dst_pitch);
 199                 OUT_RING  (chan, w * src->texture->block.size);
 200                 OUT_RING  (chan, count);
 201                 OUT_RING  (chan, 0x0101);
 202                 OUT_RING  (chan, 0);
 203
 204                 h -= count;
 205                 src_offset += src_pitch * count;
 206                 dst_offset += dst_pitch * count;
 207         }
 208
 209         return 0;
 210 }
 211
 212 static int
 213 nv04_surface_copy_blit(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
 214                        int dx, int dy, struct pipe_surface *src, int sx, int sy,
 215                        int w, int h)
 216 {
 217         struct nouveau_channel *chan = ctx->surf2d->channel;
 218         struct nouveau_grobj *surf2d = ctx->surf2d;
 219         struct nouveau_grobj *blit = ctx->blit;
 220         struct nouveau_bo *src_bo = nouveau_bo(ctx->buf(src));
 221         struct nouveau_bo *dst_bo = nouveau_bo(ctx->buf(dst));
 222         unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
 223         unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
 224         int format;
 225
 226         format = nv04_surface_format(dst->format);
 227         if (format < 0)
 228                 return 1;
 229
 230         WAIT_RING (chan, 12);
 231         BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
 232         OUT_RELOCo(chan, src_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 233         OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 234         BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
 235         OUT_RING  (chan, format);
 236         OUT_RING  (chan, (dst_pitch << 16) | src_pitch);
 237         OUT_RELOCl(chan, src_bo, src->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 238         OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 239
 240         BEGIN_RING(chan, blit, 0x0300, 3);
 241         OUT_RING  (chan, (sy << 16) | sx);
 242         OUT_RING  (chan, (dy << 16) | dx);
 243         OUT_RING  (chan, ( h << 16) |  w);
 244
 245         return 0;
 246 }
 247
 248 static void
 249 nv04_surface_copy(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
 250                   int dx, int dy, struct pipe_surface *src, int sx, int sy,
 251                   int w, int h)
 252 {
 253         unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
 254         unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
 255         int src_linear = src->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR;
 256         int dst_linear = dst->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR;
 257
 258         assert(src->format == dst->format);
 259
 260         /* Setup transfer to swizzle the texture to vram if needed */
 261         if (src_linear && !dst_linear && w > 1 && h > 1) {
 262                 nv04_surface_copy_swizzle(ctx, dst, dx, dy, src, sx, sy, w, h);
 263                 return;
 264         }
 265
 266         /* NV_CONTEXT_SURFACES_2D has buffer alignment restrictions, fallback
 267          * to NV_MEMORY_TO_MEMORY_FORMAT in this case.
 268          */
 269         if ((src->offset & 63) || (dst->offset & 63) ||
 270             (src_pitch & 63) || (dst_pitch & 63)) {
 271                 nv04_surface_copy_m2mf(ctx, dst, dx, dy, src, sx, sy, w, h);
 272                 return;
 273         }
 274
 275         nv04_surface_copy_blit(ctx, dst, dx, dy, src, sx, sy, w, h);
 276 }
 277
 278 static void
 279 nv04_surface_fill(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
 280                   int dx, int dy, int w, int h, unsigned value)
 281 {
 282         struct nouveau_channel *chan = ctx->surf2d->channel;
 283         struct nouveau_grobj *surf2d = ctx->surf2d;
 284         struct nouveau_grobj *rect = ctx->rect;
 285         struct nouveau_bo *dst_bo = nouveau_bo(ctx->buf(dst));
 286         unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
 287         int cs2d_format, gdirect_format;
 288
 289         cs2d_format = nv04_surface_format(dst->format);
 290         assert(cs2d_format >= 0);
 291
 292         gdirect_format = nv04_rect_format(dst->format);
 293         assert(gdirect_format >= 0);
 294
 295         WAIT_RING (chan, 16);
 296         BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
 297         OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 298         OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 299         BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
 300         OUT_RING  (chan, cs2d_format);
 301         OUT_RING  (chan, (dst_pitch << 16) | dst_pitch);
 302         OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 303         OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 304
 305         BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT, 1);
 306         OUT_RING  (chan, gdirect_format);
 307         BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_COLOR1_A, 1);
 308         OUT_RING  (chan, value);
 309         BEGIN_RING(chan, rect,
 310                    NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT(0), 2);
 311         OUT_RING  (chan, (dx << 16) | dy);
 312         OUT_RING  (chan, ( w << 16) |  h);
 313 }
 314
 315 void
 316 nv04_surface_2d_takedown(struct nv04_surface_2d **pctx)
 317 {
 318         struct nv04_surface_2d *ctx;
 319
 320         if (!pctx || !*pctx)
 321                 return;
 322         ctx = *pctx;
 323         *pctx = NULL;
 324
 325         nouveau_notifier_free(&ctx->ntfy);
 326         nouveau_grobj_free(&ctx->m2mf);
 327         nouveau_grobj_free(&ctx->surf2d);
 328         nouveau_grobj_free(&ctx->swzsurf);
 329         nouveau_grobj_free(&ctx->rect);
 330         nouveau_grobj_free(&ctx->blit);
 331         nouveau_grobj_free(&ctx->sifm);
 332
 333         FREE(ctx);
 334 }
 335
 336 struct nv04_surface_2d *
 337 nv04_surface_2d_init(struct nouveau_screen *screen)
 338 {
 339         struct nv04_surface_2d *ctx = CALLOC_STRUCT(nv04_surface_2d);
 340         struct nouveau_channel *chan = screen->channel;
 341         unsigned handle = 0x88000000, class;
 342         int ret;
 343
 344         if (!ctx)
 345                 return NULL;
 346
 347         ret = nouveau_notifier_alloc(chan, handle++, 1, &ctx->ntfy);
 348         if (ret) {
 349                 nv04_surface_2d_takedown(&ctx);
 350                 return NULL;
 351         }
 352
 353         ret = nouveau_grobj_alloc(chan, handle++, 0x0039, &ctx->m2mf);
 354         if (ret) {
 355                 nv04_surface_2d_takedown(&ctx);
 356                 return NULL;
 357         }
 358
 359         BEGIN_RING(chan, ctx->m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
 360         OUT_RING  (chan, ctx->ntfy->handle);
 361
 362         if (chan->device->chipset < 0x10)
 363                 class = NV04_CONTEXT_SURFACES_2D;
 364         else
 365                 class = NV10_CONTEXT_SURFACES_2D;
 366
 367         ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->surf2d);
 368         if (ret) {
 369                 nv04_surface_2d_takedown(&ctx);
 370                 return NULL;
 371         }
 372
 373         BEGIN_RING(chan, ctx->surf2d,
 374                          NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
 375         OUT_RING  (chan, chan->vram->handle);
 376         OUT_RING  (chan, chan->vram->handle);
 377
 378         if (chan->device->chipset < 0x10)
 379                 class = NV04_IMAGE_BLIT;
 380         else
 381                 class = NV12_IMAGE_BLIT;
 382
 383         ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->blit);
 384         if (ret) {
 385                 nv04_surface_2d_takedown(&ctx);
 386                 return NULL;
 387         }
 388
 389         BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_DMA_NOTIFY, 1);
 390         OUT_RING  (chan, ctx->ntfy->handle);
 391         BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_SURFACE, 1);
 392         OUT_RING  (chan, ctx->surf2d->handle);
 393         BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_OPERATION, 1);
 394         OUT_RING  (chan, NV04_IMAGE_BLIT_OPERATION_SRCCOPY);
 395
 396         ret = nouveau_grobj_alloc(chan, handle++, NV04_GDI_RECTANGLE_TEXT,
 397                                   &ctx->rect);
 398         if (ret) {
 399                 nv04_surface_2d_takedown(&ctx);
 400                 return NULL;
 401         }
 402
 403         BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_DMA_NOTIFY, 1);
 404         OUT_RING  (chan, ctx->ntfy->handle);
 405         BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_SURFACE, 1);
 406         OUT_RING  (chan, ctx->surf2d->handle);
 407         BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_OPERATION, 1);
 408         OUT_RING  (chan, NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY);
 409         BEGIN_RING(chan, ctx->rect,
 410                          NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT, 1);
 411         OUT_RING  (chan, NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_LE);
 412
 413         switch (chan->device->chipset & 0xf0) {
 414         case 0x00:
 415         case 0x10:
 416                 class = NV04_SWIZZLED_SURFACE;
 417                 break;
 418         case 0x20:
 419                 class = NV20_SWIZZLED_SURFACE;
 420                 break;
 421         case 0x30:
 422                 class = NV30_SWIZZLED_SURFACE;
 423                 break;
 424         case 0x40:
 425         case 0x60:
 426                 class = NV40_SWIZZLED_SURFACE;
 427                 break;
 428         default:
 429                 /* Famous last words: this really can't happen.. */
 430                 assert(0);
 431                 break;
 432         }
 433
 434         ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->swzsurf);
 435         if (ret) {
 436                 nv04_surface_2d_takedown(&ctx);
 437                 return NULL;
 438         }
 439
 440         switch (chan->device->chipset & 0xf0) {
 441         case 0x10:
 442         case 0x20:
 443                 class = NV10_SCALED_IMAGE_FROM_MEMORY;
 444                 break;
 445         case 0x30:
 446                 class = NV30_SCALED_IMAGE_FROM_MEMORY;
 447                 break;
 448         case 0x40:
 449         case 0x60:
 450                 class = NV40_SCALED_IMAGE_FROM_MEMORY;
 451                 break;
 452         default:
 453                 class = NV04_SCALED_IMAGE_FROM_MEMORY;
 454                 break;
 455         }
 456
 457         ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->sifm);
 458         if (ret) {
 459                 nv04_surface_2d_takedown(&ctx);
 460                 return NULL;
 461         }
 462
 463         ctx->copy = nv04_surface_copy;
 464         ctx->fill = nv04_surface_fill;
 465         return ctx;
 466 }