Merge branch 'mesa_7_5_branch' into mesa_7_6_branch
[mesa.git] / src / gallium / drivers / nv10 / nv10_prim_vbuf.c
1 /**************************************************************************
2 *
3 * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /**
29 * \file
30 * Build post-transformation, post-clipping vertex buffers and element
31 * lists by hooking into the end of the primitive pipeline and
32 * manipulating the vertex_id field in the vertex headers.
33 *
34 * XXX: work in progress
35 *
36 * \author José Fonseca <jrfonseca@tungstengraphics.com>
37 * \author Keith Whitwell <keith@tungstengraphics.com>
38 */
39
40
41 #include "util/u_debug.h"
42 #include "pipe/p_inlines.h"
43
44 #include "nv10_context.h"
45 #include "nv10_state.h"
46
47 #include "draw/draw_vbuf.h"
48
49 /**
50 * Primitive renderer for nv10.
51 */
52 struct nv10_vbuf_render {
53 struct vbuf_render base;
54
55 struct nv10_context *nv10;
56
57 /** Vertex buffer */
58 struct pipe_buffer* buffer;
59
60 /** Vertex size in bytes */
61 unsigned vertex_size;
62
63 /** Hardware primitive */
64 unsigned hwprim;
65 };
66
67
68 void nv10_vtxbuf_bind( struct nv10_context* nv10 )
69 {
70 int i;
71 for(i = 0; i < 8; i++) {
72 BEGIN_RING(celsius, NV10TCL_VERTEX_ARRAY_ATTRIB_OFFSET(i), 1);
73 OUT_RING(0/*nv10->vtxbuf*/);
74 BEGIN_RING(celsius, NV10TCL_VERTEX_ARRAY_ATTRIB_FORMAT(i) ,1);
75 OUT_RING(0/*XXX*/);
76 }
77 }
78
79 /**
80 * Basically a cast wrapper.
81 */
82 static INLINE struct nv10_vbuf_render *
83 nv10_vbuf_render( struct vbuf_render *render )
84 {
85 assert(render);
86 return (struct nv10_vbuf_render *)render;
87 }
88
89
90 static const struct vertex_info *
91 nv10_vbuf_render_get_vertex_info( struct vbuf_render *render )
92 {
93 struct nv10_vbuf_render *nv10_render = nv10_vbuf_render(render);
94 struct nv10_context *nv10 = nv10_render->nv10;
95
96 nv10_emit_hw_state(nv10);
97
98 return &nv10->vertex_info;
99 }
100
101 static boolean
102 nv10_vbuf_render_allocate_vertices( struct vbuf_render *render,
103 ushort vertex_size,
104 ushort nr_vertices )
105 {
106 struct nv10_vbuf_render *nv10_render = nv10_vbuf_render(render);
107 struct nv10_context *nv10 = nv10_render->nv10;
108 struct pipe_screen *screen = nv10->pipe.screen;
109 size_t size = (size_t)vertex_size * (size_t)nr_vertices;
110
111 assert(!nv10_render->buffer);
112 nv10_render->buffer = screen->buffer_create(screen, 64, PIPE_BUFFER_USAGE_VERTEX, size);
113
114 nv10->dirty |= NV10_NEW_VTXARRAYS;
115
116 if (nv10_render->buffer)
117 return FALSE;
118 return TRUE;
119 }
120
121 static void *
122 nv10_vbuf_render_map_vertices( struct vbuf_render *render )
123 {
124 struct nv10_vbuf_render *nv10_render = nv10_vbuf_render(render);
125 struct nv10_context *nv10 = nv10_render->nv10;
126 struct pipe_screen *pscreen = nv10->pipe.screen;
127
128 return pipe_buffer_map(pscreen, nv10_render->buffer,
129 PIPE_BUFFER_USAGE_CPU_WRITE);
130 }
131
132 static void
133 nv10_vbuf_render_unmap_vertices( struct vbuf_render *render,
134 ushort min_index,
135 ushort max_index )
136 {
137 struct nv10_vbuf_render *nv10_render = nv10_vbuf_render(render);
138 struct nv10_context *nv10 = nv10_render->nv10;
139 struct pipe_screen *pscreen = nv10->pipe.screen;
140
141 assert(!nv10_render->buffer);
142 pipe_buffer_unmap(pscreen, nv10_render->buffer);
143 }
144
145 static boolean
146 nv10_vbuf_render_set_primitive( struct vbuf_render *render,
147 unsigned prim )
148 {
149 struct nv10_vbuf_render *nv10_render = nv10_vbuf_render(render);
150 unsigned hwp = nvgl_primitive(prim);
151 if (hwp == 0)
152 return FALSE;
153
154 nv10_render->hwprim = hwp;
155 return TRUE;
156 }
157
158
159 static void
160 nv10_vbuf_render_draw( struct vbuf_render *render,
161 const ushort *indices,
162 uint nr_indices)
163 {
164 struct nv10_vbuf_render *nv10_render = nv10_vbuf_render(render);
165 struct nv10_context *nv10 = nv10_render->nv10;
166 int push, i;
167
168 nv10_emit_hw_state(nv10);
169
170 BEGIN_RING(celsius, NV10TCL_VERTEX_ARRAY_OFFSET_POS, 1);
171 OUT_RELOCl(nv10_render->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD);
172
173 BEGIN_RING(celsius, NV10TCL_VERTEX_BUFFER_BEGIN_END, 1);
174 OUT_RING(nv10_render->hwprim);
175
176 if (nr_indices & 1) {
177 BEGIN_RING(celsius, NV10TCL_VB_ELEMENT_U32, 1);
178 OUT_RING (indices[0]);
179 indices++; nr_indices--;
180 }
181
182 while (nr_indices) {
183 // XXX too big/small ? check the size
184 push = MIN2(nr_indices, 1200 * 2);
185
186 BEGIN_RING_NI(celsius, NV10TCL_VB_ELEMENT_U16, push >> 1);
187 for (i = 0; i < push; i+=2)
188 OUT_RING((indices[i+1] << 16) | indices[i]);
189
190 nr_indices -= push;
191 indices += push;
192 }
193
194 BEGIN_RING(celsius, NV10TCL_VERTEX_BUFFER_BEGIN_END, 1);
195 OUT_RING (0);
196 }
197
198
199 static void
200 nv10_vbuf_render_release_vertices( struct vbuf_render *render )
201 {
202 struct nv10_vbuf_render *nv10_render = nv10_vbuf_render(render);
203
204 assert(nv10_render->buffer);
205 pipe_buffer_reference(&nv10_render->buffer, NULL);
206 }
207
208
209 static void
210 nv10_vbuf_render_destroy( struct vbuf_render *render )
211 {
212 struct nv10_vbuf_render *nv10_render = nv10_vbuf_render(render);
213 FREE(nv10_render);
214 }
215
216
217 /**
218 * Create a new primitive render.
219 */
220 static struct vbuf_render *
221 nv10_vbuf_render_create( struct nv10_context *nv10 )
222 {
223 struct nv10_vbuf_render *nv10_render = CALLOC_STRUCT(nv10_vbuf_render);
224
225 nv10_render->nv10 = nv10;
226
227 nv10_render->base.max_vertex_buffer_bytes = 16*1024;
228 nv10_render->base.max_indices = 1024;
229 nv10_render->base.get_vertex_info = nv10_vbuf_render_get_vertex_info;
230 nv10_render->base.allocate_vertices = nv10_vbuf_render_allocate_vertices;
231 nv10_render->base.map_vertices = nv10_vbuf_render_map_vertices;
232 nv10_render->base.unmap_vertices = nv10_vbuf_render_unmap_vertices;
233 nv10_render->base.set_primitive = nv10_vbuf_render_set_primitive;
234 nv10_render->base.draw = nv10_vbuf_render_draw;
235 nv10_render->base.release_vertices = nv10_vbuf_render_release_vertices;
236 nv10_render->base.destroy = nv10_vbuf_render_destroy;
237
238 return &nv10_render->base;
239 }
240
241
242 /**
243 * Create a new primitive vbuf/render stage.
244 */
245 struct draw_stage *nv10_draw_vbuf_stage( struct nv10_context *nv10 )
246 {
247 struct vbuf_render *render;
248 struct draw_stage *stage;
249
250 render = nv10_vbuf_render_create(nv10);
251 if(!render)
252 return NULL;
253
254 stage = draw_vbuf_stage( nv10->draw, render );
255 if(!stage) {
256 render->destroy(render);
257 return NULL;
258 }
259
260 return stage;
261 }