nv10.
[mesa.git] / src / gallium / drivers / nv10 / nv10_state_emit.c
1 #include "nv10_context.h"
2 #include "nv10_state.h"
3
4 void
5 nv10_emit_hw_state(struct nv10_context *nv10)
6 {
7 int i;
8
9 if (nv10->dirty & NV10_NEW_FRAGPROG) {
10 nv10_fragprog_bind(nv10, nv10->fragprog.current);
11 /*XXX: clear NV10_NEW_FRAGPROG if no new program uploaded */
12 }
13
14 if (nv10->dirty_samplers || (nv10->dirty & NV10_NEW_FRAGPROG)) {
15 nv10_fragtex_bind(nv10);
16 nv10->dirty &= ~NV10_NEW_FRAGPROG;
17 }
18
19 if (nv10->dirty & NV10_NEW_VERTPROG) {
20 //nv10_vertprog_bind(nv10, nv10->vertprog.current);
21 nv10->dirty &= ~NV10_NEW_VERTPROG;
22 }
23
24 if (nv10->dirty & NV10_NEW_VBO) {
25
26 }
27
28 nv10->dirty_samplers = 0;
29
30 /* Emit relocs for every referenced buffer.
31 * This is to ensure the bufmgr has an accurate idea of how
32 * the buffer is used. This isn't very efficient, but we don't
33 * seem to take a significant performance hit. Will be improved
34 * at some point. Vertex arrays are emitted by nv10_vbo.c
35 */
36
37 /* Render target */
38 // XXX figre out who's who for NV10TCL_DMA_* and fill accordingly
39 // BEGIN_RING(celsius, NV10TCL_DMA_COLOR0, 1);
40 // OUT_RELOCo(nv10->rt[0], NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
41 BEGIN_RING(celsius, NV10TCL_COLOR_OFFSET, 1);
42 OUT_RELOCl(nv10->rt[0], 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
43
44 if (nv10->zeta) {
45 // XXX
46 // BEGIN_RING(celsius, NV10TCL_DMA_ZETA, 1);
47 // OUT_RELOCo(nv10->zeta, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
48 BEGIN_RING(celsius, NV10TCL_ZETA_OFFSET, 1);
49 OUT_RELOCl(nv10->zeta, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
50 /* XXX for when we allocate LMA on nv17 */
51 /* BEGIN_RING(celsius, NV10TCL_LMA_DEPTH_OFFSET, 1);
52 OUT_RELOCl(nv10->zeta+...);*/
53 }
54
55 /* Texture images */
56 for (i = 0; i < 2; i++) {
57 if (!(nv10->fp_samplers & (1 << i)))
58 continue;
59 BEGIN_RING(celsius, NV10TCL_TX_OFFSET(i), 2);
60 OUT_RELOCl(nv10->tex[i].buffer, 0, NOUVEAU_BO_VRAM |
61 NOUVEAU_BO_GART | NOUVEAU_BO_RD);
62 // XXX
63 /* OUT_RELOCd(nv10->tex[i].buffer, nv10->tex[i].format,
64 NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD |
65 NOUVEAU_BO_OR, NV10TCL_TX_FORMAT_DMA0,
66 NV10TCL_TX_FORMAT_DMA1);*/
67 }
68 }
69