1 #include "pipe/p_util.h"
3 #include "nv10_context.h"
4 #include "nv10_state.h"
6 static void nv10_state_emit_blend(struct nv10_context
* nv10
)
8 struct nv10_blend_state
*b
= nv10
->blend
;
10 BEGIN_RING(celsius
, NV10TCL_DITHER_ENABLE
, 1);
11 OUT_RING (b
->d_enable
);
13 BEGIN_RING(celsius
, NV10TCL_BLEND_FUNC_ENABLE
, 3);
14 OUT_RING (b
->b_enable
);
15 OUT_RING (b
->b_srcfunc
);
16 OUT_RING (b
->b_dstfunc
);
18 BEGIN_RING(celsius
, NV10TCL_COLOR_MASK
, 1);
22 static void nv10_state_emit_blend_color(struct nv10_context
* nv10
)
24 struct pipe_blend_color
*c
= nv10
->blend_color
;
26 BEGIN_RING(celsius
, NV10TCL_BLEND_COLOR
, 1);
27 OUT_RING ((float_to_ubyte(c
->color
[3]) << 24)|
28 (float_to_ubyte(c
->color
[0]) << 16)|
29 (float_to_ubyte(c
->color
[1]) << 8) |
30 (float_to_ubyte(c
->color
[2]) << 0));
33 static void nv10_state_emit_rast(struct nv10_context
* nv10
)
35 struct nv10_rasterizer_state
*r
= nv10
->rast
;
37 BEGIN_RING(celsius
, NV10TCL_SHADE_MODEL
, 2);
38 OUT_RING (r
->shade_model
);
39 OUT_RING (r
->line_width
);
42 BEGIN_RING(celsius
, NV10TCL_POINT_SIZE
, 1);
43 OUT_RING (r
->point_size
);
45 BEGIN_RING(celsius
, NV10TCL_POLYGON_MODE_FRONT
, 2);
46 OUT_RING (r
->poly_mode_front
);
47 OUT_RING (r
->poly_mode_back
);
50 BEGIN_RING(celsius
, NV10TCL_CULL_FACE
, 2);
51 OUT_RING (r
->cull_face
);
52 OUT_RING (r
->front_face
);
54 BEGIN_RING(celsius
, NV10TCL_LINE_SMOOTH_ENABLE
, 2);
55 OUT_RING (r
->line_smooth_en
);
56 OUT_RING (r
->poly_smooth_en
);
58 BEGIN_RING(celsius
, NV10TCL_CULL_FACE_ENABLE
, 1);
59 OUT_RING (r
->cull_face_en
);
62 static void nv10_state_emit_dsa(struct nv10_context
* nv10
)
64 struct nv10_depth_stencil_alpha_state
*d
= nv10
->dsa
;
66 BEGIN_RING(celsius
, NV10TCL_DEPTH_FUNC
, 3);
67 OUT_RINGp ((uint32_t *)&d
->depth
, 3);
68 BEGIN_RING(celsius
, NV10TCL_STENCIL_ENABLE
, 1);
69 OUT_RING (d
->stencil
.enable
);
70 BEGIN_RING(celsius
, NV10TCL_STENCIL_MASK
, 7);
71 OUT_RINGp ((uint32_t *)&(d
->stencil
.wmask
), 7);
72 BEGIN_RING(celsius
, NV10TCL_ALPHA_FUNC_ENABLE
, 3);
73 OUT_RINGp ((uint32_t *)&d
->alpha
.enabled
, 3);
76 static void nv10_state_emit_viewport(struct nv10_context
* nv10
)
78 struct pipe_viewport_state
*vpt
= nv10
->viewport
;
80 /* OUT_RINGf (vpt->translate[0]);
81 OUT_RINGf (vpt->translate[1]);
82 OUT_RINGf (vpt->translate[2]);
83 OUT_RINGf (vpt->translate[3]);*/
84 BEGIN_RING(celsius
, NV10TCL_VIEWPORT_SCALE_X
, 4);
85 OUT_RINGf (vpt
->scale
[0]);
86 OUT_RINGf (vpt
->scale
[1]);
87 OUT_RINGf (vpt
->scale
[2]);
88 OUT_RINGf (vpt
->scale
[3]);
91 static void nv10_state_emit_scissor(struct nv10_context
* nv10
)
93 // XXX this is so not working
94 /* struct pipe_scissor_state *s = nv10->scissor;
95 BEGIN_RING(celsius, NV10TCL_SCISSOR_HORIZ, 2);
96 OUT_RING (((s->maxx - s->minx) << 16) | s->minx);
97 OUT_RING (((s->maxy - s->miny) << 16) | s->miny);*/
100 static void nv10_state_emit_framebuffer(struct nv10_context
* nv10
)
102 struct pipe_framebuffer_state
* fb
= nv10
->framebuffer
;
103 struct pipe_surface
*rt
, *zeta
;
104 uint32_t rt_format
, w
, h
;
105 int colour_format
= 0, zeta_format
= 0;
107 w
= fb
->cbufs
[0]->width
;
108 h
= fb
->cbufs
[0]->height
;
109 colour_format
= fb
->cbufs
[0]->format
;
114 assert(w
== fb
->zsbuf
->width
);
115 assert(h
== fb
->zsbuf
->height
);
117 w
= fb
->zsbuf
->width
;
118 h
= fb
->zsbuf
->height
;
121 zeta_format
= fb
->zsbuf
->format
;
125 rt_format
= NV10TCL_RT_FORMAT_TYPE_LINEAR
;
127 switch (colour_format
) {
128 case PIPE_FORMAT_A8R8G8B8_UNORM
:
130 rt_format
|= NV10TCL_RT_FORMAT_COLOR_A8R8G8B8
;
132 case PIPE_FORMAT_R5G6B5_UNORM
:
133 rt_format
|= NV10TCL_RT_FORMAT_COLOR_R5G6B5
;
140 BEGIN_RING(celsius
, NV10TCL_RT_PITCH
, 1);
141 OUT_RING ( (rt
->pitch
* rt
->cpp
) | ( (zeta
->pitch
* zeta
->cpp
) << 16) );
143 BEGIN_RING(celsius
, NV10TCL_RT_PITCH
, 1);
144 OUT_RING ( (rt
->pitch
* rt
->cpp
) | ( (rt
->pitch
* rt
->cpp
) << 16) );
147 nv10
->rt
[0] = rt
->buffer
;
151 nv10
->zeta
= zeta
->buffer
;
154 BEGIN_RING(celsius
, NV10TCL_RT_HORIZ
, 3);
155 OUT_RING ((w
<< 16) | 0);
156 OUT_RING ((h
<< 16) | 0);
157 OUT_RING (rt_format
);
158 BEGIN_RING(celsius
, NV10TCL_VIEWPORT_CLIP_HORIZ(0), 2);
159 OUT_RING (((w
- 1) << 16) | 0);
160 OUT_RING (((h
- 1) << 16) | 0);
163 static void nv10_vertex_layout(struct nv10_context
*nv10
)
165 struct nv10_fragment_program
*fp
= nv10
->fragprog
.current
;
168 struct vertex_info vinfo
;
170 memset(&vinfo
, 0, sizeof(vinfo
));
172 for (i
= 0; i
< fp
->info
.num_inputs
; i
++) {
173 switch (fp
->info
.input_semantic_name
[i
]) {
174 case TGSI_SEMANTIC_POSITION
:
175 draw_emit_vertex_attr(&vinfo
, EMIT_4F
, INTERP_LINEAR
, src
++);
177 case TGSI_SEMANTIC_COLOR
:
178 draw_emit_vertex_attr(&vinfo
, EMIT_4F
, INTERP_LINEAR
, src
++);
181 case TGSI_SEMANTIC_GENERIC
:
182 draw_emit_vertex_attr(&vinfo
, EMIT_4F
, INTERP_PERSPECTIVE
, src
++);
184 case TGSI_SEMANTIC_FOG
:
185 draw_emit_vertex_attr(&vinfo
, EMIT_4F
, INTERP_PERSPECTIVE
, src
++);
189 draw_compute_vertex_size(&vinfo
);
193 nv10_emit_hw_state(struct nv10_context
*nv10
)
197 if (nv10
->dirty
& NV10_NEW_VERTPROG
) {
198 //nv10_vertprog_bind(nv10, nv10->vertprog.current);
199 nv10
->dirty
&= ~NV10_NEW_VERTPROG
;
202 if (nv10
->dirty
& NV10_NEW_FRAGPROG
) {
203 nv10_fragprog_bind(nv10
, nv10
->fragprog
.current
);
204 /*XXX: clear NV10_NEW_FRAGPROG if no new program uploaded */
205 nv10
->dirty_samplers
|= (1<<10);
206 nv10
->dirty_samplers
= 0;
209 if (nv10
->dirty_samplers
|| (nv10
->dirty
& NV10_NEW_FRAGPROG
)) {
210 nv10_fragtex_bind(nv10
);
211 nv10
->dirty
&= ~NV10_NEW_FRAGPROG
;
214 if (nv10
->dirty
& NV10_NEW_VTXARRAYS
) {
215 nv10
->dirty
&= ~NV10_NEW_VTXARRAYS
;
216 nv10_vertex_layout(nv10
);
217 nv10_vtxbuf_bind(nv10
);
220 if (nv10
->dirty
& NV10_NEW_BLEND
) {
221 nv10
->dirty
&= ~NV10_NEW_BLEND
;
222 nv10_state_emit_blend(nv10
);
225 if (nv10
->dirty
& NV10_NEW_BLENDCOL
) {
226 nv10
->dirty
&= ~NV10_NEW_BLENDCOL
;
227 nv10_state_emit_blend_color(nv10
);
230 if (nv10
->dirty
& NV10_NEW_RAST
) {
231 nv10
->dirty
&= ~NV10_NEW_RAST
;
232 nv10_state_emit_rast(nv10
);
235 if (nv10
->dirty
& NV10_NEW_DSA
) {
236 nv10
->dirty
&= ~NV10_NEW_DSA
;
237 nv10_state_emit_dsa(nv10
);
240 if (nv10
->dirty
& NV10_NEW_VIEWPORT
) {
241 nv10
->dirty
&= ~NV10_NEW_VIEWPORT
;
242 nv10_state_emit_viewport(nv10
);
245 if (nv10
->dirty
& NV10_NEW_SCISSOR
) {
246 nv10
->dirty
&= ~NV10_NEW_SCISSOR
;
247 nv10_state_emit_scissor(nv10
);
250 if (nv10
->dirty
& NV10_NEW_FRAMEBUFFER
) {
251 nv10
->dirty
&= ~NV10_NEW_FRAMEBUFFER
;
252 nv10_state_emit_framebuffer(nv10
);
255 /* Emit relocs for every referenced buffer.
256 * This is to ensure the bufmgr has an accurate idea of how
257 * the buffer is used. This isn't very efficient, but we don't
258 * seem to take a significant performance hit. Will be improved
259 * at some point. Vertex arrays are emitted by nv10_vbo.c
263 // XXX figre out who's who for NV10TCL_DMA_* and fill accordingly
264 // BEGIN_RING(celsius, NV10TCL_DMA_COLOR0, 1);
265 // OUT_RELOCo(nv10->rt[0], NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
266 BEGIN_RING(celsius
, NV10TCL_COLOR_OFFSET
, 1);
267 OUT_RELOCl(nv10
->rt
[0], 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_WR
);
271 // BEGIN_RING(celsius, NV10TCL_DMA_ZETA, 1);
272 // OUT_RELOCo(nv10->zeta, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
273 BEGIN_RING(celsius
, NV10TCL_ZETA_OFFSET
, 1);
274 OUT_RELOCl(nv10
->zeta
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_WR
);
275 /* XXX for when we allocate LMA on nv17 */
276 /* BEGIN_RING(celsius, NV10TCL_LMA_DEPTH_BUFFER_OFFSET, 1);
277 OUT_RELOCl(nv10->zeta + lma_offset);*/
281 BEGIN_RING(celsius
, NV10TCL_DMA_VTXBUF0
, 1);
282 OUT_RELOCo(nv10
->rt
[0], NOUVEAU_BO_VRAM
| NOUVEAU_BO_WR
);
283 BEGIN_RING(celsius
, NV10TCL_COLOR_OFFSET
, 1);
284 OUT_RELOCl(nv10
->rt
[0], 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_WR
);
287 for (i
= 0; i
< 2; i
++) {
288 if (!(nv10
->fp_samplers
& (1 << i
)))
290 BEGIN_RING(celsius
, NV10TCL_TX_OFFSET(i
), 1);
291 OUT_RELOCl(nv10
->tex
[i
].buffer
, 0, NOUVEAU_BO_VRAM
|
292 NOUVEAU_BO_GART
| NOUVEAU_BO_RD
);
293 BEGIN_RING(celsius
, NV10TCL_TX_FORMAT(i
), 1);
294 OUT_RELOCd(nv10
->tex
[i
].buffer
, nv10
->tex
[i
].format
,
295 NOUVEAU_BO_VRAM
| NOUVEAU_BO_GART
| NOUVEAU_BO_RD
|
296 NOUVEAU_BO_OR
, NV10TCL_TX_FORMAT_DMA0
,
297 NV10TCL_TX_FORMAT_DMA1
);