1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
5 #include "pipe/p_shader_tokens.h"
6 #include "tgsi/tgsi_parse.h"
7 #include "tgsi/tgsi_dump.h"
9 #include "nv20_context.h"
10 #include "nv20_state.h"
12 /* TODO (at least...):
13 * 1. Indexed consts + ARL
14 * 2. Arb. swz/negation
15 * 3. NV_vp11, NV_vp2, NV_vp3 features
16 * - extra arith opcodes
32 #define MASK_ALL (MASK_X|MASK_Y|MASK_Z|MASK_W)
35 #include "nv20_shader.h"
37 #define swz(s,x,y,z,w) nv20_sr_swz((s), SWZ_##x, SWZ_##y, SWZ_##z, SWZ_##w)
38 #define neg(s) nv20_sr_neg((s))
39 #define abs(s) nv20_sr_abs((s))
42 struct nv20_vertex_program
*vp
;
44 struct nv20_vertex_program_exec
*vpi
;
46 unsigned output_map
[PIPE_MAX_SHADER_OUTPUTS
];
51 struct nv20_sreg
*imm
;
55 static struct nv20_sreg
56 temp(struct nv20_vpc
*vpc
)
60 idx
= vpc
->temp_temp_count
++;
61 idx
+= vpc
->high_temp
+ 1;
62 return nv20_sr(NV30SR_TEMP
, idx
);
65 static struct nv20_sreg
66 constant(struct nv20_vpc
*vpc
, int pipe
, float x
, float y
, float z
, float w
)
68 struct nv20_vertex_program
*vp
= vpc
->vp
;
69 struct nv20_vertex_program_data
*vpd
;
73 for (idx
= 0; idx
< vp
->nr_consts
; idx
++) {
74 if (vp
->consts
[idx
].index
== pipe
)
75 return nv20_sr(NV30SR_CONST
, idx
);
79 idx
= vp
->nr_consts
++;
80 vp
->consts
= realloc(vp
->consts
, sizeof(*vpd
) * vp
->nr_consts
);
81 vpd
= &vp
->consts
[idx
];
88 return nv20_sr(NV30SR_CONST
, idx
);
91 #define arith(cc,s,o,d,m,s0,s1,s2) \
92 nv20_vp_arith((cc), (s), NV30_VP_INST_##o, (d), (m), (s0), (s1), (s2))
95 emit_src(struct nv20_vpc
*vpc
, uint32_t *hw
, int pos
, struct nv20_sreg src
)
97 struct nv20_vertex_program
*vp
= vpc
->vp
;
102 sr
|= (NV30_VP_SRC_REG_TYPE_TEMP
<< NV30_VP_SRC_REG_TYPE_SHIFT
);
103 sr
|= (src
.index
<< NV30_VP_SRC_TEMP_SRC_SHIFT
);
106 sr
|= (NV30_VP_SRC_REG_TYPE_INPUT
<<
107 NV30_VP_SRC_REG_TYPE_SHIFT
);
108 vp
->ir
|= (1 << src
.index
);
109 hw
[1] |= (src
.index
<< NV30_VP_INST_INPUT_SRC_SHIFT
);
112 sr
|= (NV30_VP_SRC_REG_TYPE_CONST
<<
113 NV30_VP_SRC_REG_TYPE_SHIFT
);
114 assert(vpc
->vpi
->const_index
== -1 ||
115 vpc
->vpi
->const_index
== src
.index
);
116 vpc
->vpi
->const_index
= src
.index
;
119 sr
|= (NV30_VP_SRC_REG_TYPE_INPUT
<<
120 NV30_VP_SRC_REG_TYPE_SHIFT
);
127 sr
|= NV30_VP_SRC_NEGATE
;
130 hw
[0] |= (1 << (21 + pos
));
132 sr
|= ((src
.swz
[0] << NV30_VP_SRC_SWZ_X_SHIFT
) |
133 (src
.swz
[1] << NV30_VP_SRC_SWZ_Y_SHIFT
) |
134 (src
.swz
[2] << NV30_VP_SRC_SWZ_Z_SHIFT
) |
135 (src
.swz
[3] << NV30_VP_SRC_SWZ_W_SHIFT
));
146 hw
[1] |= ((sr
& NV30_VP_SRC0_HIGH_MASK
) >>
147 NV30_VP_SRC0_HIGH_SHIFT
) << NV30_VP_INST_SRC0H_SHIFT
;
148 hw
[2] |= (sr
& NV30_VP_SRC0_LOW_MASK
) <<
149 NV30_VP_INST_SRC0L_SHIFT
;
152 hw
[2] |= sr
<< NV30_VP_INST_SRC1_SHIFT
;
155 hw
[2] |= ((sr
& NV30_VP_SRC2_HIGH_MASK
) >>
156 NV30_VP_SRC2_HIGH_SHIFT
) << NV30_VP_INST_SRC2H_SHIFT
;
157 hw
[3] |= (sr
& NV30_VP_SRC2_LOW_MASK
) <<
158 NV30_VP_INST_SRC2L_SHIFT
;
166 emit_dst(struct nv20_vpc
*vpc
, uint32_t *hw
, int slot
, struct nv20_sreg dst
)
168 struct nv20_vertex_program
*vp
= vpc
->vp
;
172 hw
[0] |= (dst
.index
<< NV30_VP_INST_DEST_TEMP_ID_SHIFT
);
176 case NV30_VP_INST_DEST_COL0
: vp
->or |= (1 << 0); break;
177 case NV30_VP_INST_DEST_COL1
: vp
->or |= (1 << 1); break;
178 case NV30_VP_INST_DEST_BFC0
: vp
->or |= (1 << 2); break;
179 case NV30_VP_INST_DEST_BFC1
: vp
->or |= (1 << 3); break;
180 case NV30_VP_INST_DEST_FOGC
: vp
->or |= (1 << 4); break;
181 case NV30_VP_INST_DEST_PSZ
: vp
->or |= (1 << 5); break;
182 case NV30_VP_INST_DEST_TC(0): vp
->or |= (1 << 14); break;
183 case NV30_VP_INST_DEST_TC(1): vp
->or |= (1 << 15); break;
184 case NV30_VP_INST_DEST_TC(2): vp
->or |= (1 << 16); break;
185 case NV30_VP_INST_DEST_TC(3): vp
->or |= (1 << 17); break;
186 case NV30_VP_INST_DEST_TC(4): vp
->or |= (1 << 18); break;
187 case NV30_VP_INST_DEST_TC(5): vp
->or |= (1 << 19); break;
188 case NV30_VP_INST_DEST_TC(6): vp
->or |= (1 << 20); break;
189 case NV30_VP_INST_DEST_TC(7): vp
->or |= (1 << 21); break;
194 hw
[3] |= (dst
.index
<< NV30_VP_INST_DEST_SHIFT
);
195 hw
[0] |= NV30_VP_INST_VEC_DEST_TEMP_MASK
| (1<<20);
197 /*XXX: no way this is entirely correct, someone needs to
198 * figure out what exactly it is.
208 nv20_vp_arith(struct nv20_vpc
*vpc
, int slot
, int op
,
209 struct nv20_sreg dst
, int mask
,
210 struct nv20_sreg s0
, struct nv20_sreg s1
,
213 struct nv20_vertex_program
*vp
= vpc
->vp
;
216 vp
->insns
= realloc(vp
->insns
, ++vp
->nr_insns
* sizeof(*vpc
->vpi
));
217 vpc
->vpi
= &vp
->insns
[vp
->nr_insns
- 1];
218 memset(vpc
->vpi
, 0, sizeof(*vpc
->vpi
));
219 vpc
->vpi
->const_index
= -1;
223 hw
[0] |= (NV30_VP_INST_COND_TR
<< NV30_VP_INST_COND_SHIFT
);
224 hw
[0] |= ((0 << NV30_VP_INST_COND_SWZ_X_SHIFT
) |
225 (1 << NV30_VP_INST_COND_SWZ_Y_SHIFT
) |
226 (2 << NV30_VP_INST_COND_SWZ_Z_SHIFT
) |
227 (3 << NV30_VP_INST_COND_SWZ_W_SHIFT
));
229 hw
[1] |= (op
<< NV30_VP_INST_VEC_OPCODE_SHIFT
);
230 // hw[3] |= NV30_VP_INST_SCA_DEST_TEMP_MASK;
231 // hw[3] |= (mask << NV30_VP_INST_VEC_WRITEMASK_SHIFT);
233 if (dst
.type
== NV30SR_OUTPUT
) {
235 hw
[3] |= (mask
<< NV30_VP_INST_SDEST_WRITEMASK_SHIFT
);
237 hw
[3] |= (mask
<< NV30_VP_INST_VDEST_WRITEMASK_SHIFT
);
240 hw
[3] |= (mask
<< NV30_VP_INST_STEMP_WRITEMASK_SHIFT
);
242 hw
[3] |= (mask
<< NV30_VP_INST_VTEMP_WRITEMASK_SHIFT
);
245 emit_dst(vpc
, hw
, slot
, dst
);
246 emit_src(vpc
, hw
, 0, s0
);
247 emit_src(vpc
, hw
, 1, s1
);
248 emit_src(vpc
, hw
, 2, s2
);
251 static INLINE
struct nv20_sreg
252 tgsi_src(struct nv20_vpc
*vpc
, const struct tgsi_full_src_register
*fsrc
) {
253 struct nv20_sreg src
;
255 switch (fsrc
->SrcRegister
.File
) {
256 case TGSI_FILE_INPUT
:
257 src
= nv20_sr(NV30SR_INPUT
, fsrc
->SrcRegister
.Index
);
259 case TGSI_FILE_CONSTANT
:
260 src
= constant(vpc
, fsrc
->SrcRegister
.Index
, 0, 0, 0, 0);
262 case TGSI_FILE_IMMEDIATE
:
263 src
= vpc
->imm
[fsrc
->SrcRegister
.Index
];
265 case TGSI_FILE_TEMPORARY
:
266 if (vpc
->high_temp
< fsrc
->SrcRegister
.Index
)
267 vpc
->high_temp
= fsrc
->SrcRegister
.Index
;
268 src
= nv20_sr(NV30SR_TEMP
, fsrc
->SrcRegister
.Index
);
271 NOUVEAU_ERR("bad src file\n");
275 src
.abs
= fsrc
->SrcRegisterExtMod
.Absolute
;
276 src
.negate
= fsrc
->SrcRegister
.Negate
;
277 src
.swz
[0] = fsrc
->SrcRegister
.SwizzleX
;
278 src
.swz
[1] = fsrc
->SrcRegister
.SwizzleY
;
279 src
.swz
[2] = fsrc
->SrcRegister
.SwizzleZ
;
280 src
.swz
[3] = fsrc
->SrcRegister
.SwizzleW
;
284 static INLINE
struct nv20_sreg
285 tgsi_dst(struct nv20_vpc
*vpc
, const struct tgsi_full_dst_register
*fdst
) {
286 struct nv20_sreg dst
;
288 switch (fdst
->DstRegister
.File
) {
289 case TGSI_FILE_OUTPUT
:
290 dst
= nv20_sr(NV30SR_OUTPUT
,
291 vpc
->output_map
[fdst
->DstRegister
.Index
]);
294 case TGSI_FILE_TEMPORARY
:
295 dst
= nv20_sr(NV30SR_TEMP
, fdst
->DstRegister
.Index
);
296 if (vpc
->high_temp
< dst
.index
)
297 vpc
->high_temp
= dst
.index
;
300 NOUVEAU_ERR("bad dst file\n");
312 if (tgsi
& TGSI_WRITEMASK_X
) mask
|= MASK_X
;
313 if (tgsi
& TGSI_WRITEMASK_Y
) mask
|= MASK_Y
;
314 if (tgsi
& TGSI_WRITEMASK_Z
) mask
|= MASK_Z
;
315 if (tgsi
& TGSI_WRITEMASK_W
) mask
|= MASK_W
;
320 nv20_vertprog_parse_instruction(struct nv20_vpc
*vpc
,
321 const struct tgsi_full_instruction
*finst
)
323 struct nv20_sreg src
[3], dst
, tmp
;
324 struct nv20_sreg none
= nv20_sr(NV30SR_NONE
, 0);
326 int ai
= -1, ci
= -1;
329 if (finst
->Instruction
.Opcode
== TGSI_OPCODE_END
)
332 vpc
->temp_temp_count
= 0;
333 for (i
= 0; i
< finst
->Instruction
.NumSrcRegs
; i
++) {
334 const struct tgsi_full_src_register
*fsrc
;
336 fsrc
= &finst
->FullSrcRegisters
[i
];
337 if (fsrc
->SrcRegister
.File
== TGSI_FILE_TEMPORARY
) {
338 src
[i
] = tgsi_src(vpc
, fsrc
);
342 for (i
= 0; i
< finst
->Instruction
.NumSrcRegs
; i
++) {
343 const struct tgsi_full_src_register
*fsrc
;
345 fsrc
= &finst
->FullSrcRegisters
[i
];
346 switch (fsrc
->SrcRegister
.File
) {
347 case TGSI_FILE_INPUT
:
348 if (ai
== -1 || ai
== fsrc
->SrcRegister
.Index
) {
349 ai
= fsrc
->SrcRegister
.Index
;
350 src
[i
] = tgsi_src(vpc
, fsrc
);
353 arith(vpc
, 0, OP_MOV
, src
[i
], MASK_ALL
,
354 tgsi_src(vpc
, fsrc
), none
, none
);
357 /*XXX: index comparison is broken now that consts come from
358 * two different register files.
360 case TGSI_FILE_CONSTANT
:
361 case TGSI_FILE_IMMEDIATE
:
362 if (ci
== -1 || ci
== fsrc
->SrcRegister
.Index
) {
363 ci
= fsrc
->SrcRegister
.Index
;
364 src
[i
] = tgsi_src(vpc
, fsrc
);
367 arith(vpc
, 0, OP_MOV
, src
[i
], MASK_ALL
,
368 tgsi_src(vpc
, fsrc
), none
, none
);
371 case TGSI_FILE_TEMPORARY
:
375 NOUVEAU_ERR("bad src file\n");
380 dst
= tgsi_dst(vpc
, &finst
->FullDstRegisters
[0]);
381 mask
= tgsi_mask(finst
->FullDstRegisters
[0].DstRegister
.WriteMask
);
383 switch (finst
->Instruction
.Opcode
) {
384 case TGSI_OPCODE_ABS
:
385 arith(vpc
, 0, OP_MOV
, dst
, mask
, abs(src
[0]), none
, none
);
387 case TGSI_OPCODE_ADD
:
388 arith(vpc
, 0, OP_ADD
, dst
, mask
, src
[0], none
, src
[1]);
390 case TGSI_OPCODE_ARL
:
391 arith(vpc
, 0, OP_ARL
, dst
, mask
, src
[0], none
, none
);
393 case TGSI_OPCODE_DP3
:
394 arith(vpc
, 0, OP_DP3
, dst
, mask
, src
[0], src
[1], none
);
396 case TGSI_OPCODE_DP4
:
397 arith(vpc
, 0, OP_DP4
, dst
, mask
, src
[0], src
[1], none
);
399 case TGSI_OPCODE_DPH
:
400 arith(vpc
, 0, OP_DPH
, dst
, mask
, src
[0], src
[1], none
);
402 case TGSI_OPCODE_DST
:
403 arith(vpc
, 0, OP_DST
, dst
, mask
, src
[0], src
[1], none
);
405 case TGSI_OPCODE_EX2
:
406 arith(vpc
, 1, OP_EX2
, dst
, mask
, none
, none
, src
[0]);
408 case TGSI_OPCODE_EXP
:
409 arith(vpc
, 1, OP_EXP
, dst
, mask
, none
, none
, src
[0]);
411 case TGSI_OPCODE_FLR
:
412 arith(vpc
, 0, OP_FLR
, dst
, mask
, src
[0], none
, none
);
414 case TGSI_OPCODE_FRC
:
415 arith(vpc
, 0, OP_FRC
, dst
, mask
, src
[0], none
, none
);
417 case TGSI_OPCODE_LG2
:
418 arith(vpc
, 1, OP_LG2
, dst
, mask
, none
, none
, src
[0]);
420 case TGSI_OPCODE_LIT
:
421 arith(vpc
, 1, OP_LIT
, dst
, mask
, none
, none
, src
[0]);
423 case TGSI_OPCODE_LOG
:
424 arith(vpc
, 1, OP_LOG
, dst
, mask
, none
, none
, src
[0]);
426 case TGSI_OPCODE_MAD
:
427 arith(vpc
, 0, OP_MAD
, dst
, mask
, src
[0], src
[1], src
[2]);
429 case TGSI_OPCODE_MAX
:
430 arith(vpc
, 0, OP_MAX
, dst
, mask
, src
[0], src
[1], none
);
432 case TGSI_OPCODE_MIN
:
433 arith(vpc
, 0, OP_MIN
, dst
, mask
, src
[0], src
[1], none
);
435 case TGSI_OPCODE_MOV
:
436 arith(vpc
, 0, OP_MOV
, dst
, mask
, src
[0], none
, none
);
438 case TGSI_OPCODE_MUL
:
439 arith(vpc
, 0, OP_MUL
, dst
, mask
, src
[0], src
[1], none
);
441 case TGSI_OPCODE_POW
:
443 arith(vpc
, 1, OP_LG2
, tmp
, MASK_X
, none
, none
,
444 swz(src
[0], X
, X
, X
, X
));
445 arith(vpc
, 0, OP_MUL
, tmp
, MASK_X
, swz(tmp
, X
, X
, X
, X
),
446 swz(src
[1], X
, X
, X
, X
), none
);
447 arith(vpc
, 1, OP_EX2
, dst
, mask
, none
, none
,
448 swz(tmp
, X
, X
, X
, X
));
450 case TGSI_OPCODE_RCP
:
451 arith(vpc
, 1, OP_RCP
, dst
, mask
, none
, none
, src
[0]);
453 case TGSI_OPCODE_RET
:
455 case TGSI_OPCODE_RSQ
:
456 arith(vpc
, 1, OP_RSQ
, dst
, mask
, none
, none
, src
[0]);
458 case TGSI_OPCODE_SGE
:
459 arith(vpc
, 0, OP_SGE
, dst
, mask
, src
[0], src
[1], none
);
461 case TGSI_OPCODE_SGT
:
462 arith(vpc
, 0, OP_SGT
, dst
, mask
, src
[0], src
[1], none
);
464 case TGSI_OPCODE_SLT
:
465 arith(vpc
, 0, OP_SLT
, dst
, mask
, src
[0], src
[1], none
);
467 case TGSI_OPCODE_SUB
:
468 arith(vpc
, 0, OP_ADD
, dst
, mask
, src
[0], none
, neg(src
[1]));
470 case TGSI_OPCODE_XPD
:
472 arith(vpc
, 0, OP_MUL
, tmp
, mask
,
473 swz(src
[0], Z
, X
, Y
, Y
), swz(src
[1], Y
, Z
, X
, X
), none
);
474 arith(vpc
, 0, OP_MAD
, dst
, (mask
& ~MASK_W
),
475 swz(src
[0], Y
, Z
, X
, X
), swz(src
[1], Z
, X
, Y
, Y
),
479 NOUVEAU_ERR("invalid opcode %d\n", finst
->Instruction
.Opcode
);
487 nv20_vertprog_parse_decl_output(struct nv20_vpc
*vpc
,
488 const struct tgsi_full_declaration
*fdec
)
492 switch (fdec
->Semantic
.SemanticName
) {
493 case TGSI_SEMANTIC_POSITION
:
494 hw
= NV30_VP_INST_DEST_POS
;
496 case TGSI_SEMANTIC_COLOR
:
497 if (fdec
->Semantic
.SemanticIndex
== 0) {
498 hw
= NV30_VP_INST_DEST_COL0
;
500 if (fdec
->Semantic
.SemanticIndex
== 1) {
501 hw
= NV30_VP_INST_DEST_COL1
;
503 NOUVEAU_ERR("bad colour semantic index\n");
507 case TGSI_SEMANTIC_BCOLOR
:
508 if (fdec
->Semantic
.SemanticIndex
== 0) {
509 hw
= NV30_VP_INST_DEST_BFC0
;
511 if (fdec
->Semantic
.SemanticIndex
== 1) {
512 hw
= NV30_VP_INST_DEST_BFC1
;
514 NOUVEAU_ERR("bad bcolour semantic index\n");
518 case TGSI_SEMANTIC_FOG
:
519 hw
= NV30_VP_INST_DEST_FOGC
;
521 case TGSI_SEMANTIC_PSIZE
:
522 hw
= NV30_VP_INST_DEST_PSZ
;
524 case TGSI_SEMANTIC_GENERIC
:
525 if (fdec
->Semantic
.SemanticIndex
<= 7) {
526 hw
= NV30_VP_INST_DEST_TC(fdec
->Semantic
.SemanticIndex
);
528 NOUVEAU_ERR("bad generic semantic index\n");
533 NOUVEAU_ERR("bad output semantic\n");
537 vpc
->output_map
[fdec
->DeclarationRange
.First
] = hw
;
542 nv20_vertprog_prepare(struct nv20_vpc
*vpc
)
544 struct tgsi_parse_context p
;
547 tgsi_parse_init(&p
, vpc
->vp
->pipe
.tokens
);
548 while (!tgsi_parse_end_of_tokens(&p
)) {
549 const union tgsi_full_token
*tok
= &p
.FullToken
;
551 tgsi_parse_token(&p
);
552 switch(tok
->Token
.Type
) {
553 case TGSI_TOKEN_TYPE_IMMEDIATE
:
563 vpc
->imm
= CALLOC(nr_imm
, sizeof(struct nv20_sreg
));
571 nv20_vertprog_translate(struct nv20_context
*nv20
,
572 struct nv20_vertex_program
*vp
)
574 struct tgsi_parse_context parse
;
575 struct nv20_vpc
*vpc
= NULL
;
577 tgsi_dump(vp
->pipe
.tokens
,0);
579 vpc
= CALLOC(1, sizeof(struct nv20_vpc
));
585 if (!nv20_vertprog_prepare(vpc
)) {
590 tgsi_parse_init(&parse
, vp
->pipe
.tokens
);
592 while (!tgsi_parse_end_of_tokens(&parse
)) {
593 tgsi_parse_token(&parse
);
595 switch (parse
.FullToken
.Token
.Type
) {
596 case TGSI_TOKEN_TYPE_DECLARATION
:
598 const struct tgsi_full_declaration
*fdec
;
599 fdec
= &parse
.FullToken
.FullDeclaration
;
600 switch (fdec
->Declaration
.File
) {
601 case TGSI_FILE_OUTPUT
:
602 if (!nv20_vertprog_parse_decl_output(vpc
, fdec
))
610 case TGSI_TOKEN_TYPE_IMMEDIATE
:
612 const struct tgsi_full_immediate
*imm
;
614 imm
= &parse
.FullToken
.FullImmediate
;
615 assert(imm
->Immediate
.DataType
== TGSI_IMM_FLOAT32
);
616 // assert(imm->Immediate.Size == 4);
617 vpc
->imm
[vpc
->nr_imm
++] =
619 imm
->u
.ImmediateFloat32
[0].Float
,
620 imm
->u
.ImmediateFloat32
[1].Float
,
621 imm
->u
.ImmediateFloat32
[2].Float
,
622 imm
->u
.ImmediateFloat32
[3].Float
);
625 case TGSI_TOKEN_TYPE_INSTRUCTION
:
627 const struct tgsi_full_instruction
*finst
;
628 finst
= &parse
.FullToken
.FullInstruction
;
629 if (!nv20_vertprog_parse_instruction(vpc
, finst
))
638 vp
->insns
[vp
->nr_insns
- 1].data
[3] |= NV30_VP_INST_LAST
;
639 vp
->translated
= TRUE
;
641 tgsi_parse_free(&parse
);
646 nv20_vertprog_validate(struct nv20_context
*nv20
)
648 struct nouveau_winsys
*nvws
= nv20
->nvws
;
649 struct pipe_winsys
*ws
= nv20
->pipe
.winsys
;
650 struct nouveau_grobj
*rankine
= nv20
->screen
->rankine
;
651 struct nv20_vertex_program
*vp
;
652 struct pipe_buffer
*constbuf
;
653 boolean upload_code
= FALSE
, upload_data
= FALSE
;
657 constbuf
= nv20
->constbuf
[PIPE_SHADER_VERTEX
];
659 /* Translate TGSI shader into hw bytecode */
660 if (!vp
->translated
) {
661 nv20_vertprog_translate(nv20
, vp
);
666 /* Allocate hw vtxprog exec slots */
668 struct nouveau_resource
*heap
= nv20
->screen
->vp_exec_heap
;
669 struct nouveau_stateobj
*so
;
670 uint vplen
= vp
->nr_insns
;
672 if (nvws
->res_alloc(heap
, vplen
, vp
, &vp
->exec
)) {
673 while (heap
->next
&& heap
->size
< vplen
) {
674 struct nv20_vertex_program
*evict
;
676 evict
= heap
->next
->priv
;
677 nvws
->res_free(&evict
->exec
);
680 if (nvws
->res_alloc(heap
, vplen
, vp
, &vp
->exec
))
685 so_method(so
, rankine
, NV34TCL_VP_START_FROM_ID
, 1);
686 so_data (so
, vp
->exec
->start
);
692 /* Allocate hw vtxprog const slots */
693 if (vp
->nr_consts
&& !vp
->data
) {
694 struct nouveau_resource
*heap
= nv20
->screen
->vp_data_heap
;
696 if (nvws
->res_alloc(heap
, vp
->nr_consts
, vp
, &vp
->data
)) {
697 while (heap
->next
&& heap
->size
< vp
->nr_consts
) {
698 struct nv20_vertex_program
*evict
;
700 evict
= heap
->next
->priv
;
701 nvws
->res_free(&evict
->data
);
704 if (nvws
->res_alloc(heap
, vp
->nr_consts
, vp
, &vp
->data
))
708 /*XXX: handle this some day */
709 assert(vp
->data
->start
>= vp
->data_start_min
);
712 if (vp
->data_start
!= vp
->data
->start
)
716 /* If exec or data segments moved we need to patch the program to
717 * fixup offsets and register IDs.
719 if (vp
->exec_start
!= vp
->exec
->start
) {
720 for (i
= 0; i
< vp
->nr_insns
; i
++) {
721 struct nv20_vertex_program_exec
*vpi
= &vp
->insns
[i
];
723 if (vpi
->has_branch_offset
) {
728 vp
->exec_start
= vp
->exec
->start
;
731 if (vp
->nr_consts
&& vp
->data_start
!= vp
->data
->start
) {
732 for (i
= 0; i
< vp
->nr_insns
; i
++) {
733 struct nv20_vertex_program_exec
*vpi
= &vp
->insns
[i
];
735 if (vpi
->const_index
>= 0) {
736 vpi
->data
[1] &= ~NV30_VP_INST_CONST_SRC_MASK
;
738 (vpi
->const_index
+ vp
->data
->start
) <<
739 NV30_VP_INST_CONST_SRC_SHIFT
;
744 vp
->data_start
= vp
->data
->start
;
747 /* Update + Upload constant values */
752 map
= ws
->buffer_map(ws
, constbuf
,
753 PIPE_BUFFER_USAGE_CPU_READ
);
756 for (i
= 0; i
< vp
->nr_consts
; i
++) {
757 struct nv20_vertex_program_data
*vpd
= &vp
->consts
[i
];
759 if (vpd
->index
>= 0) {
761 !memcmp(vpd
->value
, &map
[vpd
->index
* 4],
764 memcpy(vpd
->value
, &map
[vpd
->index
* 4],
768 BEGIN_RING(rankine
, NV34TCL_VP_UPLOAD_CONST_ID
, 5);
769 OUT_RING (i
+ vp
->data
->start
);
770 OUT_RINGp ((uint32_t *)vpd
->value
, 4);
774 ws
->buffer_unmap(ws
, constbuf
);
781 for (i
= 0; i
< vp
->nr_insns
; i
++) {
782 NOUVEAU_MSG("VP inst %d: 0x%08x 0x%08x 0x%08x 0x%08x\n",
783 i
, vp
->insns
[i
].data
[0], vp
->insns
[i
].data
[1],
784 vp
->insns
[i
].data
[2], vp
->insns
[i
].data
[3]);
787 BEGIN_RING(rankine
, NV34TCL_VP_UPLOAD_FROM_ID
, 1);
788 OUT_RING (vp
->exec
->start
);
789 for (i
= 0; i
< vp
->nr_insns
; i
++) {
790 BEGIN_RING(rankine
, NV34TCL_VP_UPLOAD_INST(0), 4);
791 OUT_RINGp (vp
->insns
[i
].data
, 4);
795 if (vp
->so
!= nv20
->state
.hw
[NV30_STATE_VERTPROG
]) {
796 so_ref(vp
->so
, &nv20
->state
.hw
[NV30_STATE_VERTPROG
]);
804 nv20_vertprog_destroy(struct nv20_context
*nv20
, struct nv20_vertex_program
*vp
)
806 struct nouveau_winsys
*nvws
= nv20
->screen
->nvws
;
808 vp
->translated
= FALSE
;
822 nvws
->res_free(&vp
->exec
);
824 nvws
->res_free(&vp
->data
);
826 vp
->data_start_min
= 0;
829 so_ref(NULL
, &vp
->so
);
832 struct nv20_state_entry nv20_state_vertprog
= {
833 .validate
= nv20_vertprog_validate
,
835 .pipe
= NV30_NEW_VERTPROG
/*| NV30_NEW_UCP*/,
836 .hw
= NV30_STATE_VERTPROG
,